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2024-05-14 bedbef8ad3e75a304af6361af235302bcc61d06b 
 kernel/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * OMAP5 HDMI CORE IP driver library
34  *
....@@ -7,18 +8,6 @@
78  *	Mythri pk
89  *	Archit Taneja <archit@ti.com>
910  *	Tomi Valkeinen <tomi.valkeinen@ti.com>
10
- *
11
- * This program is free software; you can redistribute it and/or modify it
12
- * under the terms of the GNU General Public License version 2 as published by
13
- * the Free Software Foundation.
14
- *
15
- * This program is distributed in the hope that it will be useful, but WITHOUT
16
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
- * more details.
19
- *
20
- * You should have received a copy of the GNU General Public License along with
21
- * this program.  If not, see <http://www.gnu.org/licenses/>.
2211  */
2312 
2413 #include <linux/kernel.h>
....@@ -34,24 +23,12 @@
3423 
3524 #include "hdmi5_core.h"
3625 
37
-/* only 24 bit color depth used for now */
38
-static const struct csc_table csc_table_deepcolor[] = {
39
-	/* HDMI_DEEP_COLOR_24BIT */
40
-	[0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, },
41
-	/* HDMI_DEEP_COLOR_30BIT */
42
-	[1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, },
43
-	/* HDMI_DEEP_COLOR_36BIT */
44
-	[2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, },
45
-	/* FULL RANGE */
46
-	[3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, },
47
-};
48
-
49
-static void hdmi_core_ddc_init(struct hdmi_core_data *core)
26
+void hdmi5_core_ddc_init(struct hdmi_core_data *core)
5027 {
5128 	void __iomem *base = core->base;
5229 	const unsigned long long iclk = 266000000;	/* DSS L3 ICLK */
53
-	const unsigned int ss_scl_high = 4600;		/* ns */
54
-	const unsigned int ss_scl_low = 5400;		/* ns */
30
+	const unsigned int ss_scl_high = 4700;		/* ns */
31
+	const unsigned int ss_scl_low = 5500;		/* ns */
5532 	const unsigned int fs_scl_high = 600;		/* ns */
5633 	const unsigned int fs_scl_low = 1300;		/* ns */
5734 	const unsigned int sda_hold = 1000;		/* ns */
....@@ -125,7 +102,7 @@
125102 	REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2);
126103 }
127104 
128
-static void hdmi_core_ddc_uninit(struct hdmi_core_data *core)
105
+void hdmi5_core_ddc_uninit(struct hdmi_core_data *core)
129106 {
130107 	void __iomem *base = core->base;
131108 
....@@ -135,14 +112,14 @@
135112 	REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
136113 }
137114 
138
-static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext)
115
+int hdmi5_core_ddc_read(void *data, u8 *buf, unsigned int block, size_t len)
139116 {
117
+	struct hdmi_core_data *core = data;
140118 	void __iomem *base = core->base;
141119 	u8 cur_addr;
142
-	char checksum = 0;
143120 	const int retries = 1000;
144
-	u8 seg_ptr = ext / 2;
145
-	u8 edidbase = ((ext % 2) * 0x80);
121
+	u8 seg_ptr = block / 2;
122
+	u8 edidbase = ((block % 2) * EDID_LENGTH);
146123 
147124 	REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0);
148125 
....@@ -150,7 +127,7 @@
150127 	 * TODO: We use polling here, although we probably should use proper
151128 	 * interrupts.
152129 	 */
153
-	for (cur_addr = 0; cur_addr < 128; ++cur_addr) {
130
+	for (cur_addr = 0; cur_addr < len; ++cur_addr) {
154131 		int i;
155132 
156133 		/* clear ERROR and DONE */
....@@ -187,43 +164,11 @@
187164 			return -EIO;
188165 		}
189166 
190
-		pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
191
-		checksum += pedid[cur_addr];
167
+		buf[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
192168 	}
193169 
194170 	return 0;
195171 
196
-}
197
-
198
-int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
199
-{
200
-	int r, n, i;
201
-	int max_ext_blocks = (len / 128) - 1;
202
-
203
-	if (len < 128)
204
-		return -EINVAL;
205
-
206
-	hdmi_core_ddc_init(core);
207
-
208
-	r = hdmi_core_ddc_edid(core, edid, 0);
209
-	if (r)
210
-		goto out;
211
-
212
-	n = edid[0x7e];
213
-
214
-	if (n > max_ext_blocks)
215
-		n = max_ext_blocks;
216
-
217
-	for (i = 1; i <= n; i++) {
218
-		r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i);
219
-		if (r)
220
-			goto out;
221
-	}
222
-
223
-out:
224
-	hdmi_core_ddc_uninit(core);
225
-
226
-	return r ? r : len;
227172 }
228173 
229174 void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s)
....@@ -287,7 +232,7 @@
287232 }
288233 
289234 static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
290
-			struct hdmi_config *cfg)
235
+			   const struct hdmi_config *cfg)
291236 {
292237 	DSSDBG("hdmi_core_init\n");
293238 
....@@ -325,10 +270,10 @@
325270 
326271 /* DSS_HDMI_CORE_VIDEO_CONFIG */
327272 static void hdmi_core_video_config(struct hdmi_core_data *core,
328
-			struct hdmi_core_vid_config *cfg)
273
+			const struct hdmi_core_vid_config *cfg)
329274 {
330275 	void __iomem *base = core->base;
331
-	struct videomode *vm = &cfg->v_fc_config.vm;
276
+	const struct videomode *vm = &cfg->v_fc_config.vm;
332277 	unsigned char r = 0;
333278 	bool vsync_pol, hsync_pol;
334279 
....@@ -408,14 +353,6 @@
408353 	REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
409354 }
410355 
411
-static void hdmi_core_config_csc(struct hdmi_core_data *core)
412
-{
413
-	int clr_depth = 0;	/* 24 bit color depth */
414
-
415
-	/* CSC_COLORDEPTH */
416
-	REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4);
417
-}
418
-
419356 static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
420357 {
421358 	int video_mapping = 1;	/* for 24 bit color depth */
....@@ -480,47 +417,67 @@
480417 	REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0);
481418 }
482419 
483
-static void hdmi_core_csc_config(struct hdmi_core_data *core,
484
-		struct csc_table csc_coeff)
420
+static void hdmi_core_write_csc(struct hdmi_core_data *core,
421
+		const struct csc_table *csc_coeff)
485422 {
486423 	void __iomem *base = core->base;
487424 
488
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0);
489
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0);
490
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0);
491
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0);
492
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0);
493
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0);
494
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0);
495
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0);
496
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0);
497
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0);
498
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0);
499
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0);
500
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0);
501
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0);
502
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0);
503
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0);
504
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0);
505
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0);
506
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0);
507
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0);
508
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0);
509
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0);
510
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0);
511
-	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0);
425
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff->a1 >> 8, 6, 0);
426
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff->a1, 7, 0);
427
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff->a2 >> 8, 6, 0);
428
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff->a2, 7, 0);
429
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff->a3 >> 8, 6, 0);
430
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff->a3, 7, 0);
431
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff->a4 >> 8, 6, 0);
432
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff->a4, 7, 0);
433
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff->b1 >> 8, 6, 0);
434
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff->b1, 7, 0);
435
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff->b2 >> 8, 6, 0);
436
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff->b2, 7, 0);
437
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff->b3 >> 8, 6, 0);
438
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff->b3, 7, 0);
439
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff->b4 >> 8, 6, 0);
440
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff->b4, 7, 0);
441
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff->c1 >> 8, 6, 0);
442
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff->c1, 7, 0);
443
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff->c2 >> 8, 6, 0);
444
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff->c2, 7, 0);
445
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff->c3 >> 8, 6, 0);
446
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff->c3, 7, 0);
447
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff->c4 >> 8, 6, 0);
448
+	REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff->c4, 7, 0);
512449 
450
+	/* enable CSC */
513451 	REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
514452 }
515453 
516
-static void hdmi_core_configure_range(struct hdmi_core_data *core)
454
+static void hdmi_core_configure_range(struct hdmi_core_data *core,
455
+				      enum hdmi_quantization_range range)
517456 {
518
-	struct csc_table csc_coeff = { 0 };
457
+	static const struct csc_table csc_limited_range = {
458
+		7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32
459
+	};
460
+	static const struct csc_table csc_full_range = {
461
+		8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0
462
+	};
463
+	const struct csc_table *csc_coeff;
519464 
520
-	/* support limited range with 24 bit color depth for now */
521
-	csc_coeff = csc_table_deepcolor[0];
465
+	/* CSC_COLORDEPTH  = 24 bits*/
466
+	REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, 0, 7, 4);
522467 
523
-	hdmi_core_csc_config(core, csc_coeff);
468
+	switch (range) {
469
+	case HDMI_QUANTIZATION_RANGE_FULL:
470
+		csc_coeff = &csc_full_range;
471
+		break;
472
+
473
+	case HDMI_QUANTIZATION_RANGE_DEFAULT:
474
+	case HDMI_QUANTIZATION_RANGE_LIMITED:
475
+	default:
476
+		csc_coeff = &csc_limited_range;
477
+		break;
478
+	}
479
+
480
+	hdmi_core_write_csc(core, csc_coeff);
524481 }
525482 
526483 static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
....@@ -611,8 +568,19 @@
611568 	struct videomode vm;
612569 	struct hdmi_video_format video_format;
613570 	struct hdmi_core_vid_config v_core_cfg;
571
+	enum hdmi_quantization_range range;
614572 
615573 	hdmi_core_mask_interrupts(core);
574
+
575
+	if (cfg->hdmi_dvi_mode == HDMI_HDMI) {
576
+		char vic = cfg->infoframe.video_code;
577
+
578
+		/* All CEA modes other than VIC 1 use limited quantization range. */
579
+		range = vic > 1 ? HDMI_QUANTIZATION_RANGE_LIMITED :
580
+			HDMI_QUANTIZATION_RANGE_FULL;
581
+	} else {
582
+		range = HDMI_QUANTIZATION_RANGE_FULL;
583
+	}
616584 
617585 	hdmi_core_init(&v_core_cfg, cfg);
618586 
....@@ -627,9 +595,8 @@
627595 
628596 	hdmi_wp_video_config_interface(wp, &vm);
629597 
630
-	/* support limited range with 24 bit color depth for now */
631
-	hdmi_core_configure_range(core);
632
-	cfg->infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED;
598
+	hdmi_core_configure_range(core, range);
599
+	cfg->infoframe.quantization_range = range;
633600 
634601 	/*
635602 	 * configure core video part, set software reset in the core
....@@ -639,7 +606,6 @@
639606 	hdmi_core_video_config(core, &v_core_cfg);
640607 
641608 	hdmi_core_config_video_packetizer(core);
642
-	hdmi_core_config_csc(core);
643609 	hdmi_core_config_video_sampler(core);
644610 
645611 	if (cfg->hdmi_dvi_mode == HDMI_HDMI)
....@@ -809,7 +775,7 @@
809775 	struct hdmi_audio_format audio_format;
810776 	struct hdmi_audio_dma audio_dma;
811777 	struct hdmi_core_audio_config core_cfg;
812
-	int err, n, cts, channel_count;
778
+	int n, cts, channel_count;
813779 	unsigned int fs_nr;
814780 	bool word_length_16b = false;
815781 
....@@ -852,7 +818,7 @@
852818 		return -EINVAL;
853819 	}
854820 
855
-	err = hdmi_compute_acr(pclk, fs_nr, &n, &cts);
821
+	hdmi_compute_acr(pclk, fs_nr, &n, &cts);
856822 	core_cfg.n = n;
857823 	core_cfg.cts = cts;
858824