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2024-05-14 bedbef8ad3e75a304af6361af235302bcc61d06b 
 kernel/drivers/dma/sh/rcar-dmac.c
....@@ -1,8 +1,8 @@
11 // SPDX-License-Identifier: GPL-2.0
22 /*
3
- * Renesas R-Car Gen2 DMA Controller Driver
3
+ * Renesas R-Car Gen2/Gen3 DMA Controller Driver
44  *
5
- * Copyright (C) 2014 Renesas Electronics Inc.
5
+ * Copyright (C) 2014-2019 Renesas Electronics Inc.
66  *
77  * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
88  */
....@@ -192,27 +192,36 @@
192192  * @iomem: remapped I/O memory base
193193  * @n_channels: number of available channels
194194  * @channels: array of DMAC channels
195
+ * @channels_mask: bitfield of which DMA channels are managed by this driver
195196  * @modules: bitmask of client modules in use
196197  */
197198 struct rcar_dmac {
198199 	struct dma_device engine;
199200 	struct device *dev;
200201 	void __iomem *iomem;
201
-	struct device_dma_parameters parms;
202202 
203203 	unsigned int n_channels;
204204 	struct rcar_dmac_chan *channels;
205
+	u32 channels_mask;
205206 
206207 	DECLARE_BITMAP(modules, 256);
207208 };
208209 
209210 #define to_rcar_dmac(d)		container_of(d, struct rcar_dmac, engine)
210211 
212
+/*
213
+ * struct rcar_dmac_of_data - This driver's OF data
214
+ * @chan_offset_base: DMAC channels base offset
215
+ * @chan_offset_stride: DMAC channels offset stride
216
+ */
217
+struct rcar_dmac_of_data {
218
+	u32 chan_offset_base;
219
+	u32 chan_offset_stride;
220
+};
221
+
211222 /* -----------------------------------------------------------------------------
212223  * Registers
213224  */
214
-
215
-#define RCAR_DMAC_CHAN_OFFSET(i)	(0x8000 + 0x80 * (i))
216225 
217226 #define RCAR_DMAISTA			0x0020
218227 #define RCAR_DMASEC			0x0030
....@@ -438,7 +447,7 @@
438447 	u16 dmaor;
439448 
440449 	/* Clear all channels and enable the DMAC globally. */
441
-	rcar_dmac_write(dmac, RCAR_DMACHCLR, GENMASK(dmac->n_channels - 1, 0));
450
+	rcar_dmac_write(dmac, RCAR_DMACHCLR, dmac->channels_mask);
442451 	rcar_dmac_write(dmac, RCAR_DMAOR,
443452 			RCAR_DMAOR_PRI_FIXED | RCAR_DMAOR_DME);
444453 
....@@ -813,6 +822,9 @@
813822 	/* Stop all channels. */
814823 	for (i = 0; i < dmac->n_channels; ++i) {
815824 		struct rcar_dmac_chan *chan = &dmac->channels[i];
825
+
826
+		if (!(dmac->channels_mask & BIT(i)))
827
+			continue;
816828 
817829 		/* Stop and reinitialize the channel. */
818830 		spin_lock_irq(&chan->lock);
....@@ -1206,7 +1218,7 @@
12061218 	sg_len = buf_len / period_len;
12071219 	if (sg_len > RCAR_DMAC_MAX_SG_LEN) {
12081220 		dev_err(chan->device->dev,
1209
-			"chan%u: sg length %d exceds limit %d",
1221
+			"chan%u: sg length %d exceeds limit %d",
12101222 			rchan->index, sg_len, RCAR_DMAC_MAX_SG_LEN);
12111223 		return NULL;
12121224 	}
....@@ -1215,7 +1227,7 @@
12151227 	 * Allocate the sg list dynamically as it would consume too much stack
12161228 	 * space.
12171229 	 */
1218
-	sgl = kcalloc(sg_len, sizeof(*sgl), GFP_NOWAIT);
1230
+	sgl = kmalloc_array(sg_len, sizeof(*sgl), GFP_NOWAIT);
12191231 	if (!sgl)
12201232 		return NULL;
12211233 
....@@ -1654,8 +1666,7 @@
16541666 	 * Forcing it to call dma_request_channel() and iterate through all
16551667 	 * channels from all controllers is just pointless.
16561668 	 */
1657
-	if (chan->device->device_config != rcar_dmac_device_config ||
1658
-	    dma_spec->np != chan->device->dev->of_node)
1669
+	if (chan->device->device_config != rcar_dmac_device_config)
16591670 		return false;
16601671 
16611672 	return !test_and_set_bit(dma_spec->args[0], dmac->modules);
....@@ -1675,7 +1686,8 @@
16751686 	dma_cap_zero(mask);
16761687 	dma_cap_set(DMA_SLAVE, mask);
16771688 
1678
-	chan = dma_request_channel(mask, rcar_dmac_chan_filter, dma_spec);
1689
+	chan = __dma_request_channel(&mask, rcar_dmac_chan_filter, dma_spec,
1690
+				     ofdma->of_node);
16791691 	if (!chan)
16801692 		return NULL;
16811693 
....@@ -1721,6 +1733,7 @@
17211733 
17221734 static int rcar_dmac_chan_probe(struct rcar_dmac *dmac,
17231735 				struct rcar_dmac_chan *rchan,
1736
+				const struct rcar_dmac_of_data *data,
17241737 				unsigned int index)
17251738 {
17261739 	struct platform_device *pdev = to_platform_device(dmac->dev);
....@@ -1730,7 +1743,8 @@
17301743 	int ret;
17311744 
17321745 	rchan->index = index;
1733
-	rchan->iomem = dmac->iomem + RCAR_DMAC_CHAN_OFFSET(index);
1746
+	rchan->iomem = dmac->iomem + data->chan_offset_base +
1747
+		       data->chan_offset_stride * index;
17341748 	rchan->mid_rid = -EINVAL;
17351749 
17361750 	spin_lock_init(&rchan->lock);
....@@ -1744,10 +1758,8 @@
17441758 	/* Request the channel interrupt. */
17451759 	sprintf(pdev_irqname, "ch%u", index);
17461760 	rchan->irq = platform_get_irq_byname(pdev, pdev_irqname);
1747
-	if (rchan->irq < 0) {
1748
-		dev_err(dmac->dev, "no IRQ specified for channel %u\n", index);
1761
+	if (rchan->irq < 0)
17491762 		return -ENODEV;
1750
-	}
17511763 
17521764 	irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:%u",
17531765 				 dev_name(dmac->dev), index);
....@@ -1776,6 +1788,8 @@
17761788 	return 0;
17771789 }
17781790 
1791
+#define RCAR_DMAC_MAX_CHANNELS	32
1792
+
17791793 static int rcar_dmac_parse_of(struct device *dev, struct rcar_dmac *dmac)
17801794 {
17811795 	struct device_node *np = dev->of_node;
....@@ -1787,11 +1801,23 @@
17871801 		return ret;
17881802 	}
17891803 
1790
-	if (dmac->n_channels <= 0 || dmac->n_channels >= 100) {
1804
+	/* The hardware and driver don't support more than 32 bits in CHCLR */
1805
+	if (dmac->n_channels <= 0 ||
1806
+	    dmac->n_channels >= RCAR_DMAC_MAX_CHANNELS) {
17911807 		dev_err(dev, "invalid number of channels %u\n",
17921808 			dmac->n_channels);
17931809 		return -EINVAL;
17941810 	}
1811
+
1812
+	/*
1813
+	 * If the driver is unable to read dma-channel-mask property,
1814
+	 * the driver assumes that it can use all channels.
1815
+	 */
1816
+	dmac->channels_mask = GENMASK(dmac->n_channels - 1, 0);
1817
+	of_property_read_u32(np, "dma-channel-mask", &dmac->channels_mask);
1818
+
1819
+	/* If the property has out-of-channel mask, this driver clears it */
1820
+	dmac->channels_mask &= GENMASK(dmac->n_channels - 1, 0);
17951821 
17961822 	return 0;
17971823 }
....@@ -1802,12 +1828,15 @@
18021828 		DMA_SLAVE_BUSWIDTH_2_BYTES | DMA_SLAVE_BUSWIDTH_4_BYTES |
18031829 		DMA_SLAVE_BUSWIDTH_8_BYTES | DMA_SLAVE_BUSWIDTH_16_BYTES |
18041830 		DMA_SLAVE_BUSWIDTH_32_BYTES | DMA_SLAVE_BUSWIDTH_64_BYTES;
1805
-	unsigned int channels_offset = 0;
18061831 	struct dma_device *engine;
18071832 	struct rcar_dmac *dmac;
1808
-	struct resource *mem;
1833
+	const struct rcar_dmac_of_data *data;
18091834 	unsigned int i;
18101835 	int ret;
1836
+
1837
+	data = of_device_get_match_data(&pdev->dev);
1838
+	if (!data)
1839
+		return -EINVAL;
18111840 
18121841 	dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL);
18131842 	if (!dmac)
....@@ -1815,8 +1844,10 @@
18151844 
18161845 	dmac->dev = &pdev->dev;
18171846 	platform_set_drvdata(pdev, dmac);
1818
-	dmac->dev->dma_parms = &dmac->parms;
1819
-	dma_set_max_seg_size(dmac->dev, RCAR_DMATCR_MASK);
1847
+	ret = dma_set_max_seg_size(dmac->dev, RCAR_DMATCR_MASK);
1848
+	if (ret)
1849
+		return ret;
1850
+
18201851 	ret = dma_set_mask_and_coherent(dmac->dev, DMA_BIT_MASK(40));
18211852 	if (ret)
18221853 		return ret;
....@@ -1833,10 +1864,8 @@
18331864 	 * level we can't disable it selectively, so ignore channel 0 for now if
18341865 	 * the device is part of an IOMMU group.
18351866 	 */
1836
-	if (pdev->dev.iommu_group) {
1837
-		dmac->n_channels--;
1838
-		channels_offset = 1;
1839
-	}
1867
+	if (device_iommu_mapped(&pdev->dev))
1868
+		dmac->channels_mask &= ~BIT(0);
18401869 
18411870 	dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels,
18421871 				      sizeof(*dmac->channels), GFP_KERNEL);
....@@ -1844,14 +1873,13 @@
18441873 		return -ENOMEM;
18451874 
18461875 	/* Request resources. */
1847
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1848
-	dmac->iomem = devm_ioremap_resource(&pdev->dev, mem);
1876
+	dmac->iomem = devm_platform_ioremap_resource(pdev, 0);
18491877 	if (IS_ERR(dmac->iomem))
18501878 		return PTR_ERR(dmac->iomem);
18511879 
18521880 	/* Enable runtime PM and initialize the device. */
18531881 	pm_runtime_enable(&pdev->dev);
1854
-	ret = pm_runtime_get_sync(&pdev->dev);
1882
+	ret = pm_runtime_resume_and_get(&pdev->dev);
18551883 	if (ret < 0) {
18561884 		dev_err(&pdev->dev, "runtime PM get sync failed (%d)\n", ret);
18571885 		return ret;
....@@ -1894,8 +1922,10 @@
18941922 	INIT_LIST_HEAD(&engine->channels);
18951923 
18961924 	for (i = 0; i < dmac->n_channels; ++i) {
1897
-		ret = rcar_dmac_chan_probe(dmac, &dmac->channels[i],
1898
-					   i + channels_offset);
1925
+		if (!(dmac->channels_mask & BIT(i)))
1926
+			continue;
1927
+
1928
+		ret = rcar_dmac_chan_probe(dmac, &dmac->channels[i], data, i);
18991929 		if (ret < 0)
19001930 			goto error;
19011931 	}
....@@ -1942,8 +1972,16 @@
19421972 	rcar_dmac_stop_all_chan(dmac);
19431973 }
19441974 
1975
+static const struct rcar_dmac_of_data rcar_dmac_data = {
1976
+	.chan_offset_base = 0x8000,
1977
+	.chan_offset_stride = 0x80,
1978
+};
1979
+
19451980 static const struct of_device_id rcar_dmac_of_ids[] = {
1946
-	{ .compatible = "renesas,rcar-dmac", },
1981
+	{
1982
+		.compatible = "renesas,rcar-dmac",
1983
+		.data = &rcar_dmac_data,
1984
+	},
19471985 	{ /* Sentinel */ }
19481986 };
19491987 MODULE_DEVICE_TABLE(of, rcar_dmac_of_ids);