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479 | 479 | On Intel Skylake-era systems the mitigation covers most, but not all, |
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480 | 480 | cases. See :ref:`[3] <spec_ref3>` for more details. |
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481 | 481 | |
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482 | | - On CPUs with hardware mitigation for Spectre variant 2 (e.g. Enhanced |
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483 | | - IBRS on x86), retpoline is automatically disabled at run time. |
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| 482 | + On CPUs with hardware mitigation for Spectre variant 2 (e.g. IBRS |
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| 483 | + or enhanced IBRS on x86), retpoline is automatically disabled at run time. |
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| 484 | + |
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| 485 | + Systems which support enhanced IBRS (eIBRS) enable IBRS protection once at |
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| 486 | + boot, by setting the IBRS bit, and they're automatically protected against |
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| 487 | + Spectre v2 variant attacks, including cross-thread branch target injections |
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| 488 | + on SMT systems (STIBP). In other words, eIBRS enables STIBP too. |
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| 489 | + |
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| 490 | + Legacy IBRS systems clear the IBRS bit on exit to userspace and |
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| 491 | + therefore explicitly enable STIBP for that |
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484 | 492 | |
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485 | 493 | The retpoline mitigation is turned on by default on vulnerable |
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486 | 494 | CPUs. It can be forced on or off by the administrator |
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.. | .. |
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504 | 512 | For Spectre variant 2 mitigation, individual user programs |
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505 | 513 | can be compiled with return trampolines for indirect branches. |
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506 | 514 | This protects them from consuming poisoned entries in the branch |
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507 | | - target buffer left by malicious software. Alternatively, the |
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508 | | - programs can disable their indirect branch speculation via prctl() |
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509 | | - (See :ref:`Documentation/userspace-api/spec_ctrl.rst <set_spec_ctrl>`). |
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| 515 | + target buffer left by malicious software. |
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| 516 | + |
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| 517 | + On legacy IBRS systems, at return to userspace, implicit STIBP is disabled |
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| 518 | + because the kernel clears the IBRS bit. In this case, the userspace programs |
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| 519 | + can disable indirect branch speculation via prctl() (See |
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| 520 | + :ref:`Documentation/userspace-api/spec_ctrl.rst <set_spec_ctrl>`). |
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510 | 521 | On x86, this will turn on STIBP to guard against attacks from the |
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511 | 522 | sibling thread when the user program is running, and use IBPB to |
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512 | 523 | flush the branch target buffer when switching to/from the program. |
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