forked from ~ljy/RK356X_SDK_RELEASE

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hc
2023-02-14 b625cdcd68479b3d540a915785b6d9809b52a2f8 
 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
....@@ -47,10 +47,7 @@
4747 	void (*set_to_qsgmii)(struct rk_priv_data *bsp_priv);
4848 	void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
4949 	void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
50
-	void (*set_sgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
51
-	void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
52
-				    bool enable);
53
-	void (*integrated_phy_power)(struct rk_priv_data *bsp_priv, bool up);
50
+	void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
5451 };
5552 
5653 struct rk_priv_data {
....@@ -64,7 +61,6 @@
6461 	bool clk_enabled;
6562 	bool clock_input;
6663 	bool integrated_phy;
67
-	struct phy *comphy;
6864 
6965 	struct clk *clk_mac;
7066 	struct clk *gmac_clkin;
....@@ -169,10 +165,10 @@
169165 	int ret, i, id = bsp_priv->bus_id;
170166 	u32 val;
171167 
172
-	if (mode == PHY_INTERFACE_MODE_QSGMII && !id)
168
+	if (mode == PHY_INTERFACE_MODE_QSGMII && id > 0)
173169 		return 0;
174170 
175
-	ret = xpcs_soft_reset(bsp_priv, 0);
171
+	ret = xpcs_soft_reset(bsp_priv, id);
176172 	if (ret) {
177173 		dev_err(&bsp_priv->pdev->dev, "xpcs_soft_reset fail %d\n", ret);
178174 		return ret;
....@@ -199,10 +195,10 @@
199195 				   SR_MII_CTRL_AN_ENABLE);
200196 		}
201197 	} else {
202
-		val = xpcs_read(bsp_priv, SR_MII_OFFSET(0) + VR_MII_DIG_CTRL1);
203
-		xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_DIG_CTRL1,
198
+		val = xpcs_read(bsp_priv, SR_MII_OFFSET(id) + VR_MII_DIG_CTRL1);
199
+		xpcs_write(bsp_priv, SR_MII_OFFSET(id) + VR_MII_DIG_CTRL1,
204200 			   val | MII_MAC_AUTO_SW);
205
-		xpcs_write(bsp_priv, SR_MII_OFFSET(0) + MII_BMCR,
201
+		xpcs_write(bsp_priv, SR_MII_OFFSET(id) + MII_BMCR,
206202 			   SR_MII_CTRL_AN_ENABLE);
207203 	}
208204 
....@@ -216,55 +212,8 @@
216212 #define GRF_CLR_BIT(nr)	(BIT(nr+16))
217213 
218214 #define DELAY_ENABLE(soc, tx, rx) \
219
-	((((tx) >= 0) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
220
-	 (((rx) >= 0) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
221
-
222
-#define DELAY_VALUE(soc, tx, rx) \
223
-	((((tx) >= 0) ? soc##_GMAC_CLK_TX_DL_CFG(tx) : 0) | \
224
-	 (((rx) >= 0) ? soc##_GMAC_CLK_RX_DL_CFG(rx) : 0))
225
-
226
-/* Integrated EPHY */
227
-
228
-#define RK_GRF_MACPHY_CON0		0xb00
229
-#define RK_GRF_MACPHY_CON1		0xb04
230
-#define RK_GRF_MACPHY_CON2		0xb08
231
-#define RK_GRF_MACPHY_CON3		0xb0c
232
-
233
-#define RK_MACPHY_ENABLE		GRF_BIT(0)
234
-#define RK_MACPHY_DISABLE		GRF_CLR_BIT(0)
235
-#define RK_MACPHY_CFG_CLK_50M		GRF_BIT(14)
236
-#define RK_GMAC2PHY_RMII_MODE		(GRF_BIT(6) | GRF_CLR_BIT(7))
237
-#define RK_GRF_CON2_MACPHY_ID		HIWORD_UPDATE(0x1234, 0xffff, 0)
238
-#define RK_GRF_CON3_MACPHY_ID		HIWORD_UPDATE(0x35, 0x3f, 0)
239
-
240
-static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
241
-{
242
-	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
243
-	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
244
-
245
-	regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
246
-	regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
247
-
248
-	if (priv->phy_reset) {
249
-		/* PHY needs to be disabled before trying to reset it */
250
-		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
251
-		if (priv->phy_reset)
252
-			reset_control_assert(priv->phy_reset);
253
-		usleep_range(10, 20);
254
-		if (priv->phy_reset)
255
-			reset_control_deassert(priv->phy_reset);
256
-		usleep_range(10, 20);
257
-		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
258
-		msleep(30);
259
-	}
260
-}
261
-
262
-static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)
263
-{
264
-	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
265
-	if (priv->phy_reset)
266
-		reset_control_assert(priv->phy_reset);
267
-}
215
+	(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
216
+	 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
268217 
269218 #define PX30_GRF_GMAC_CON1		0x0904
270219 
....@@ -357,10 +306,12 @@
357306 
358307 	regmap_write(bsp_priv->grf, RK1808_GRF_GMAC_CON1,
359308 		     RK1808_GMAC_PHY_INTF_SEL_RGMII |
360
-		     DELAY_ENABLE(RK1808, tx_delay, rx_delay));
309
+		     RK1808_GMAC_RXCLK_DLY_ENABLE |
310
+		     RK1808_GMAC_TXCLK_DLY_ENABLE);
361311 
362312 	regmap_write(bsp_priv->grf, RK1808_GRF_GMAC_CON0,
363
-		     DELAY_VALUE(RK1808, tx_delay, rx_delay));
313
+		     RK1808_GMAC_CLK_RX_DL_CFG(rx_delay) |
314
+		     RK1808_GMAC_CLK_TX_DL_CFG(tx_delay));
364315 }
365316 
366317 static void rk1808_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -488,7 +439,8 @@
488439 		     RK3128_GMAC_RMII_MODE_CLR);
489440 	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
490441 		     DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
491
-		     DELAY_VALUE(RK3128, tx_delay, rx_delay));
442
+		     RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
443
+		     RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
492444 }
493445 
494446 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -604,7 +556,8 @@
604556 		     DELAY_ENABLE(RK3228, tx_delay, rx_delay));
605557 
606558 	regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
607
-		     DELAY_VALUE(RK3128, tx_delay, rx_delay));
559
+		     RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
560
+		     RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
608561 }
609562 
610563 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -667,16 +620,10 @@
667620 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
668621 }
669622 
670
-static void rk3228_integrated_phy_power(struct rk_priv_data *priv, bool up)
623
+static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
671624 {
672
-	if (up) {
673
-		regmap_write(priv->grf, RK3228_GRF_CON_MUX,
674
-			     RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
675
-
676
-		rk_gmac_integrated_ephy_powerup(priv);
677
-	} else {
678
-		rk_gmac_integrated_ephy_powerdown(priv);
679
-	}
625
+	regmap_write(priv->grf, RK3228_GRF_CON_MUX,
626
+		     RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
680627 }
681628 
682629 static const struct rk_gmac_ops rk3228_ops = {
....@@ -684,7 +631,7 @@
684631 	.set_to_rmii = rk3228_set_to_rmii,
685632 	.set_rgmii_speed = rk3228_set_rgmii_speed,
686633 	.set_rmii_speed = rk3228_set_rmii_speed,
687
-	.integrated_phy_power = rk3228_integrated_phy_power,
634
+	.integrated_phy_powerup =  rk3228_integrated_phy_powerup,
688635 };
689636 
690637 #define RK3288_GRF_SOC_CON1	0x0248
....@@ -730,7 +677,8 @@
730677 		     RK3288_GMAC_RMII_MODE_CLR);
731678 	regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
732679 		     DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
733
-		     DELAY_VALUE(RK3288, tx_delay, rx_delay));
680
+		     RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
681
+		     RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
734682 }
735683 
736684 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -901,10 +849,12 @@
901849 	regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
902850 		     RK3328_GMAC_PHY_INTF_SEL_RGMII |
903851 		     RK3328_GMAC_RMII_MODE_CLR |
904
-		     DELAY_ENABLE(RK3328, tx_delay, rx_delay));
852
+		     RK3328_GMAC_RXCLK_DLY_ENABLE |
853
+		     RK3328_GMAC_TXCLK_DLY_ENABLE);
905854 
906855 	regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
907
-		     DELAY_VALUE(RK3328, tx_delay, rx_delay));
856
+		     RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
857
+		     RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
908858 }
909859 
910860 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -972,16 +922,10 @@
972922 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
973923 }
974924 
975
-static void rk3328_integrated_phy_power(struct rk_priv_data *priv, bool up)
925
+static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
976926 {
977
-	if (up) {
978
-		regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
979
-			     RK3328_MACPHY_RMII_MODE);
980
-
981
-		rk_gmac_integrated_ephy_powerup(priv);
982
-	} else {
983
-		rk_gmac_integrated_ephy_powerdown(priv);
984
-	}
927
+	regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
928
+		     RK3328_MACPHY_RMII_MODE);
985929 }
986930 
987931 static const struct rk_gmac_ops rk3328_ops = {
....@@ -989,7 +933,7 @@
989933 	.set_to_rmii = rk3328_set_to_rmii,
990934 	.set_rgmii_speed = rk3328_set_rgmii_speed,
991935 	.set_rmii_speed = rk3328_set_rmii_speed,
992
-	.integrated_phy_power = rk3328_integrated_phy_power,
936
+	.integrated_phy_powerup =  rk3328_integrated_phy_powerup,
993937 };
994938 
995939 #define RK3366_GRF_SOC_CON6	0x0418
....@@ -1035,7 +979,8 @@
1035979 		     RK3366_GMAC_RMII_MODE_CLR);
1036980 	regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
1037981 		     DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
1038
-		     DELAY_VALUE(RK3366, tx_delay, rx_delay));
982
+		     RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
983
+		     RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
1039984 }
1040985 
1041986 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -1145,7 +1090,8 @@
11451090 		     RK3368_GMAC_RMII_MODE_CLR);
11461091 	regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
11471092 		     DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
1148
-		     DELAY_VALUE(RK3368, tx_delay, rx_delay));
1093
+		     RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
1094
+		     RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
11491095 }
11501096 
11511097 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -1255,7 +1201,8 @@
12551201 		     RK3399_GMAC_RMII_MODE_CLR);
12561202 	regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
12571203 		     DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
1258
-		     DELAY_VALUE(RK3399, tx_delay, rx_delay));
1204
+		     RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
1205
+		     RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
12591206 }
12601207 
12611208 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -1402,10 +1349,12 @@
14021349 
14031350 	regmap_write(bsp_priv->grf, offset_con1,
14041351 		     RK3568_GMAC_PHY_INTF_SEL_RGMII |
1405
-		     DELAY_ENABLE(RK3568, tx_delay, rx_delay));
1352
+		     RK3568_GMAC_RXCLK_DLY_ENABLE |
1353
+		     RK3568_GMAC_TXCLK_DLY_ENABLE);
14061354 
14071355 	regmap_write(bsp_priv->grf, offset_con0,
1408
-		     DELAY_VALUE(RK3568, tx_delay, rx_delay));
1356
+		     RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
1357
+		     RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
14091358 }
14101359 
14111360 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -1451,34 +1400,6 @@
14511400 			__func__, rate, ret);
14521401 }
14531402 
1454
-static void rk3568_set_gmac_sgmii_speed(struct rk_priv_data *bsp_priv, int speed)
1455
-{
1456
-	struct device *dev = &bsp_priv->pdev->dev;
1457
-	unsigned int ctrl;
1458
-
1459
-	/* Only gmac1 set the speed for port1 */
1460
-	if (!bsp_priv->bus_id)
1461
-		return;
1462
-
1463
-	switch (speed) {
1464
-	case 10:
1465
-		ctrl = BMCR_SPEED10;
1466
-		break;
1467
-	case 100:
1468
-		ctrl = BMCR_SPEED100;
1469
-		break;
1470
-	case 1000:
1471
-		ctrl = BMCR_SPEED1000;
1472
-		break;
1473
-	default:
1474
-		dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1475
-		return;
1476
-	}
1477
-
1478
-	xpcs_write(bsp_priv, SR_MII_OFFSET(bsp_priv->bus_id) + MII_BMCR,
1479
-		   ctrl | BMCR_FULLDPLX);
1480
-}
1481
-
14821403 static const struct rk_gmac_ops rk3568_ops = {
14831404 	.set_to_rgmii = rk3568_set_to_rgmii,
14841405 	.set_to_rmii = rk3568_set_to_rmii,
....@@ -1486,7 +1407,6 @@
14861407 	.set_to_qsgmii = rk3568_set_to_qsgmii,
14871408 	.set_rgmii_speed = rk3568_set_gmac_speed,
14881409 	.set_rmii_speed = rk3568_set_gmac_speed,
1489
-	.set_sgmii_speed = rk3568_set_gmac_sgmii_speed,
14901410 };
14911411 
14921412 #define RV1108_GRF_GMAC_CON0		0X0900
....@@ -1552,18 +1472,21 @@
15521472 		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
15531473 #define RV1126_GMAC_FLOW_CTRL			GRF_BIT(7)
15541474 #define RV1126_GMAC_FLOW_CTRL_CLR		GRF_CLR_BIT(7)
1555
-#define RV1126_M0_GMAC_RXCLK_DLY_ENABLE		GRF_BIT(1)
1556
-#define RV1126_M0_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(1)
1557
-#define RV1126_M0_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(0)
1558
-#define RV1126_M0_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
1559
-#define RV1126_M1_GMAC_RXCLK_DLY_ENABLE		GRF_BIT(3)
1560
-#define RV1126_M1_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(3)
1561
-#define RV1126_M1_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(2)
1562
-#define RV1126_M1_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(2)
1475
+#define RV1126_GMAC_M0_RXCLK_DLY_ENABLE		GRF_BIT(1)
1476
+#define RV1126_GMAC_M0_RXCLK_DLY_DISABLE	GRF_CLR_BIT(1)
1477
+#define RV1126_GMAC_M0_TXCLK_DLY_ENABLE		GRF_BIT(0)
1478
+#define RV1126_GMAC_M0_TXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
1479
+#define RV1126_GMAC_M1_RXCLK_DLY_ENABLE		GRF_BIT(3)
1480
+#define RV1126_GMAC_M1_RXCLK_DLY_DISABLE	GRF_CLR_BIT(3)
1481
+#define RV1126_GMAC_M1_TXCLK_DLY_ENABLE		GRF_BIT(2)
1482
+#define RV1126_GMAC_M1_TXCLK_DLY_DISABLE	GRF_CLR_BIT(2)
15631483 
1564
-/* RV1126_GRF_GMAC_CON1 && RV1126_GRF_GMAC_CON2 */
1565
-#define RV1126_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
1566
-#define RV1126_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
1484
+/* RV1126_GRF_GMAC_CON1 */
1485
+#define RV1126_GMAC_M0_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
1486
+#define RV1126_GMAC_M0_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
1487
+/* RV1126_GRF_GMAC_CON2 */
1488
+#define RV1126_GMAC_M1_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
1489
+#define RV1126_GMAC_M1_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
15671490 
15681491 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
15691492 				int tx_delay, int rx_delay)
....@@ -1577,14 +1500,18 @@
15771500 
15781501 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
15791502 		     RV1126_GMAC_PHY_INTF_SEL_RGMII |
1580
-		     DELAY_ENABLE(RV1126_M0, tx_delay, rx_delay) |
1581
-		     DELAY_ENABLE(RV1126_M1, tx_delay, rx_delay));
1503
+		     RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
1504
+		     RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
1505
+		     RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
1506
+		     RV1126_GMAC_M1_TXCLK_DLY_ENABLE);
15821507 
15831508 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1,
1584
-		     DELAY_VALUE(RV1126, tx_delay, rx_delay));
1509
+		     RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) |
1510
+		     RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay));
15851511 
15861512 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2,
1587
-		     DELAY_VALUE(RV1126, tx_delay, rx_delay));
1513
+		     RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) |
1514
+		     RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
15881515 }
15891516 
15901517 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -1657,6 +1584,50 @@
16571584 	.set_rgmii_speed = rv1126_set_rgmii_speed,
16581585 	.set_rmii_speed = rv1126_set_rmii_speed,
16591586 };
1587
+
1588
+#define RK_GRF_MACPHY_CON0		0xb00
1589
+#define RK_GRF_MACPHY_CON1		0xb04
1590
+#define RK_GRF_MACPHY_CON2		0xb08
1591
+#define RK_GRF_MACPHY_CON3		0xb0c
1592
+
1593
+#define RK_MACPHY_ENABLE		GRF_BIT(0)
1594
+#define RK_MACPHY_DISABLE		GRF_CLR_BIT(0)
1595
+#define RK_MACPHY_CFG_CLK_50M		GRF_BIT(14)
1596
+#define RK_GMAC2PHY_RMII_MODE		(GRF_BIT(6) | GRF_CLR_BIT(7))
1597
+#define RK_GRF_CON2_MACPHY_ID		HIWORD_UPDATE(0x1234, 0xffff, 0)
1598
+#define RK_GRF_CON3_MACPHY_ID		HIWORD_UPDATE(0x35, 0x3f, 0)
1599
+
1600
+static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
1601
+{
1602
+	if (priv->ops->integrated_phy_powerup)
1603
+		priv->ops->integrated_phy_powerup(priv);
1604
+
1605
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
1606
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
1607
+
1608
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
1609
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
1610
+
1611
+	if (priv->phy_reset) {
1612
+		/* PHY needs to be disabled before trying to reset it */
1613
+		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1614
+		if (priv->phy_reset)
1615
+			reset_control_assert(priv->phy_reset);
1616
+		usleep_range(10, 20);
1617
+		if (priv->phy_reset)
1618
+			reset_control_deassert(priv->phy_reset);
1619
+		usleep_range(10, 20);
1620
+		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
1621
+		msleep(30);
1622
+	}
1623
+}
1624
+
1625
+static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
1626
+{
1627
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1628
+	if (priv->phy_reset)
1629
+		reset_control_assert(priv->phy_reset);
1630
+}
16601631 
16611632 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
16621633 {
....@@ -1777,23 +1748,15 @@
17771748 			if (!IS_ERR(bsp_priv->pclk_xpcs))
17781749 				clk_prepare_enable(bsp_priv->pclk_xpcs);
17791750 
1780
-			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1781
-				bsp_priv->ops->set_clock_selection(bsp_priv, bsp_priv->clock_input,
1782
-								   true);
1783
-
17841751 			/**
17851752 			 * if (!IS_ERR(bsp_priv->clk_mac))
17861753 			 *	clk_prepare_enable(bsp_priv->clk_mac);
17871754 			 */
1788
-			usleep_range(100, 200);
1755
+			mdelay(5);
17891756 			bsp_priv->clk_enabled = true;
17901757 		}
17911758 	} else {
17921759 		if (bsp_priv->clk_enabled) {
1793
-			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1794
-				bsp_priv->ops->set_clock_selection(bsp_priv, bsp_priv->clock_input,
1795
-								   false);
1796
-
17971760 			if (phy_iface == PHY_INTERFACE_MODE_RMII) {
17981761 				clk_disable_unprepare(bsp_priv->mac_clk_rx);
17991762 
....@@ -1890,7 +1853,7 @@
18901853 
18911854 	ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
18921855 	if (ret) {
1893
-		bsp_priv->tx_delay = -1;
1856
+		bsp_priv->tx_delay = 0x30;
18941857 		dev_err(dev, "Can not read property: tx_delay.");
18951858 		dev_err(dev, "set tx_delay to 0x%x\n",
18961859 			bsp_priv->tx_delay);
....@@ -1901,7 +1864,7 @@
19011864 
19021865 	ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
19031866 	if (ret) {
1904
-		bsp_priv->rx_delay = -1;
1867
+		bsp_priv->rx_delay = 0x10;
19051868 		dev_err(dev, "Can not read property: rx_delay.");
19061869 		dev_err(dev, "set rx_delay to 0x%x\n",
19071870 			bsp_priv->rx_delay);
....@@ -1915,11 +1878,14 @@
19151878 	bsp_priv->xpcs = syscon_regmap_lookup_by_phandle(dev->of_node,
19161879 							 "rockchip,xpcs");
19171880 	if (!IS_ERR(bsp_priv->xpcs)) {
1918
-		bsp_priv->comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL);
1919
-		if (IS_ERR(bsp_priv->comphy)) {
1920
-			bsp_priv->comphy = NULL;
1881
+		struct phy *comphy;
1882
+
1883
+		comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL);
1884
+		if (IS_ERR(comphy))
19211885 			dev_err(dev, "devm_of_phy_get error\n");
1922
-		}
1886
+		ret = phy_init(comphy);
1887
+		if (ret)
1888
+			dev_err(dev, "phy_init error\n");
19231889 	}
19241890 
19251891 	if (plat->phy_node) {
....@@ -1961,17 +1927,17 @@
19611927 	case PHY_INTERFACE_MODE_RGMII_ID:
19621928 		dev_info(dev, "init for RGMII_ID\n");
19631929 		if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
1964
-			bsp_priv->ops->set_to_rgmii(bsp_priv, -1, -1);
1930
+			bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
19651931 		break;
19661932 	case PHY_INTERFACE_MODE_RGMII_RXID:
19671933 		dev_info(dev, "init for RGMII_RXID\n");
19681934 		if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
1969
-			bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, -1);
1935
+			bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
19701936 		break;
19711937 	case PHY_INTERFACE_MODE_RGMII_TXID:
19721938 		dev_info(dev, "init for RGMII_TXID\n");
19731939 		if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
1974
-			bsp_priv->ops->set_to_rgmii(bsp_priv, -1, bsp_priv->rx_delay);
1940
+			bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
19751941 		break;
19761942 	case PHY_INTERFACE_MODE_RMII:
19771943 		dev_info(dev, "init for RMII\n");
....@@ -1980,23 +1946,11 @@
19801946 		break;
19811947 	case PHY_INTERFACE_MODE_SGMII:
19821948 		dev_info(dev, "init for SGMII\n");
1983
-		ret = phy_init(bsp_priv->comphy);
1984
-		if (ret) {
1985
-			dev_err(dev, "phy_init error: %d\n", ret);
1986
-			return ret;
1987
-		}
1988
-
19891949 		if (bsp_priv->ops && bsp_priv->ops->set_to_sgmii)
19901950 			bsp_priv->ops->set_to_sgmii(bsp_priv);
19911951 		break;
19921952 	case PHY_INTERFACE_MODE_QSGMII:
19931953 		dev_info(dev, "init for QSGMII\n");
1994
-		ret = phy_init(bsp_priv->comphy);
1995
-		if (ret) {
1996
-			dev_err(dev, "phy_init error: %d\n", ret);
1997
-			return ret;
1998
-		}
1999
-
20001954 		if (bsp_priv->ops && bsp_priv->ops->set_to_qsgmii)
20011955 			bsp_priv->ops->set_to_qsgmii(bsp_priv);
20021956 		break;
....@@ -2013,6 +1967,9 @@
20131967 	pm_runtime_enable(dev);
20141968 	pm_runtime_get_sync(dev);
20151969 
1970
+	if (bsp_priv->integrated_phy)
1971
+		rk_gmac_integrated_phy_powerup(bsp_priv);
1972
+
20161973 	return 0;
20171974 }
20181975 
....@@ -2020,9 +1977,8 @@
20201977 {
20211978 	struct device *dev = &gmac->pdev->dev;
20221979 
2023
-	if (gmac->phy_iface == PHY_INTERFACE_MODE_SGMII ||
2024
-	    gmac->phy_iface == PHY_INTERFACE_MODE_QSGMII)
2025
-		phy_exit(gmac->comphy);
1980
+	if (gmac->integrated_phy)
1981
+		rk_gmac_integrated_phy_powerdown(gmac);
20261982 
20271983 	pm_runtime_put_sync(dev);
20281984 	pm_runtime_disable(dev);
....@@ -2049,26 +2005,11 @@
20492005 			bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
20502006 		break;
20512007 	case PHY_INTERFACE_MODE_SGMII:
2052
-		if (bsp_priv->ops && bsp_priv->ops->set_sgmii_speed)
2053
-			bsp_priv->ops->set_sgmii_speed(bsp_priv, speed);
20542008 	case PHY_INTERFACE_MODE_QSGMII:
20552009 		break;
20562010 	default:
20572011 		dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
20582012 	}
2059
-}
2060
-
2061
-static int rk_integrated_phy_power(void *priv, bool up)
2062
-{
2063
-	struct rk_priv_data *bsp_priv = priv;
2064
-
2065
-	if (!bsp_priv->integrated_phy || !bsp_priv->ops ||
2066
-	    !bsp_priv->ops->integrated_phy_power)
2067
-		return 0;
2068
-
2069
-	bsp_priv->ops->integrated_phy_power(bsp_priv, up);
2070
-
2071
-	return 0;
20722013 }
20732014 
20742015 void dwmac_rk_set_rgmii_delayline(struct stmmac_priv *priv,
....@@ -2109,17 +2050,24 @@
21092050 {
21102051 }
21112052 
2053
+static unsigned char macaddr[6];
2054
+extern ssize_t at24_mac_read(unsigned char* addr);
21122055 void rk_get_eth_addr(void *priv, unsigned char *addr)
21132056 {
21142057 	struct rk_priv_data *bsp_priv = priv;
21152058 	struct device *dev = &bsp_priv->pdev->dev;
2116
-	unsigned char ethaddr[ETH_ALEN * MAX_ETH] = {0};
2117
-	int ret, id = bsp_priv->bus_id;
2059
+	int i;
2060
+	//unsigned char ethaddr[ETH_ALEN * MAX_ETH] = {0};
2061
+	//int ret, id = bsp_priv->bus_id;
21182062 
2063
+	//ben
2064
+	printk("nk-debug:enter rk_get_eth_addr.. \n");
2065
+
2066
+	#if 0
21192067 	rk_devinfo_get_eth_mac(addr);
21202068 	if (is_valid_ether_addr(addr))
21212069 		goto out;
2122
-
2070
+		
21232071 	if (id < 0 || id >= MAX_ETH) {
21242072 		dev_err(dev, "%s: Invalid ethernet bus id %d\n", __func__, id);
21252073 		return;
....@@ -2146,7 +2094,35 @@
21462094 	} else {
21472095 		memcpy(addr, &ethaddr[id * ETH_ALEN], ETH_ALEN);
21482096 	}
2097
+	#endif
2098
+	
2099
+	#if 0
2100
+	macaddr[0] = 0xee;
2101
+	macaddr[1] = 0x31;
2102
+	macaddr[2] = 0x32;
2103
+	macaddr[3] = 0x33;
2104
+	macaddr[4] = 0x34;
2105
+	macaddr[5] = 0x35;
2106
+	
2107
+	memcpy(addr, macaddr, 6);
2108
+	#endif
2109
+	
2110
+	#if 1
2111
+	if (at24_mac_read(macaddr) > 0) {
2112
+		printk("ben %s: at24_mac_read Success!! \n", __func__);
2113
+		memcpy(addr, macaddr, 6);
21492114 
2115
+		printk("Read the Ethernet MAC address from :");
2116
+		for (i = 0; i < 5; i++)
2117
+			printk("%2.2x:", addr[i]);
2118
+ 
2119
+		printk("%2.2x\n", addr[i]);	
2120
+	} else {
2121
+		printk("ben %s: at24_mac_read Failed!! \n", __func__);
2122
+		goto out;
2123
+	}
2124
+	#endif
2125
+	
21502126 out:
21512127 	dev_err(dev, "%s: mac address: %pM\n", __func__, addr);
21522128 }
....@@ -2158,6 +2134,7 @@
21582134 	const struct rk_gmac_ops *data;
21592135 	int ret;
21602136 
2137
+	printk("nk-debug:enter rk_gmac_probe 1.. \n");
21612138 	data = of_device_get_match_data(&pdev->dev);
21622139 	if (!data) {
21632140 		dev_err(&pdev->dev, "no of match data provided\n");
....@@ -2177,7 +2154,6 @@
21772154 
21782155 	plat_dat->fix_mac_speed = rk_fix_speed;
21792156 	plat_dat->get_eth_addr = rk_get_eth_addr;
2180
-	plat_dat->integrated_phy_power = rk_integrated_phy_power;
21812157 
21822158 	plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
21832159 	if (IS_ERR(plat_dat->bsp_priv)) {
....@@ -2185,6 +2161,7 @@
21852161 		goto err_remove_config_dt;
21862162 	}
21872163 
2164
+	printk("nk-debug:enter rk_gmac_probe 2.. \n");
21882165 	ret = rk_gmac_clk_init(plat_dat);
21892166 	if (ret)
21902167 		goto err_remove_config_dt;
....@@ -2254,45 +2231,19 @@
22542231 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
22552232 
22562233 static const struct of_device_id rk_gmac_dwmac_match[] = {
2257
-#ifdef CONFIG_CPU_PX30
22582234 	{ .compatible = "rockchip,px30-gmac",	.data = &px30_ops   },
2259
-#endif
2260
-#ifdef CONFIG_CPU_RK1808
22612235 	{ .compatible = "rockchip,rk1808-gmac", .data = &rk1808_ops },
2262
-#endif
2263
-#ifdef CONFIG_CPU_RK312X
22642236 	{ .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
2265
-#endif
2266
-#ifdef CONFIG_CPU_RK322X
22672237 	{ .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
2268
-#endif
2269
-#ifdef CONFIG_CPU_RK3288
22702238 	{ .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
2271
-#endif
2272
-#ifdef CONFIG_CPU_RK3308
22732239 	{ .compatible = "rockchip,rk3308-mac",  .data = &rk3308_ops },
2274
-#endif
2275
-#ifdef CONFIG_CPU_RK3328
22762240 	{ .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
2277
-#endif
2278
-#ifdef CONFIG_CPU_RK3366
22792241 	{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
2280
-#endif
2281
-#ifdef CONFIG_CPU_RK3368
22822242 	{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
2283
-#endif
2284
-#ifdef CONFIG_CPU_RK3399
22852243 	{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
2286
-#endif
2287
-#ifdef CONFIG_CPU_RK3568
22882244 	{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
2289
-#endif
2290
-#ifdef CONFIG_CPU_RV110X
22912245 	{ .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
2292
-#endif
2293
-#ifdef CONFIG_CPU_RV1126
22942246 	{ .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
2295
-#endif
22962247 	{ }
22972248 };
22982249 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
....@@ -2306,7 +2257,8 @@
23062257 		.of_match_table = rk_gmac_dwmac_match,
23072258 	},
23082259 };
2309
-module_platform_driver(rk_gmac_dwmac_driver);
2260
+//module_platform_driver(rk_gmac_dwmac_driver);
2261
+ module_platform_driver1(rk_gmac_dwmac_driver);
23102262 
23112263 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
23122264 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");