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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/sound/soc/tegra/tegra_asoc_utils.c
..
..
@@ -1,23 +1,9 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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2
 /*
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  * tegra_asoc_utils.c - Harmony machine ASoC driver
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  *
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  * Author: Stephen Warren <swarren@nvidia.com>
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  * Copyright (C) 2010,2012 - NVIDIA, Inc.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License
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- * version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful, but
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- * WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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- * General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, write to the Free Software
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- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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- * 02110-1301 USA
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- *
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  */
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8
 
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9
 #include <linux/clk.h>
..
..
@@ -74,8 +60,6 @@
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 	data->set_mclk = 0;
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61
 
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 	clk_disable_unprepare(data->clk_cdev1);
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-	clk_disable_unprepare(data->clk_pll_a_out0);
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-	clk_disable_unprepare(data->clk_pll_a);
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 	err = clk_set_rate(data->clk_pll_a, new_baseclock);
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 	if (err) {
..
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@@ -90,18 +74,6 @@
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 	}
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 	/* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
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-
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-	err = clk_prepare_enable(data->clk_pll_a);
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-	if (err) {
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-		dev_err(data->dev, "Can't enable pll_a: %d\n", err);
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-		return err;
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-	}
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-
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-	err = clk_prepare_enable(data->clk_pll_a_out0);
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-	if (err) {
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-		dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
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-		return err;
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-	}
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77
 
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 	err = clk_prepare_enable(data->clk_cdev1);
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79
 	if (err) {
..
..
@@ -123,8 +95,6 @@
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 	int err;
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 	clk_disable_unprepare(data->clk_cdev1);
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-	clk_disable_unprepare(data->clk_pll_a_out0);
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-	clk_disable_unprepare(data->clk_pll_a);
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98
 
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 	/*
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 	 * AC97 rate is fixed at 24.576MHz and is used for both the host
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..
@@ -144,18 +114,6 @@
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114
 
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 	/* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
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116
 
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-	err = clk_prepare_enable(data->clk_pll_a);
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-	if (err) {
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-		dev_err(data->dev, "Can't enable pll_a: %d\n", err);
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-		return err;
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-	}
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-
153
-	err = clk_prepare_enable(data->clk_pll_a_out0);
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-	if (err) {
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-		dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
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-		return err;
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-	}
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-
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 	err = clk_prepare_enable(data->clk_cdev1);
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 	if (err) {
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 		dev_err(data->dev, "Can't enable cdev1: %d\n", err);
..
..
@@ -172,6 +130,7 @@
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 int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
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 			  struct device *dev)
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 {
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+	struct clk *clk_out_1, *clk_extern1;
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 	int ret;
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 	data->dev = dev;
..
..
@@ -189,51 +148,77 @@
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 		return -EINVAL;
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 	}
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150
 
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-	data->clk_pll_a = clk_get(dev, "pll_a");
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+	data->clk_pll_a = devm_clk_get(dev, "pll_a");
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 	if (IS_ERR(data->clk_pll_a)) {
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 		dev_err(data->dev, "Can't retrieve clk pll_a\n");
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-		ret = PTR_ERR(data->clk_pll_a);
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-		goto err;
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+		return PTR_ERR(data->clk_pll_a);
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 	}
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-	data->clk_pll_a_out0 = clk_get(dev, "pll_a_out0");
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+	data->clk_pll_a_out0 = devm_clk_get(dev, "pll_a_out0");
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 	if (IS_ERR(data->clk_pll_a_out0)) {
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 		dev_err(data->dev, "Can't retrieve clk pll_a_out0\n");
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-		ret = PTR_ERR(data->clk_pll_a_out0);
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-		goto err_put_pll_a;
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+		return PTR_ERR(data->clk_pll_a_out0);
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 	}
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162
 
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-	data->clk_cdev1 = clk_get(dev, "mclk");
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+	data->clk_cdev1 = devm_clk_get(dev, "mclk");
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 	if (IS_ERR(data->clk_cdev1)) {
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 		dev_err(data->dev, "Can't retrieve clk cdev1\n");
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-		ret = PTR_ERR(data->clk_cdev1);
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-		goto err_put_pll_a_out0;
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+		return PTR_ERR(data->clk_cdev1);
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167
 	}
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168
 
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-	ret = tegra_asoc_utils_set_rate(data, 44100, 256 * 44100);
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-	if (ret)
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-		goto err_put_cdev1;
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+	/*
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+	 * If clock parents are not set in DT, configure here to use clk_out_1
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+	 * as mclk and extern1 as parent for Tegra30 and higher.
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+	 */
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+	if (!of_find_property(dev->of_node, "assigned-clock-parents", NULL) &&
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+	    data->soc > TEGRA_ASOC_UTILS_SOC_TEGRA20) {
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+		dev_warn(data->dev,
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+			 "Configuring clocks for a legacy device-tree\n");
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+		dev_warn(data->dev,
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+			 "Please update DT to use assigned-clock-parents\n");
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+		clk_extern1 = devm_clk_get(dev, "extern1");
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+		if (IS_ERR(clk_extern1)) {
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+			dev_err(data->dev, "Can't retrieve clk extern1\n");
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+			return PTR_ERR(clk_extern1);
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+		}
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+
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+		ret = clk_set_parent(clk_extern1, data->clk_pll_a_out0);
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+		if (ret < 0) {
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+			dev_err(data->dev,
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+				"Set parent failed for clk extern1\n");
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+			return ret;
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+		}
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+
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+		clk_out_1 = devm_clk_get(dev, "pmc_clk_out_1");
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+		if (IS_ERR(clk_out_1)) {
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+			dev_err(data->dev, "Can't retrieve pmc_clk_out_1\n");
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+			return PTR_ERR(clk_out_1);
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+		}
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+
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+		ret = clk_set_parent(clk_out_1, clk_extern1);
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+		if (ret < 0) {
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+			dev_err(data->dev,
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+				"Set parent failed for pmc_clk_out_1\n");
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+			return ret;
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+		}
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+
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+		data->clk_cdev1 = clk_out_1;
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+	}
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+
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+	/*
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+	 * FIXME: There is some unknown dependency between audio mclk disable
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+	 * and suspend-resume functionality on Tegra30, although audio mclk is
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+	 * only needed for audio.
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+	 */
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+	ret = clk_prepare_enable(data->clk_cdev1);
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+	if (ret) {
215
+		dev_err(data->dev, "Can't enable cdev1: %d\n", ret);
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+		return ret;
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+	}
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218
 
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 	return 0;
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-
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-err_put_cdev1:
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-	clk_put(data->clk_cdev1);
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-err_put_pll_a_out0:
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-	clk_put(data->clk_pll_a_out0);
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-err_put_pll_a:
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-	clk_put(data->clk_pll_a);
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-err:
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-	return ret;
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220
 }
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221
 EXPORT_SYMBOL_GPL(tegra_asoc_utils_init);
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-
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-void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data)
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-{
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-	clk_put(data->clk_cdev1);
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-	clk_put(data->clk_pll_a_out0);
234
-	clk_put(data->clk_pll_a);
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-}
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-EXPORT_SYMBOL_GPL(tegra_asoc_utils_fini);
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222
 
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 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
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224
 MODULE_DESCRIPTION("Tegra ASoC utility code");