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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/sound/soc/sunxi/sun8i-codec-analog.c
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@@ -1,18 +1,9 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * This driver supports the analog controls for the internal codec
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  * found in Allwinner's A31s, A23, A33 and H3 SoCs.
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  *
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  * Copyright 2016 Chen-Yu Tsai <wens@csie.org>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #include <linux/io.h>
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@@ -26,6 +17,8 @@
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 #include <sound/soc.h>
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 #include <sound/soc-dapm.h>
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 #include <sound/tlv.h>
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+
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+#include "sun8i-adda-pr-regmap.h"
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 /* Codec analog control register offsets and bit fields */
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 #define SUN8I_ADDA_HP_VOLC		0x00
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@@ -119,81 +112,6 @@
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 #define SUN8I_ADDA_ADC_AP_EN_ADCREN		7
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 #define SUN8I_ADDA_ADC_AP_EN_ADCLEN		6
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 #define SUN8I_ADDA_ADC_AP_EN_ADCG		0
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-
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-/* Analog control register access bits */
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-#define ADDA_PR			0x0		/* PRCM base + 0x1c0 */
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-#define ADDA_PR_RESET			BIT(28)
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-#define ADDA_PR_WRITE			BIT(24)
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-#define ADDA_PR_ADDR_SHIFT		16
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-#define ADDA_PR_ADDR_MASK		GENMASK(4, 0)
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-#define ADDA_PR_DATA_IN_SHIFT		8
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-#define ADDA_PR_DATA_IN_MASK		GENMASK(7, 0)
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-#define ADDA_PR_DATA_OUT_SHIFT		0
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-#define ADDA_PR_DATA_OUT_MASK		GENMASK(7, 0)
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-
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-/* regmap access bits */
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-static int adda_reg_read(void *context, unsigned int reg, unsigned int *val)
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-{
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-	void __iomem *base = (void __iomem *)context;
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-	u32 tmp;
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-
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-	/* De-assert reset */
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-	writel(readl(base) | ADDA_PR_RESET, base);
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-
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-	/* Clear write bit */
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-	writel(readl(base) & ~ADDA_PR_WRITE, base);
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-
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-	/* Set register address */
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-	tmp = readl(base);
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-	tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);
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-	tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;
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-	writel(tmp, base);
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-
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-	/* Read back value */
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-	*val = readl(base) & ADDA_PR_DATA_OUT_MASK;
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-
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-	return 0;
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-}
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-
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-static int adda_reg_write(void *context, unsigned int reg, unsigned int val)
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-{
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-	void __iomem *base = (void __iomem *)context;
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-	u32 tmp;
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-
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-	/* De-assert reset */
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-	writel(readl(base) | ADDA_PR_RESET, base);
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-
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-	/* Set register address */
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-	tmp = readl(base);
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-	tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);
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-	tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;
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-	writel(tmp, base);
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-
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-	/* Set data to write */
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-	tmp = readl(base);
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-	tmp &= ~(ADDA_PR_DATA_IN_MASK << ADDA_PR_DATA_IN_SHIFT);
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-	tmp |= (val & ADDA_PR_DATA_IN_MASK) << ADDA_PR_DATA_IN_SHIFT;
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-	writel(tmp, base);
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-
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-	/* Set write bit to signal a write */
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-	writel(readl(base) | ADDA_PR_WRITE, base);
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-
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-	/* Clear write bit */
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-	writel(readl(base) & ~ADDA_PR_WRITE, base);
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-
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-	return 0;
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-}
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-
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-static const struct regmap_config adda_pr_regmap_cfg = {
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-	.name		= "adda-pr",
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-	.reg_bits	= 5,
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-	.reg_stride	= 1,
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-	.val_bits	= 8,
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-	.reg_read	= adda_reg_read,
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-	.reg_write	= adda_reg_write,
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-	.fast_io	= true,
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-	.max_register	= 24,
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-};
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 /* mixer controls */
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 static const struct snd_kcontrol_new sun8i_codec_mixer_controls[] = {
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@@ -901,18 +819,16 @@
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819
 
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 static int sun8i_codec_analog_probe(struct platform_device *pdev)
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 {
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-	struct resource *res;
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 	struct regmap *regmap;
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 	void __iomem *base;
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-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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-	base = devm_ioremap_resource(&pdev->dev, res);
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+	base = devm_platform_ioremap_resource(pdev, 0);
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 	if (IS_ERR(base)) {
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 		dev_err(&pdev->dev, "Failed to map the registers\n");
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 		return PTR_ERR(base);
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 	}
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-	regmap = devm_regmap_init(&pdev->dev, NULL, base, &adda_pr_regmap_cfg);
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+	regmap = sun8i_adda_pr_regmap_init(&pdev->dev, base);
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 	if (IS_ERR(regmap)) {
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 		dev_err(&pdev->dev, "Failed to create regmap\n");
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 		return PTR_ERR(regmap);