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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/sound/soc/rockchip/rockchip_spdif.h
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@@ -1,12 +1,9 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * ALSA SoC Audio Layer - Rockchip SPDIF transceiver driver
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  *
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  * Copyright (c) 2015 Collabora Ltd.
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  * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #ifndef _ROCKCHIP_SPDIF_H
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@@ -18,7 +15,19 @@
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 */
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 #define SPDIF_CFGR_CLK_DIV_SHIFT	(16)
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 #define SPDIF_CFGR_CLK_DIV_MASK		(0xff << SPDIF_CFGR_CLK_DIV_SHIFT)
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-#define SPDIF_CFGR_CLK_DIV(x)		(x << SPDIF_CFGR_CLK_DIV_SHIFT)
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+#define SPDIF_CFGR_CLK_DIV(x)		((x - 1) << SPDIF_CFGR_CLK_DIV_SHIFT)
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+
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+#define SPDIF_CFGR_CLR_MASK		BIT(7)
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+#define SPDIF_CFGR_CLR_EN		BIT(7)
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+#define SPDIF_CFGR_CLR_DIS		0
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+
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+#define SPDIF_CFGR_CSE_MASK		BIT(6)
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+#define SPDIF_CFGR_CSE_EN		BIT(6)
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+#define SPDIF_CFGR_CSE_DIS		0
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+
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+#define SPDIF_CFGR_ADJ_MASK		BIT(3)
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+#define SPDIF_CFGR_ADJ_LEFT_J		BIT(3)
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+#define SPDIF_CFGR_ADJ_RIGHT_J		0
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 #define SPDIF_CFGR_HALFWORD_SHIFT	2
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 #define SPDIF_CFGR_HALFWORD_DISABLE	(0 << SPDIF_CFGR_HALFWORD_SHIFT)
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@@ -59,5 +68,9 @@
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 #define SPDIF_INTSR	(0x0010)
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 #define SPDIF_XFER	(0x0018)
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 #define SPDIF_SMPDR	(0x0020)
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+#define SPDIF_VLDFRn(x)	(0x0060 + (x) * 4)
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+#define SPDIF_USRDRn(x)	(0x0090 + (x) * 4)
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+#define SPDIF_CHNSRn(x)	(0x00c0 + (x) * 4)
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+#define SPDIF_VERSION	(0x01c0)
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 #endif /* _ROCKCHIP_SPDIF_H */