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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/sound/soc/intel/skylake/skl-ssp-clk.c
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@@ -1,4 +1,4 @@
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-// SPDX-License-Identifier: GPL-2.0
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+// SPDX-License-Identifier: GPL-2.0-only
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 // Copyright(c) 2015-17 Intel Corporation
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 /*
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@@ -11,6 +11,7 @@
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 #include <linux/platform_device.h>
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 #include <linux/clk-provider.h>
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 #include <linux/clkdev.h>
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+#include <sound/intel-nhlt.h>
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 #include "skl.h"
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 #include "skl-ssp-clk.h"
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 #include "skl-topology.h"
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@@ -101,7 +102,7 @@
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 }
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 /* Sends dma control IPC to turn the clock ON/OFF */
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-static int skl_send_clk_dma_control(struct skl *skl,
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+static int skl_send_clk_dma_control(struct skl_dev *skl,
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 				struct skl_clk_rate_cfg_table *rcfg,
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 				u32 vbus_id, u8 clk_type,
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 				bool enable)
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@@ -152,7 +153,7 @@
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 	memcpy(i2s_config + sp_cfg->size, data, size);
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 	node_id = ((SKL_DMA_I2S_LINK_INPUT_CLASS << 8) | (vbus_id << 4));
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-	ret = skl_dsp_set_dma_control(skl->skl_sst, (u32 *)i2s_config,
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+	ret = skl_dsp_set_dma_control(skl, (u32 *)i2s_config,
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 					i2s_config_size, node_id);
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 	kfree(i2s_config);
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@@ -276,10 +277,8 @@
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 static void unregister_src_clk(struct skl_clk_data *dclk)
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 {
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-	u8 cnt = dclk->avail_clk_cnt;
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-
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-	while (cnt--)
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-		clkdev_drop(dclk->clk[cnt]->lookup);
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+	while (dclk->avail_clk_cnt--)
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+		clkdev_drop(dclk->clk[dclk->avail_clk_cnt]->lookup);
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 }
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 static int skl_register_parent_clks(struct device *dev,
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@@ -381,9 +380,11 @@
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 		if (clks[i].rate_cfg[0].rate == 0)
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 			continue;
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-		data->clk[i] = register_skl_clk(dev, &clks[i], clk_pdata, i);
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-		if (IS_ERR(data->clk[i])) {
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-			ret = PTR_ERR(data->clk[i]);
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+		data->clk[data->avail_clk_cnt] = register_skl_clk(dev,
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+				&clks[i], clk_pdata, i);
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+
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+		if (IS_ERR(data->clk[data->avail_clk_cnt])) {
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+			ret = PTR_ERR(data->clk[data->avail_clk_cnt]);
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 			goto err_unreg_skl_clk;
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 		}
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