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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/sound/soc/fsl/fsl_asrc.c
....@@ -19,68 +19,189 @@
1919 #include "fsl_asrc.h"
2020 
2121 #define IDEAL_RATIO_DECIMAL_DEPTH 26
22
+#define DIVIDER_NUM  64
2223 
2324 #define pair_err(fmt, ...) \
24
-	dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
25
+	dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
2526 
2627 #define pair_dbg(fmt, ...) \
27
-	dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
28
-
29
-/* Sample rates are aligned with that defined in pcm.h file */
30
-static const u8 process_option[][12][2] = {
31
-	/* 8kHz 11.025kHz 16kHz 22.05kHz 32kHz 44.1kHz 48kHz   64kHz   88.2kHz 96kHz   176kHz  192kHz */
32
-	{{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},	/* 5512Hz */
33
-	{{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},	/* 8kHz */
34
-	{{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},	/* 11025Hz */
35
-	{{1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},	/* 16kHz */
36
-	{{1, 2}, {1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},},	/* 22050Hz */
37
-	{{1, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},},	/* 32kHz */
38
-	{{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},},	/* 44.1kHz */
39
-	{{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},},	/* 48kHz */
40
-	{{2, 2}, {2, 2}, {2, 2}, {2, 1}, {1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},},	/* 64kHz */
41
-	{{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},},	/* 88.2kHz */
42
-	{{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},},	/* 96kHz */
43
-	{{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},},	/* 176kHz */
44
-	{{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},},	/* 192kHz */
45
-};
28
+	dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
4629 
4730 /* Corresponding to process_option */
48
-static int supported_input_rate[] = {
49
-	5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200,
50
-	96000, 176400, 192000,
31
+static unsigned int supported_asrc_rate[] = {
32
+	5512, 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
33
+	64000, 88200, 96000, 128000, 176400, 192000,
5134 };
5235 
53
-static int supported_asrc_rate[] = {
54
-	8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000,
36
+static struct snd_pcm_hw_constraint_list fsl_asrc_rate_constraints = {
37
+	.count = ARRAY_SIZE(supported_asrc_rate),
38
+	.list = supported_asrc_rate,
5539 };
5640 
57
-/**
41
+/*
5842  * The following tables map the relationship between asrc_inclk/asrc_outclk in
5943  * fsl_asrc.h and the registers of ASRCSR
6044  */
61
-static unsigned char input_clk_map_imx35[] = {
45
+static unsigned char input_clk_map_imx35[ASRC_CLK_MAP_LEN] = {
6246 	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
47
+	3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
48
+	3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
6349 };
6450 
65
-static unsigned char output_clk_map_imx35[] = {
51
+static unsigned char output_clk_map_imx35[ASRC_CLK_MAP_LEN] = {
6652 	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
53
+	3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
54
+	3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
6755 };
6856 
6957 /* i.MX53 uses the same map for input and output */
70
-static unsigned char input_clk_map_imx53[] = {
58
+static unsigned char input_clk_map_imx53[ASRC_CLK_MAP_LEN] = {
7159 /*	0x0  0x1  0x2  0x3  0x4  0x5  0x6  0x7  0x8  0x9  0xa  0xb  0xc  0xd  0xe  0xf */
7260 	0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
61
+	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
62
+	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
7363 };
7464 
75
-static unsigned char output_clk_map_imx53[] = {
65
+static unsigned char output_clk_map_imx53[ASRC_CLK_MAP_LEN] = {
7666 /*	0x0  0x1  0x2  0x3  0x4  0x5  0x6  0x7  0x8  0x9  0xa  0xb  0xc  0xd  0xe  0xf */
7767 	0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
68
+	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
69
+	0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
7870 };
7971 
80
-static unsigned char *clk_map[2];
72
+/*
73
+ * i.MX8QM/i.MX8QXP uses the same map for input and output.
74
+ * clk_map_imx8qm[0] is for i.MX8QM asrc0
75
+ * clk_map_imx8qm[1] is for i.MX8QM asrc1
76
+ * clk_map_imx8qxp[0] is for i.MX8QXP asrc0
77
+ * clk_map_imx8qxp[1] is for i.MX8QXP asrc1
78
+ */
79
+static unsigned char clk_map_imx8qm[2][ASRC_CLK_MAP_LEN] = {
80
+	{
81
+	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
82
+	0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
83
+	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
84
+	},
85
+	{
86
+	0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
87
+	0x0, 0x1, 0x2, 0x3, 0xb, 0xc, 0xf, 0xf, 0xd, 0xe, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
88
+	0x4, 0x5, 0x6, 0xf, 0x8, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
89
+	},
90
+};
91
+
92
+static unsigned char clk_map_imx8qxp[2][ASRC_CLK_MAP_LEN] = {
93
+	{
94
+	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
95
+	0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0xf, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xf,
96
+	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
97
+	},
98
+	{
99
+	0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0,
100
+	0x0, 0x1, 0x2, 0x3, 0x7, 0x8, 0xf, 0xf, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
101
+	0xf, 0xf, 0x6, 0xf, 0xf, 0xf, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
102
+	},
103
+};
104
+
105
+/*
106
+ * According to RM, the divider range is 1 ~ 8,
107
+ * prescaler is power of 2 from 1 ~ 128.
108
+ */
109
+static int asrc_clk_divider[DIVIDER_NUM] = {
110
+	1,  2,  4,  8,  16,  32,  64,  128,  /* divider = 1 */
111
+	2,  4,  8, 16,  32,  64, 128,  256,  /* divider = 2 */
112
+	3,  6, 12, 24,  48,  96, 192,  384,  /* divider = 3 */
113
+	4,  8, 16, 32,  64, 128, 256,  512,  /* divider = 4 */
114
+	5, 10, 20, 40,  80, 160, 320,  640,  /* divider = 5 */
115
+	6, 12, 24, 48,  96, 192, 384,  768,  /* divider = 6 */
116
+	7, 14, 28, 56, 112, 224, 448,  896,  /* divider = 7 */
117
+	8, 16, 32, 64, 128, 256, 512, 1024,  /* divider = 8 */
118
+};
119
+
120
+/*
121
+ * Check if the divider is available for internal ratio mode
122
+ */
123
+static bool fsl_asrc_divider_avail(int clk_rate, int rate, int *div)
124
+{
125
+	u32 rem, i;
126
+	u64 n;
127
+
128
+	if (div)
129
+		*div = 0;
130
+
131
+	if (clk_rate == 0 || rate == 0)
132
+		return false;
133
+
134
+	n = clk_rate;
135
+	rem = do_div(n, rate);
136
+
137
+	if (div)
138
+		*div = n;
139
+
140
+	if (rem != 0)
141
+		return false;
142
+
143
+	for (i = 0; i < DIVIDER_NUM; i++) {
144
+		if (n == asrc_clk_divider[i])
145
+			break;
146
+	}
147
+
148
+	if (i == DIVIDER_NUM)
149
+		return false;
150
+
151
+	return true;
152
+}
81153 
82154 /**
83
- * Request ASRC pair
155
+ * fsl_asrc_sel_proc - Select the pre-processing and post-processing options
156
+ * @inrate: input sample rate
157
+ * @outrate: output sample rate
158
+ * @pre_proc: return value for pre-processing option
159
+ * @post_proc: return value for post-processing option
160
+ *
161
+ * Make sure to exclude following unsupported cases before
162
+ * calling this function:
163
+ * 1) inrate > 8.125 * outrate
164
+ * 2) inrate > 16.125 * outrate
165
+ *
166
+ */
167
+static void fsl_asrc_sel_proc(int inrate, int outrate,
168
+			     int *pre_proc, int *post_proc)
169
+{
170
+	bool post_proc_cond2;
171
+	bool post_proc_cond0;
172
+
173
+	/* select pre_proc between [0, 2] */
174
+	if (inrate * 8 > 33 * outrate)
175
+		*pre_proc = 2;
176
+	else if (inrate * 8 > 15 * outrate) {
177
+		if (inrate > 152000)
178
+			*pre_proc = 2;
179
+		else
180
+			*pre_proc = 1;
181
+	} else if (inrate < 76000)
182
+		*pre_proc = 0;
183
+	else if (inrate > 152000)
184
+		*pre_proc = 2;
185
+	else
186
+		*pre_proc = 1;
187
+
188
+	/* Condition for selection of post-processing */
189
+	post_proc_cond2 = (inrate * 15 > outrate * 16 && outrate < 56000) ||
190
+			  (inrate > 56000 && outrate < 56000);
191
+	post_proc_cond0 = inrate * 23 < outrate * 8;
192
+
193
+	if (post_proc_cond2)
194
+		*post_proc = 2;
195
+	else if (post_proc_cond0)
196
+		*post_proc = 0;
197
+	else
198
+		*post_proc = 1;
199
+}
200
+
201
+/**
202
+ * fsl_asrc_request_pair - Request ASRC pair
203
+ * @channels: number of channels
204
+ * @pair: pointer to pair
84205  *
85206  * It assigns pair by the order of A->C->B because allocation of pair B,
86207  * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A
....@@ -89,15 +210,15 @@
89210 static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
90211 {
91212 	enum asrc_pair_index index = ASRC_INVALID_PAIR;
92
-	struct fsl_asrc *asrc_priv = pair->asrc_priv;
93
-	struct device *dev = &asrc_priv->pdev->dev;
213
+	struct fsl_asrc *asrc = pair->asrc;
214
+	struct device *dev = &asrc->pdev->dev;
94215 	unsigned long lock_flags;
95216 	int i, ret = 0;
96217 
97
-	spin_lock_irqsave(&asrc_priv->lock, lock_flags);
218
+	spin_lock_irqsave(&asrc->lock, lock_flags);
98219 
99220 	for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
100
-		if (asrc_priv->pair[i] != NULL)
221
+		if (asrc->pair[i] != NULL)
101222 			continue;
102223 
103224 		index = i;
....@@ -109,54 +230,58 @@
109230 	if (index == ASRC_INVALID_PAIR) {
110231 		dev_err(dev, "all pairs are busy now\n");
111232 		ret = -EBUSY;
112
-	} else if (asrc_priv->channel_avail < channels) {
233
+	} else if (asrc->channel_avail < channels) {
113234 		dev_err(dev, "can't afford required channels: %d\n", channels);
114235 		ret = -EINVAL;
115236 	} else {
116
-		asrc_priv->channel_avail -= channels;
117
-		asrc_priv->pair[index] = pair;
237
+		asrc->channel_avail -= channels;
238
+		asrc->pair[index] = pair;
118239 		pair->channels = channels;
119240 		pair->index = index;
120241 	}
121242 
122
-	spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
243
+	spin_unlock_irqrestore(&asrc->lock, lock_flags);
123244 
124245 	return ret;
125246 }
126247 
127248 /**
128
- * Release ASRC pair
249
+ * fsl_asrc_release_pair - Release ASRC pair
250
+ * @pair: pair to release
129251  *
130
- * It clears the resource from asrc_priv and releases the occupied channels.
252
+ * It clears the resource from asrc and releases the occupied channels.
131253  */
132254 static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
133255 {
134
-	struct fsl_asrc *asrc_priv = pair->asrc_priv;
256
+	struct fsl_asrc *asrc = pair->asrc;
135257 	enum asrc_pair_index index = pair->index;
136258 	unsigned long lock_flags;
137259 
138260 	/* Make sure the pair is disabled */
139
-	regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
261
+	regmap_update_bits(asrc->regmap, REG_ASRCTR,
140262 			   ASRCTR_ASRCEi_MASK(index), 0);
141263 
142
-	spin_lock_irqsave(&asrc_priv->lock, lock_flags);
264
+	spin_lock_irqsave(&asrc->lock, lock_flags);
143265 
144
-	asrc_priv->channel_avail += pair->channels;
145
-	asrc_priv->pair[index] = NULL;
266
+	asrc->channel_avail += pair->channels;
267
+	asrc->pair[index] = NULL;
146268 	pair->error = 0;
147269 
148
-	spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
270
+	spin_unlock_irqrestore(&asrc->lock, lock_flags);
149271 }
150272 
151273 /**
152
- * Configure input and output thresholds
274
+ * fsl_asrc_set_watermarks- configure input and output thresholds
275
+ * @pair: pointer to pair
276
+ * @in: input threshold
277
+ * @out: output threshold
153278  */
154279 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out)
155280 {
156
-	struct fsl_asrc *asrc_priv = pair->asrc_priv;
281
+	struct fsl_asrc *asrc = pair->asrc;
157282 	enum asrc_pair_index index = pair->index;
158283 
159
-	regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
284
+	regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
160285 			   ASRMCRi_EXTTHRSHi_MASK |
161286 			   ASRMCRi_INFIFO_THRESHOLD_MASK |
162287 			   ASRMCRi_OUTFIFO_THRESHOLD_MASK,
....@@ -166,7 +291,9 @@
166291 }
167292 
168293 /**
169
- * Calculate the total divisor between asrck clock rate and sample rate
294
+ * fsl_asrc_cal_asrck_divisor - Calculate the total divisor between asrck clock rate and sample rate
295
+ * @pair: pointer to pair
296
+ * @div: divider
170297  *
171298  * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider
172299  */
....@@ -182,14 +309,17 @@
182309 }
183310 
184311 /**
185
- * Calculate and set the ratio for Ideal Ratio mode only
312
+ * fsl_asrc_set_ideal_ratio - Calculate and set the ratio for Ideal Ratio mode only
313
+ * @pair: pointer to pair
314
+ * @inrate: input rate
315
+ * @outrate: output rate
186316  *
187317  * The ratio is a 32-bit fixed point value with 26 fractional bits.
188318  */
189319 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
190320 				    int inrate, int outrate)
191321 {
192
-	struct fsl_asrc *asrc_priv = pair->asrc_priv;
322
+	struct fsl_asrc *asrc = pair->asrc;
193323 	enum asrc_pair_index index = pair->index;
194324 	unsigned long ratio;
195325 	int i;
....@@ -218,29 +348,44 @@
218348 			break;
219349 	}
220350 
221
-	regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio);
222
-	regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24);
351
+	regmap_write(asrc->regmap, REG_ASRIDRL(index), ratio);
352
+	regmap_write(asrc->regmap, REG_ASRIDRH(index), ratio >> 24);
223353 
224354 	return 0;
225355 }
226356 
227357 /**
228
- * Configure the assigned ASRC pair
358
+ * fsl_asrc_config_pair - Configure the assigned ASRC pair
359
+ * @pair: pointer to pair
360
+ * @use_ideal_rate: boolean configuration
229361  *
230362  * It configures those ASRC registers according to a configuration instance
231363  * of struct asrc_config which includes in/output sample rate, width, channel
232364  * and clock settings.
365
+ *
366
+ * Note:
367
+ * The ideal ratio configuration can work with a flexible clock rate setting.
368
+ * Using IDEAL_RATIO_RATE gives a faster converting speed but overloads ASRC.
369
+ * For a regular audio playback, the clock rate should not be slower than an
370
+ * clock rate aligning with the output sample rate; For a use case requiring
371
+ * faster conversion, set use_ideal_rate to have the faster speed.
233372  */
234
-static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
373
+static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate)
235374 {
236
-	struct asrc_config *config = pair->config;
237
-	struct fsl_asrc *asrc_priv = pair->asrc_priv;
375
+	struct fsl_asrc_pair_priv *pair_priv = pair->private;
376
+	struct asrc_config *config = pair_priv->config;
377
+	struct fsl_asrc *asrc = pair->asrc;
378
+	struct fsl_asrc_priv *asrc_priv = asrc->private;
238379 	enum asrc_pair_index index = pair->index;
380
+	enum asrc_word_width input_word_width;
381
+	enum asrc_word_width output_word_width;
239382 	u32 inrate, outrate, indiv, outdiv;
240383 	u32 clk_index[2], div[2];
384
+	u64 clk_rate;
241385 	int in, out, channels;
386
+	int pre_proc, post_proc;
242387 	struct clk *clk;
243
-	bool ideal;
388
+	bool ideal, div_avail;
244389 
245390 	if (!config) {
246391 		pair_err("invalid pair config\n");
....@@ -253,9 +398,32 @@
253398 		return -EINVAL;
254399 	}
255400 
256
-	/* Validate output width */
257
-	if (config->output_word_width == ASRC_WIDTH_8_BIT) {
258
-		pair_err("does not support 8bit width output\n");
401
+	switch (snd_pcm_format_width(config->input_format)) {
402
+	case 8:
403
+		input_word_width = ASRC_WIDTH_8_BIT;
404
+		break;
405
+	case 16:
406
+		input_word_width = ASRC_WIDTH_16_BIT;
407
+		break;
408
+	case 24:
409
+		input_word_width = ASRC_WIDTH_24_BIT;
410
+		break;
411
+	default:
412
+		pair_err("does not support this input format, %d\n",
413
+			 config->input_format);
414
+		return -EINVAL;
415
+	}
416
+
417
+	switch (snd_pcm_format_width(config->output_format)) {
418
+	case 16:
419
+		output_word_width = ASRC_WIDTH_16_BIT;
420
+		break;
421
+	case 24:
422
+		output_word_width = ASRC_WIDTH_24_BIT;
423
+		break;
424
+	default:
425
+		pair_err("does not support this output format, %d\n",
426
+			 config->output_format);
259427 		return -EINVAL;
260428 	}
261429 
....@@ -264,11 +432,11 @@
264432 	ideal = config->inclk == INCLK_NONE;
265433 
266434 	/* Validate input and output sample rates */
267
-	for (in = 0; in < ARRAY_SIZE(supported_input_rate); in++)
268
-		if (inrate == supported_input_rate[in])
435
+	for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++)
436
+		if (inrate == supported_asrc_rate[in])
269437 			break;
270438 
271
-	if (in == ARRAY_SIZE(supported_input_rate)) {
439
+	if (in == ARRAY_SIZE(supported_asrc_rate)) {
272440 		pair_err("unsupported input sample rate: %dHz\n", inrate);
273441 		return -EINVAL;
274442 	}
....@@ -282,7 +450,7 @@
282450 		return -EINVAL;
283451 	}
284452 
285
-	if ((outrate >= 8000 && outrate <= 30000) &&
453
+	if ((outrate >= 5512 && outrate <= 30000) &&
286454 	    (outrate > 24 * inrate || inrate > 8 * outrate)) {
287455 		pair_err("exceed supported ratio range [1/24, 8] for \
288456 				inrate/outrate: %d/%d\n", inrate, outrate);
....@@ -290,52 +458,65 @@
290458 	}
291459 
292460 	/* Validate input and output clock sources */
293
-	clk_index[IN] = clk_map[IN][config->inclk];
294
-	clk_index[OUT] = clk_map[OUT][config->outclk];
461
+	clk_index[IN] = asrc_priv->clk_map[IN][config->inclk];
462
+	clk_index[OUT] = asrc_priv->clk_map[OUT][config->outclk];
295463 
296464 	/* We only have output clock for ideal ratio mode */
297465 	clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
298466 
299
-	div[IN] = clk_get_rate(clk) / inrate;
300
-	if (div[IN] == 0) {
467
+	clk_rate = clk_get_rate(clk);
468
+	div_avail = fsl_asrc_divider_avail(clk_rate, inrate, &div[IN]);
469
+
470
+	/*
471
+	 * The divider range is [1, 1024], defined by the hardware. For non-
472
+	 * ideal ratio configuration, clock rate has to be strictly aligned
473
+	 * with the sample rate. For ideal ratio configuration, clock rates
474
+	 * only result in different converting speeds. So remainder does not
475
+	 * matter, as long as we keep the divider within its valid range.
476
+	 */
477
+	if (div[IN] == 0 || (!ideal && !div_avail)) {
301478 		pair_err("failed to support input sample rate %dHz by asrck_%x\n",
302479 				inrate, clk_index[ideal ? OUT : IN]);
303480 		return -EINVAL;
304481 	}
305482 
483
+	div[IN] = min_t(u32, 1024, div[IN]);
484
+
306485 	clk = asrc_priv->asrck_clk[clk_index[OUT]];
307
-
308
-	/* Use fixed output rate for Ideal Ratio mode (INCLK_NONE) */
309
-	if (ideal)
310
-		div[OUT] = clk_get_rate(clk) / IDEAL_RATIO_RATE;
486
+	clk_rate = clk_get_rate(clk);
487
+	if (ideal && use_ideal_rate)
488
+		div_avail = fsl_asrc_divider_avail(clk_rate, IDEAL_RATIO_RATE, &div[OUT]);
311489 	else
312
-		div[OUT] = clk_get_rate(clk) / outrate;
490
+		div_avail = fsl_asrc_divider_avail(clk_rate, outrate, &div[OUT]);
313491 
314
-	if (div[OUT] == 0) {
492
+	/* Output divider has the same limitation as the input one */
493
+	if (div[OUT] == 0 || (!ideal && !div_avail)) {
315494 		pair_err("failed to support output sample rate %dHz by asrck_%x\n",
316495 				outrate, clk_index[OUT]);
317496 		return -EINVAL;
318497 	}
319498 
499
+	div[OUT] = min_t(u32, 1024, div[OUT]);
500
+
320501 	/* Set the channel number */
321502 	channels = config->channel_num;
322503 
323
-	if (asrc_priv->channel_bits < 4)
504
+	if (asrc_priv->soc->channel_bits < 4)
324505 		channels /= 2;
325506 
326507 	/* Update channels for current pair */
327
-	regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR,
328
-			   ASRCNCR_ANCi_MASK(index, asrc_priv->channel_bits),
329
-			   ASRCNCR_ANCi(index, channels, asrc_priv->channel_bits));
508
+	regmap_update_bits(asrc->regmap, REG_ASRCNCR,
509
+			   ASRCNCR_ANCi_MASK(index, asrc_priv->soc->channel_bits),
510
+			   ASRCNCR_ANCi(index, channels, asrc_priv->soc->channel_bits));
330511 
331512 	/* Default setting: Automatic selection for processing mode */
332
-	regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
513
+	regmap_update_bits(asrc->regmap, REG_ASRCTR,
333514 			   ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index));
334
-	regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
515
+	regmap_update_bits(asrc->regmap, REG_ASRCTR,
335516 			   ASRCTR_USRi_MASK(index), 0);
336517 
337518 	/* Set the input and output clock sources */
338
-	regmap_update_bits(asrc_priv->regmap, REG_ASRCSR,
519
+	regmap_update_bits(asrc->regmap, REG_ASRCSR,
339520 			   ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index),
340521 			   ASRCSR_AICS(index, clk_index[IN]) |
341522 			   ASRCSR_AOCS(index, clk_index[OUT]));
....@@ -345,19 +526,19 @@
345526 	outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]);
346527 
347528 	/* Suppose indiv and outdiv includes prescaler, so add its MASK too */
348
-	regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index),
529
+	regmap_update_bits(asrc->regmap, REG_ASRCDR(index),
349530 			   ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) |
350531 			   ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index),
351532 			   ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv));
352533 
353534 	/* Implement word_width configurations */
354
-	regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index),
535
+	regmap_update_bits(asrc->regmap, REG_ASRMCR1(index),
355536 			   ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK,
356
-			   ASRMCR1i_OW16(config->output_word_width) |
357
-			   ASRMCR1i_IWD(config->input_word_width));
537
+			   ASRMCR1i_OW16(output_word_width) |
538
+			   ASRMCR1i_IWD(input_word_width));
358539 
359540 	/* Enable BUFFER STALL */
360
-	regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
541
+	regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
361542 			   ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi);
362543 
363544 	/* Set default thresholds for input and output FIFO */
....@@ -369,94 +550,155 @@
369550 		return 0;
370551 
371552 	/* Clear ASTSx bit to use Ideal Ratio mode */
372
-	regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
553
+	regmap_update_bits(asrc->regmap, REG_ASRCTR,
373554 			   ASRCTR_ATSi_MASK(index), 0);
374555 
375556 	/* Enable Ideal Ratio mode */
376
-	regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
557
+	regmap_update_bits(asrc->regmap, REG_ASRCTR,
377558 			   ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
378559 			   ASRCTR_IDR(index) | ASRCTR_USR(index));
379560 
561
+	fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc);
562
+
380563 	/* Apply configurations for pre- and post-processing */
381
-	regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
564
+	regmap_update_bits(asrc->regmap, REG_ASRCFG,
382565 			   ASRCFG_PREMODi_MASK(index) |	ASRCFG_POSTMODi_MASK(index),
383
-			   ASRCFG_PREMOD(index, process_option[in][out][0]) |
384
-			   ASRCFG_POSTMOD(index, process_option[in][out][1]));
566
+			   ASRCFG_PREMOD(index, pre_proc) |
567
+			   ASRCFG_POSTMOD(index, post_proc));
385568 
386569 	return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
387570 }
388571 
389572 /**
390
- * Start the assigned ASRC pair
573
+ * fsl_asrc_start_pair - Start the assigned ASRC pair
574
+ * @pair: pointer to pair
391575  *
392576  * It enables the assigned pair and makes it stopped at the stall level.
393577  */
394578 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
395579 {
396
-	struct fsl_asrc *asrc_priv = pair->asrc_priv;
580
+	struct fsl_asrc *asrc = pair->asrc;
397581 	enum asrc_pair_index index = pair->index;
398582 	int reg, retry = 10, i;
399583 
400584 	/* Enable the current pair */
401
-	regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
585
+	regmap_update_bits(asrc->regmap, REG_ASRCTR,
402586 			   ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index));
403587 
404588 	/* Wait for status of initialization */
405589 	do {
406590 		udelay(5);
407
-		regmap_read(asrc_priv->regmap, REG_ASRCFG, &reg);
591
+		regmap_read(asrc->regmap, REG_ASRCFG, &reg);
408592 		reg &= ASRCFG_INIRQi_MASK(index);
409593 	} while (!reg && --retry);
410594 
411595 	/* Make the input fifo to ASRC STALL level */
412
-	regmap_read(asrc_priv->regmap, REG_ASRCNCR, &reg);
596
+	regmap_read(asrc->regmap, REG_ASRCNCR, &reg);
413597 	for (i = 0; i < pair->channels * 4; i++)
414
-		regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0);
598
+		regmap_write(asrc->regmap, REG_ASRDI(index), 0);
415599 
416600 	/* Enable overload interrupt */
417
-	regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE);
601
+	regmap_write(asrc->regmap, REG_ASRIER, ASRIER_AOLIE);
418602 }
419603 
420604 /**
421
- * Stop the assigned ASRC pair
605
+ * fsl_asrc_stop_pair - Stop the assigned ASRC pair
606
+ * @pair: pointer to pair
422607  */
423608 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
424609 {
425
-	struct fsl_asrc *asrc_priv = pair->asrc_priv;
610
+	struct fsl_asrc *asrc = pair->asrc;
426611 	enum asrc_pair_index index = pair->index;
427612 
428613 	/* Stop the current pair */
429
-	regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
614
+	regmap_update_bits(asrc->regmap, REG_ASRCTR,
430615 			   ASRCTR_ASRCEi_MASK(index), 0);
431616 }
432617 
433618 /**
434
- * Get DMA channel according to the pair and direction.
619
+ * fsl_asrc_get_dma_channel- Get DMA channel according to the pair and direction.
620
+ * @pair: pointer to pair
621
+ * @dir: DMA direction
435622  */
436
-struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir)
623
+static struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair,
624
+						 bool dir)
437625 {
438
-	struct fsl_asrc *asrc_priv = pair->asrc_priv;
626
+	struct fsl_asrc *asrc = pair->asrc;
439627 	enum asrc_pair_index index = pair->index;
440628 	char name[4];
441629 
442630 	sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a');
443631 
444
-	return dma_request_slave_channel(&asrc_priv->pdev->dev, name);
632
+	return dma_request_slave_channel(&asrc->pdev->dev, name);
445633 }
446
-EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel);
634
+
635
+static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream,
636
+				struct snd_soc_dai *dai)
637
+{
638
+	struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
639
+	struct fsl_asrc_priv *asrc_priv = asrc->private;
640
+
641
+	/* Odd channel number is not valid for older ASRC (channel_bits==3) */
642
+	if (asrc_priv->soc->channel_bits == 3)
643
+		snd_pcm_hw_constraint_step(substream->runtime, 0,
644
+					   SNDRV_PCM_HW_PARAM_CHANNELS, 2);
645
+
646
+
647
+	return snd_pcm_hw_constraint_list(substream->runtime, 0,
648
+			SNDRV_PCM_HW_PARAM_RATE, &fsl_asrc_rate_constraints);
649
+}
650
+
651
+/* Select proper clock source for internal ratio mode */
652
+static void fsl_asrc_select_clk(struct fsl_asrc_priv *asrc_priv,
653
+				struct fsl_asrc_pair *pair,
654
+				int in_rate,
655
+				int out_rate)
656
+{
657
+	struct fsl_asrc_pair_priv *pair_priv = pair->private;
658
+	struct asrc_config *config = pair_priv->config;
659
+	int rate[2], select_clk[2]; /* Array size 2 means IN and OUT */
660
+	int clk_rate, clk_index;
661
+	int i = 0, j = 0;
662
+
663
+	rate[IN] = in_rate;
664
+	rate[OUT] = out_rate;
665
+
666
+	/* Select proper clock source for internal ratio mode */
667
+	for (j = 0; j < 2; j++) {
668
+		for (i = 0; i < ASRC_CLK_MAP_LEN; i++) {
669
+			clk_index = asrc_priv->clk_map[j][i];
670
+			clk_rate = clk_get_rate(asrc_priv->asrck_clk[clk_index]);
671
+			/* Only match a perfect clock source with no remainder */
672
+			if (fsl_asrc_divider_avail(clk_rate, rate[j], NULL))
673
+				break;
674
+		}
675
+
676
+		select_clk[j] = i;
677
+	}
678
+
679
+	/* Switch to ideal ratio mode if there is no proper clock source */
680
+	if (select_clk[IN] == ASRC_CLK_MAP_LEN || select_clk[OUT] == ASRC_CLK_MAP_LEN) {
681
+		select_clk[IN] = INCLK_NONE;
682
+		select_clk[OUT] = OUTCLK_ASRCK1_CLK;
683
+	}
684
+
685
+	config->inclk = select_clk[IN];
686
+	config->outclk = select_clk[OUT];
687
+}
447688 
448689 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
449690 				  struct snd_pcm_hw_params *params,
450691 				  struct snd_soc_dai *dai)
451692 {
452
-	struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
453
-	int width = params_width(params);
693
+	struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
694
+	struct fsl_asrc_priv *asrc_priv = asrc->private;
454695 	struct snd_pcm_runtime *runtime = substream->runtime;
455696 	struct fsl_asrc_pair *pair = runtime->private_data;
697
+	struct fsl_asrc_pair_priv *pair_priv = pair->private;
456698 	unsigned int channels = params_channels(params);
457699 	unsigned int rate = params_rate(params);
458700 	struct asrc_config config;
459
-	int word_width, ret;
701
+	int ret;
460702 
461703 	ret = fsl_asrc_request_pair(channels, pair);
462704 	if (ret) {
....@@ -464,36 +706,28 @@
464706 		return ret;
465707 	}
466708 
467
-	pair->config = &config;
468
-
469
-	if (width == 16)
470
-		width = ASRC_WIDTH_16_BIT;
471
-	else
472
-		width = ASRC_WIDTH_24_BIT;
473
-
474
-	if (asrc_priv->asrc_width == 16)
475
-		word_width = ASRC_WIDTH_16_BIT;
476
-	else
477
-		word_width = ASRC_WIDTH_24_BIT;
709
+	pair_priv->config = &config;
478710 
479711 	config.pair = pair->index;
480712 	config.channel_num = channels;
481
-	config.inclk = INCLK_NONE;
482
-	config.outclk = OUTCLK_ASRCK1_CLK;
483713 
484714 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
485
-		config.input_word_width   = width;
486
-		config.output_word_width  = word_width;
715
+		config.input_format   = params_format(params);
716
+		config.output_format  = asrc->asrc_format;
487717 		config.input_sample_rate  = rate;
488
-		config.output_sample_rate = asrc_priv->asrc_rate;
718
+		config.output_sample_rate = asrc->asrc_rate;
489719 	} else {
490
-		config.input_word_width   = word_width;
491
-		config.output_word_width  = width;
492
-		config.input_sample_rate  = asrc_priv->asrc_rate;
720
+		config.input_format   = asrc->asrc_format;
721
+		config.output_format  = params_format(params);
722
+		config.input_sample_rate  = asrc->asrc_rate;
493723 		config.output_sample_rate = rate;
494724 	}
495725 
496
-	ret = fsl_asrc_config_pair(pair);
726
+	fsl_asrc_select_clk(asrc_priv, pair,
727
+			    config.input_sample_rate,
728
+			    config.output_sample_rate);
729
+
730
+	ret = fsl_asrc_config_pair(pair, false);
497731 	if (ret) {
498732 		dev_err(dai->dev, "fail to config asrc pair\n");
499733 		return ret;
....@@ -539,6 +773,7 @@
539773 }
540774 
541775 static const struct snd_soc_dai_ops fsl_asrc_dai_ops = {
776
+	.startup      = fsl_asrc_dai_startup,
542777 	.hw_params    = fsl_asrc_dai_hw_params,
543778 	.hw_free      = fsl_asrc_dai_hw_free,
544779 	.trigger      = fsl_asrc_dai_trigger,
....@@ -546,18 +781,17 @@
546781 
547782 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai)
548783 {
549
-	struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
784
+	struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai);
550785 
551
-	snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx,
552
-				  &asrc_priv->dma_params_rx);
786
+	snd_soc_dai_init_dma_data(dai, &asrc->dma_params_tx,
787
+				  &asrc->dma_params_rx);
553788 
554789 	return 0;
555790 }
556791 
557
-#define FSL_ASRC_RATES		 SNDRV_PCM_RATE_8000_192000
558792 #define FSL_ASRC_FORMATS	(SNDRV_PCM_FMTBIT_S24_LE | \
559793 				 SNDRV_PCM_FMTBIT_S16_LE | \
560
-				 SNDRV_PCM_FMTBIT_S20_3LE)
794
+				 SNDRV_PCM_FMTBIT_S24_3LE)
561795 
562796 static struct snd_soc_dai_driver fsl_asrc_dai = {
563797 	.probe = fsl_asrc_dai_probe,
....@@ -565,14 +799,19 @@
565799 		.stream_name = "ASRC-Playback",
566800 		.channels_min = 1,
567801 		.channels_max = 10,
568
-		.rates = FSL_ASRC_RATES,
569
-		.formats = FSL_ASRC_FORMATS,
802
+		.rate_min = 5512,
803
+		.rate_max = 192000,
804
+		.rates = SNDRV_PCM_RATE_KNOT,
805
+		.formats = FSL_ASRC_FORMATS |
806
+			   SNDRV_PCM_FMTBIT_S8,
570807 	},
571808 	.capture = {
572809 		.stream_name = "ASRC-Capture",
573810 		.channels_min = 1,
574811 		.channels_max = 10,
575
-		.rates = FSL_ASRC_RATES,
812
+		.rate_min = 5512,
813
+		.rate_max = 192000,
814
+		.rates = SNDRV_PCM_RATE_KNOT,
576815 		.formats = FSL_ASRC_FORMATS,
577816 	},
578817 	.ops = &fsl_asrc_dai_ops,
....@@ -722,48 +961,56 @@
722961 };
723962 
724963 /**
725
- * Initialize ASRC registers with a default configurations
964
+ * fsl_asrc_init - Initialize ASRC registers with a default configuration
965
+ * @asrc: ASRC context
726966  */
727
-static int fsl_asrc_init(struct fsl_asrc *asrc_priv)
967
+static int fsl_asrc_init(struct fsl_asrc *asrc)
728968 {
969
+	unsigned long ipg_rate;
970
+
729971 	/* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
730
-	regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
972
+	regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
731973 
732974 	/* Disable interrupt by default */
733
-	regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0);
975
+	regmap_write(asrc->regmap, REG_ASRIER, 0x0);
734976 
735977 	/* Apply recommended settings for parameters from Reference Manual */
736
-	regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff);
737
-	regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555);
738
-	regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280);
739
-	regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280);
740
-	regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280);
978
+	regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff);
979
+	regmap_write(asrc->regmap, REG_ASRPM2, 0x255555);
980
+	regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280);
981
+	regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280);
982
+	regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280);
741983 
742984 	/* Base address for task queue FIFO. Set to 0x7C */
743
-	regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1,
985
+	regmap_update_bits(asrc->regmap, REG_ASRTFR1,
744986 			   ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
745987 
746
-	/* Set the processing clock for 76KHz to 133M */
747
-	regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6);
748
-
749
-	/* Set the processing clock for 56KHz to 133M */
750
-	return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947);
988
+	/*
989
+	 * Set the period of the 76KHz and 56KHz sampling clocks based on
990
+	 * the ASRC processing clock.
991
+	 * On iMX6, ipg_clk = 133MHz, REG_ASR76K = 0x06D6, REG_ASR56K = 0x0947
992
+	 */
993
+	ipg_rate = clk_get_rate(asrc->ipg_clk);
994
+	regmap_write(asrc->regmap, REG_ASR76K, ipg_rate / 76000);
995
+	return regmap_write(asrc->regmap, REG_ASR56K, ipg_rate / 56000);
751996 }
752997 
753998 /**
754
- * Interrupt handler for ASRC
999
+ * fsl_asrc_isr- Interrupt handler for ASRC
1000
+ * @irq: irq number
1001
+ * @dev_id: ASRC context
7551002  */
7561003 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
7571004 {
758
-	struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id;
759
-	struct device *dev = &asrc_priv->pdev->dev;
1005
+	struct fsl_asrc *asrc = (struct fsl_asrc *)dev_id;
1006
+	struct device *dev = &asrc->pdev->dev;
7601007 	enum asrc_pair_index index;
7611008 	u32 status;
7621009 
763
-	regmap_read(asrc_priv->regmap, REG_ASRSTR, &status);
1010
+	regmap_read(asrc->regmap, REG_ASRSTR, &status);
7641011 
7651012 	/* Clean overload error */
766
-	regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE);
1013
+	regmap_write(asrc->regmap, REG_ASRSTR, ASRSTR_AOLE);
7671014 
7681015 	/*
7691016 	 * We here use dev_dbg() for all exceptions because ASRC itself does
....@@ -771,31 +1018,31 @@
7711018 	 * interrupt would result a ridged conversion.
7721019 	 */
7731020 	for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
774
-		if (!asrc_priv->pair[index])
1021
+		if (!asrc->pair[index])
7751022 			continue;
7761023 
7771024 		if (status & ASRSTR_ATQOL) {
778
-			asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
1025
+			asrc->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
7791026 			dev_dbg(dev, "ASRC Task Queue FIFO overload\n");
7801027 		}
7811028 
7821029 		if (status & ASRSTR_AOOL(index)) {
783
-			asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
1030
+			asrc->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
7841031 			pair_dbg("Output Task Overload\n");
7851032 		}
7861033 
7871034 		if (status & ASRSTR_AIOL(index)) {
788
-			asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
1035
+			asrc->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
7891036 			pair_dbg("Input Task Overload\n");
7901037 		}
7911038 
7921039 		if (status & ASRSTR_AODO(index)) {
793
-			asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
1040
+			asrc->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
7941041 			pair_dbg("Output Data Buffer has overflowed\n");
7951042 		}
7961043 
7971044 		if (status & ASRSTR_AIDU(index)) {
798
-			asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
1045
+			asrc->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
7991046 			pair_dbg("Input Data Buffer has underflowed\n");
8001047 		}
8011048 	}
....@@ -803,20 +1050,33 @@
8031050 	return IRQ_HANDLED;
8041051 }
8051052 
1053
+static int fsl_asrc_get_fifo_addr(u8 dir, enum asrc_pair_index index)
1054
+{
1055
+	return REG_ASRDx(dir, index);
1056
+}
1057
+
8061058 static int fsl_asrc_probe(struct platform_device *pdev)
8071059 {
8081060 	struct device_node *np = pdev->dev.of_node;
809
-	struct fsl_asrc *asrc_priv;
1061
+	struct fsl_asrc_priv *asrc_priv;
1062
+	struct fsl_asrc *asrc;
8101063 	struct resource *res;
8111064 	void __iomem *regs;
8121065 	int irq, ret, i;
1066
+	u32 map_idx;
8131067 	char tmp[16];
1068
+	u32 width;
1069
+
1070
+	asrc = devm_kzalloc(&pdev->dev, sizeof(*asrc), GFP_KERNEL);
1071
+	if (!asrc)
1072
+		return -ENOMEM;
8141073 
8151074 	asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL);
8161075 	if (!asrc_priv)
8171076 		return -ENOMEM;
8181077 
819
-	asrc_priv->pdev = pdev;
1078
+	asrc->pdev = pdev;
1079
+	asrc->private = asrc_priv;
8201080 
8211081 	/* Get the addresses and IRQ */
8221082 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
....@@ -824,42 +1084,40 @@
8241084 	if (IS_ERR(regs))
8251085 		return PTR_ERR(regs);
8261086 
827
-	asrc_priv->paddr = res->start;
1087
+	asrc->paddr = res->start;
8281088 
829
-	asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs,
830
-						      &fsl_asrc_regmap_config);
831
-	if (IS_ERR(asrc_priv->regmap)) {
1089
+	asrc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs,
1090
+						 &fsl_asrc_regmap_config);
1091
+	if (IS_ERR(asrc->regmap)) {
8321092 		dev_err(&pdev->dev, "failed to init regmap\n");
833
-		return PTR_ERR(asrc_priv->regmap);
1093
+		return PTR_ERR(asrc->regmap);
8341094 	}
8351095 
8361096 	irq = platform_get_irq(pdev, 0);
837
-	if (irq < 0) {
838
-		dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
1097
+	if (irq < 0)
8391098 		return irq;
840
-	}
8411099 
8421100 	ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
843
-			       dev_name(&pdev->dev), asrc_priv);
1101
+			       dev_name(&pdev->dev), asrc);
8441102 	if (ret) {
8451103 		dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
8461104 		return ret;
8471105 	}
8481106 
849
-	asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem");
850
-	if (IS_ERR(asrc_priv->mem_clk)) {
1107
+	asrc->mem_clk = devm_clk_get(&pdev->dev, "mem");
1108
+	if (IS_ERR(asrc->mem_clk)) {
8511109 		dev_err(&pdev->dev, "failed to get mem clock\n");
852
-		return PTR_ERR(asrc_priv->mem_clk);
1110
+		return PTR_ERR(asrc->mem_clk);
8531111 	}
8541112 
855
-	asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
856
-	if (IS_ERR(asrc_priv->ipg_clk)) {
1113
+	asrc->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
1114
+	if (IS_ERR(asrc->ipg_clk)) {
8571115 		dev_err(&pdev->dev, "failed to get ipg clock\n");
858
-		return PTR_ERR(asrc_priv->ipg_clk);
1116
+		return PTR_ERR(asrc->ipg_clk);
8591117 	}
8601118 
861
-	asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba");
862
-	if (IS_ERR(asrc_priv->spba_clk))
1119
+	asrc->spba_clk = devm_clk_get(&pdev->dev, "spba");
1120
+	if (IS_ERR(asrc->spba_clk))
8631121 		dev_warn(&pdev->dev, "failed to get spba clock\n");
8641122 
8651123 	for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
....@@ -871,46 +1129,93 @@
8711129 		}
8721130 	}
8731131 
874
-	if (of_device_is_compatible(np, "fsl,imx35-asrc")) {
875
-		asrc_priv->channel_bits = 3;
876
-		clk_map[IN] = input_clk_map_imx35;
877
-		clk_map[OUT] = output_clk_map_imx35;
878
-	} else {
879
-		asrc_priv->channel_bits = 4;
880
-		clk_map[IN] = input_clk_map_imx53;
881
-		clk_map[OUT] = output_clk_map_imx53;
1132
+	asrc_priv->soc = of_device_get_match_data(&pdev->dev);
1133
+	if (!asrc_priv->soc) {
1134
+		dev_err(&pdev->dev, "failed to get soc data\n");
1135
+		return -ENODEV;
8821136 	}
8831137 
884
-	ret = fsl_asrc_init(asrc_priv);
1138
+	asrc->use_edma = asrc_priv->soc->use_edma;
1139
+	asrc->get_dma_channel = fsl_asrc_get_dma_channel;
1140
+	asrc->request_pair = fsl_asrc_request_pair;
1141
+	asrc->release_pair = fsl_asrc_release_pair;
1142
+	asrc->get_fifo_addr = fsl_asrc_get_fifo_addr;
1143
+	asrc->pair_priv_size = sizeof(struct fsl_asrc_pair_priv);
1144
+
1145
+	if (of_device_is_compatible(np, "fsl,imx35-asrc")) {
1146
+		asrc_priv->clk_map[IN] = input_clk_map_imx35;
1147
+		asrc_priv->clk_map[OUT] = output_clk_map_imx35;
1148
+	} else if (of_device_is_compatible(np, "fsl,imx53-asrc")) {
1149
+		asrc_priv->clk_map[IN] = input_clk_map_imx53;
1150
+		asrc_priv->clk_map[OUT] = output_clk_map_imx53;
1151
+	} else if (of_device_is_compatible(np, "fsl,imx8qm-asrc") ||
1152
+		   of_device_is_compatible(np, "fsl,imx8qxp-asrc")) {
1153
+		ret = of_property_read_u32(np, "fsl,asrc-clk-map", &map_idx);
1154
+		if (ret) {
1155
+			dev_err(&pdev->dev, "failed to get clk map index\n");
1156
+			return ret;
1157
+		}
1158
+
1159
+		if (map_idx > 1) {
1160
+			dev_err(&pdev->dev, "unsupported clk map index\n");
1161
+			return -EINVAL;
1162
+		}
1163
+		if (of_device_is_compatible(np, "fsl,imx8qm-asrc")) {
1164
+			asrc_priv->clk_map[IN] = clk_map_imx8qm[map_idx];
1165
+			asrc_priv->clk_map[OUT] = clk_map_imx8qm[map_idx];
1166
+		} else {
1167
+			asrc_priv->clk_map[IN] = clk_map_imx8qxp[map_idx];
1168
+			asrc_priv->clk_map[OUT] = clk_map_imx8qxp[map_idx];
1169
+		}
1170
+	}
1171
+
1172
+	ret = fsl_asrc_init(asrc);
8851173 	if (ret) {
8861174 		dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
8871175 		return ret;
8881176 	}
8891177 
890
-	asrc_priv->channel_avail = 10;
1178
+	asrc->channel_avail = 10;
8911179 
8921180 	ret = of_property_read_u32(np, "fsl,asrc-rate",
893
-				   &asrc_priv->asrc_rate);
1181
+				   &asrc->asrc_rate);
8941182 	if (ret) {
8951183 		dev_err(&pdev->dev, "failed to get output rate\n");
8961184 		return ret;
8971185 	}
8981186 
899
-	ret = of_property_read_u32(np, "fsl,asrc-width",
900
-				   &asrc_priv->asrc_width);
1187
+	ret = of_property_read_u32(np, "fsl,asrc-format", &asrc->asrc_format);
9011188 	if (ret) {
902
-		dev_err(&pdev->dev, "failed to get output width\n");
903
-		return ret;
1189
+		ret = of_property_read_u32(np, "fsl,asrc-width", &width);
1190
+		if (ret) {
1191
+			dev_err(&pdev->dev, "failed to decide output format\n");
1192
+			return ret;
1193
+		}
1194
+
1195
+		switch (width) {
1196
+		case 16:
1197
+			asrc->asrc_format = SNDRV_PCM_FORMAT_S16_LE;
1198
+			break;
1199
+		case 24:
1200
+			asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
1201
+			break;
1202
+		default:
1203
+			dev_warn(&pdev->dev,
1204
+				 "unsupported width, use default S24_LE\n");
1205
+			asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
1206
+			break;
1207
+		}
9041208 	}
9051209 
906
-	if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) {
907
-		dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n");
908
-		asrc_priv->asrc_width = 24;
1210
+	if (!(FSL_ASRC_FORMATS & (1ULL << asrc->asrc_format))) {
1211
+		dev_warn(&pdev->dev, "unsupported width, use default S24_LE\n");
1212
+		asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
9091213 	}
9101214 
911
-	platform_set_drvdata(pdev, asrc_priv);
1215
+	platform_set_drvdata(pdev, asrc);
9121216 	pm_runtime_enable(&pdev->dev);
913
-	spin_lock_init(&asrc_priv->lock);
1217
+	spin_lock_init(&asrc->lock);
1218
+	regcache_cache_only(asrc->regmap, true);
9141219 
9151220 	ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
9161221 					      &fsl_asrc_dai, 1);
....@@ -925,17 +1230,19 @@
9251230 #ifdef CONFIG_PM
9261231 static int fsl_asrc_runtime_resume(struct device *dev)
9271232 {
928
-	struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
1233
+	struct fsl_asrc *asrc = dev_get_drvdata(dev);
1234
+	struct fsl_asrc_priv *asrc_priv = asrc->private;
9291235 	int i, ret;
1236
+	u32 asrctr;
9301237 
931
-	ret = clk_prepare_enable(asrc_priv->mem_clk);
1238
+	ret = clk_prepare_enable(asrc->mem_clk);
9321239 	if (ret)
9331240 		return ret;
934
-	ret = clk_prepare_enable(asrc_priv->ipg_clk);
1241
+	ret = clk_prepare_enable(asrc->ipg_clk);
9351242 	if (ret)
9361243 		goto disable_mem_clk;
937
-	if (!IS_ERR(asrc_priv->spba_clk)) {
938
-		ret = clk_prepare_enable(asrc_priv->spba_clk);
1244
+	if (!IS_ERR(asrc->spba_clk)) {
1245
+		ret = clk_prepare_enable(asrc->spba_clk);
9391246 		if (ret)
9401247 			goto disable_ipg_clk;
9411248 	}
....@@ -945,84 +1252,91 @@
9451252 			goto disable_asrck_clk;
9461253 	}
9471254 
1255
+	/* Stop all pairs provisionally */
1256
+	regmap_read(asrc->regmap, REG_ASRCTR, &asrctr);
1257
+	regmap_update_bits(asrc->regmap, REG_ASRCTR,
1258
+			   ASRCTR_ASRCEi_ALL_MASK, 0);
1259
+
1260
+	/* Restore all registers */
1261
+	regcache_cache_only(asrc->regmap, false);
1262
+	regcache_mark_dirty(asrc->regmap);
1263
+	regcache_sync(asrc->regmap);
1264
+
1265
+	regmap_update_bits(asrc->regmap, REG_ASRCFG,
1266
+			   ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
1267
+			   ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
1268
+
1269
+	/* Restart enabled pairs */
1270
+	regmap_update_bits(asrc->regmap, REG_ASRCTR,
1271
+			   ASRCTR_ASRCEi_ALL_MASK, asrctr);
1272
+
9481273 	return 0;
9491274 
9501275 disable_asrck_clk:
9511276 	for (i--; i >= 0; i--)
9521277 		clk_disable_unprepare(asrc_priv->asrck_clk[i]);
953
-	if (!IS_ERR(asrc_priv->spba_clk))
954
-		clk_disable_unprepare(asrc_priv->spba_clk);
1278
+	if (!IS_ERR(asrc->spba_clk))
1279
+		clk_disable_unprepare(asrc->spba_clk);
9551280 disable_ipg_clk:
956
-	clk_disable_unprepare(asrc_priv->ipg_clk);
1281
+	clk_disable_unprepare(asrc->ipg_clk);
9571282 disable_mem_clk:
958
-	clk_disable_unprepare(asrc_priv->mem_clk);
1283
+	clk_disable_unprepare(asrc->mem_clk);
9591284 	return ret;
9601285 }
9611286 
9621287 static int fsl_asrc_runtime_suspend(struct device *dev)
9631288 {
964
-	struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
1289
+	struct fsl_asrc *asrc = dev_get_drvdata(dev);
1290
+	struct fsl_asrc_priv *asrc_priv = asrc->private;
9651291 	int i;
1292
+
1293
+	regmap_read(asrc->regmap, REG_ASRCFG,
1294
+		    &asrc_priv->regcache_cfg);
1295
+
1296
+	regcache_cache_only(asrc->regmap, true);
9661297 
9671298 	for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
9681299 		clk_disable_unprepare(asrc_priv->asrck_clk[i]);
969
-	if (!IS_ERR(asrc_priv->spba_clk))
970
-		clk_disable_unprepare(asrc_priv->spba_clk);
971
-	clk_disable_unprepare(asrc_priv->ipg_clk);
972
-	clk_disable_unprepare(asrc_priv->mem_clk);
1300
+	if (!IS_ERR(asrc->spba_clk))
1301
+		clk_disable_unprepare(asrc->spba_clk);
1302
+	clk_disable_unprepare(asrc->ipg_clk);
1303
+	clk_disable_unprepare(asrc->mem_clk);
9731304 
9741305 	return 0;
9751306 }
9761307 #endif /* CONFIG_PM */
9771308 
978
-#ifdef CONFIG_PM_SLEEP
979
-static int fsl_asrc_suspend(struct device *dev)
980
-{
981
-	struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
982
-
983
-	regmap_read(asrc_priv->regmap, REG_ASRCFG,
984
-		    &asrc_priv->regcache_cfg);
985
-
986
-	regcache_cache_only(asrc_priv->regmap, true);
987
-	regcache_mark_dirty(asrc_priv->regmap);
988
-
989
-	return 0;
990
-}
991
-
992
-static int fsl_asrc_resume(struct device *dev)
993
-{
994
-	struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
995
-	u32 asrctr;
996
-
997
-	/* Stop all pairs provisionally */
998
-	regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr);
999
-	regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
1000
-			   ASRCTR_ASRCEi_ALL_MASK, 0);
1001
-
1002
-	/* Restore all registers */
1003
-	regcache_cache_only(asrc_priv->regmap, false);
1004
-	regcache_sync(asrc_priv->regmap);
1005
-
1006
-	regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
1007
-			   ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
1008
-			   ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
1009
-
1010
-	/* Restart enabled pairs */
1011
-	regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
1012
-			   ASRCTR_ASRCEi_ALL_MASK, asrctr);
1013
-
1014
-	return 0;
1015
-}
1016
-#endif /* CONFIG_PM_SLEEP */
1017
-
10181309 static const struct dev_pm_ops fsl_asrc_pm = {
10191310 	SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL)
1020
-	SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume)
1311
+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1312
+				pm_runtime_force_resume)
1313
+};
1314
+
1315
+static const struct fsl_asrc_soc_data fsl_asrc_imx35_data = {
1316
+	.use_edma = false,
1317
+	.channel_bits = 3,
1318
+};
1319
+
1320
+static const struct fsl_asrc_soc_data fsl_asrc_imx53_data = {
1321
+	.use_edma = false,
1322
+	.channel_bits = 4,
1323
+};
1324
+
1325
+static const struct fsl_asrc_soc_data fsl_asrc_imx8qm_data = {
1326
+	.use_edma = true,
1327
+	.channel_bits = 4,
1328
+};
1329
+
1330
+static const struct fsl_asrc_soc_data fsl_asrc_imx8qxp_data = {
1331
+	.use_edma = true,
1332
+	.channel_bits = 4,
10211333 };
10221334 
10231335 static const struct of_device_id fsl_asrc_ids[] = {
1024
-	{ .compatible = "fsl,imx35-asrc", },
1025
-	{ .compatible = "fsl,imx53-asrc", },
1336
+	{ .compatible = "fsl,imx35-asrc", .data = &fsl_asrc_imx35_data },
1337
+	{ .compatible = "fsl,imx53-asrc", .data = &fsl_asrc_imx53_data },
1338
+	{ .compatible = "fsl,imx8qm-asrc", .data = &fsl_asrc_imx8qm_data },
1339
+	{ .compatible = "fsl,imx8qxp-asrc", .data = &fsl_asrc_imx8qxp_data },
10261340 	{}
10271341 };
10281342 MODULE_DEVICE_TABLE(of, fsl_asrc_ids);