| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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| 1 | 2 | /* |
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| 2 | 3 | * wm9713.c -- ALSA Soc WM9713 codec support |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright 2006-10 Wolfson Microelectronics PLC. |
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| 5 | 6 | * Author: Liam Girdwood <lrg@slimlogic.co.uk> |
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| 6 | | - * |
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| 7 | | - * This program is free software; you can redistribute it and/or modify it |
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| 8 | | - * under the terms of the GNU General Public License as published by the |
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| 9 | | - * Free Software Foundation; either version 2 of the License, or (at your |
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| 10 | | - * option) any later version. |
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| 11 | 7 | * |
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| 12 | 8 | * Features:- |
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| 13 | 9 | * |
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| .. | .. |
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| 759 | 755 | u64 Kpart; |
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| 760 | 756 | unsigned int K, Ndiv, Nmod, target; |
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| 761 | 757 | |
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| 762 | | - /* The the PLL output is always 98.304MHz. */ |
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| 758 | + /* The PLL output is always 98.304MHz. */ |
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| 763 | 759 | target = 98304000; |
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| 764 | 760 | |
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| 765 | 761 | /* If the input frequency is over 14.4MHz then scale it down. */ |
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| .. | .. |
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| 811 | 807 | pll_div->k = K; |
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| 812 | 808 | } |
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| 813 | 809 | |
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| 814 | | -/** |
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| 810 | +/* |
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| 815 | 811 | * Please note that changing the PLL input frequency may require |
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| 816 | 812 | * resynchronisation with the AC97 controller. |
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| 817 | 813 | */ |
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| .. | .. |
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| 943 | 939 | unsigned int fmt) |
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| 944 | 940 | { |
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| 945 | 941 | struct snd_soc_component *component = codec_dai->component; |
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| 946 | | - u16 gpio = snd_soc_component_read32(component, AC97_GPIO_CFG) & 0xffc5; |
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| 942 | + u16 gpio = snd_soc_component_read(component, AC97_GPIO_CFG) & 0xffc5; |
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| 947 | 943 | u16 reg = 0x8000; |
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| 948 | 944 | |
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| 949 | 945 | /* clock masters */ |
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