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hc
2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/sound/soc/codecs/max98095.c
....@@ -1,11 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * max98095.c -- MAX98095 ALSA SoC Audio driver
34  *
45  * Copyright 2011 Maxim Integrated Products
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
96  */
107 
118 #include <linux/module.h>
....@@ -974,7 +971,7 @@
974971 	cdata->rate = rate;
975972 
976973 	/* Configure NI when operating as master */
977
-	if (snd_soc_component_read32(component, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
974
+	if (snd_soc_component_read(component, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) {
978975 		if (max98095->sysclk == 0) {
979976 			dev_err(component->dev, "Invalid system clock frequency\n");
980977 			return -EINVAL;
....@@ -1035,7 +1032,7 @@
10351032 	cdata->rate = rate;
10361033 
10371034 	/* Configure NI when operating as master */
1038
-	if (snd_soc_component_read32(component, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
1035
+	if (snd_soc_component_read(component, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) {
10391036 		if (max98095->sysclk == 0) {
10401037 			dev_err(component->dev, "Invalid system clock frequency\n");
10411038 			return -EINVAL;
....@@ -1096,7 +1093,7 @@
10961093 	cdata->rate = rate;
10971094 
10981095 	/* Configure NI when operating as master */
1099
-	if (snd_soc_component_read32(component, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
1096
+	if (snd_soc_component_read(component, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) {
11001097 		if (max98095->sysclk == 0) {
11011098 			dev_err(component->dev, "Invalid system clock frequency\n");
11021099 			return -EINVAL;
....@@ -1537,7 +1534,7 @@
15371534 	regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN;
15381535 
15391536 	/* Disable filter while configuring, and save current on/off state */
1540
-	regsave = snd_soc_component_read32(component, M98095_088_CFG_LEVEL);
1537
+	regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL);
15411538 	snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
15421539 
15431540 	mutex_lock(&max98095->lock);
....@@ -1688,7 +1685,7 @@
16881685 	regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN;
16891686 
16901687 	/* Disable filter while configuring, and save current on/off state */
1691
-	regsave = snd_soc_component_read32(component, M98095_088_CFG_LEVEL);
1688
+	regsave = snd_soc_component_read(component, M98095_088_CFG_LEVEL);
16921689 	snd_soc_component_update_bits(component, M98095_088_CFG_LEVEL, regmask, 0);
16931690 
16941691 	mutex_lock(&max98095->lock);
....@@ -1819,7 +1816,7 @@
18191816 	int mic_report = 0;
18201817 
18211818 	/* Read the Jack Status Register */
1822
-	value = snd_soc_component_read32(component, M98095_007_JACK_AUTO_STS);
1819
+	value = snd_soc_component_read(component, M98095_007_JACK_AUTO_STS);
18231820 
18241821 	/* If ddone is not set, then detection isn't finished yet */
18251822 	if ((value & M98095_DDONE) == 0)
....@@ -1975,7 +1972,7 @@
19751972 	/* Reset to hardware default for registers, as there is not
19761973 	 * a soft reset hardware control register */
19771974 	for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
1978
-		ret = snd_soc_component_write(component, i, snd_soc_component_read32(component, i));
1975
+		ret = snd_soc_component_write(component, i, snd_soc_component_read(component, i));
19791976 		if (ret < 0) {
19801977 			dev_err(component->dev, "Failed to reset: %d\n", ret);
19811978 			return ret;
....@@ -2041,7 +2038,7 @@
20412038 		}
20422039 	}
20432040 
2044
-	ret = snd_soc_component_read32(component, M98095_0FF_REV_ID);
2041
+	ret = snd_soc_component_read(component, M98095_0FF_REV_ID);
20452042 	if (ret < 0) {
20462043 		dev_err(component->dev, "Failure reading hardware revision: %d\n",
20472044 			ret);