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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/sound/soc/codecs/max98088.c
....@@ -1,11 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * max98088.c -- MAX98088 ALSA SoC Audio driver
34  *
45  * Copyright 2010 Maxim Integrated Products
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
96  */
107 
118 #include <linux/module.h>
....@@ -16,6 +13,7 @@
1613 #include <linux/pm.h>
1714 #include <linux/i2c.h>
1815 #include <linux/regmap.h>
16
+#include <linux/clk.h>
1917 #include <sound/core.h>
2018 #include <sound/pcm.h>
2119 #include <sound/pcm_params.h>
....@@ -42,6 +40,8 @@
4240 	struct regmap *regmap;
4341 	enum max98088_type devtype;
4442 	struct max98088_pdata *pdata;
43
+	struct clk *mclk;
44
+	unsigned char mclk_prescaler;
4545 	unsigned int sysclk;
4646 	struct max98088_cdata dai[2];
4747 	int eq_textcnt;
....@@ -997,15 +997,18 @@
997997        cdata->rate = rate;
998998 
999999        /* Configure NI when operating as master */
1000
-       if (snd_soc_component_read32(component, M98088_REG_14_DAI1_FORMAT)
1000
+       if (snd_soc_component_read(component, M98088_REG_14_DAI1_FORMAT)
10011001                & M98088_DAI_MAS) {
1002
+               unsigned long pclk;
1003
+
10021004                if (max98088->sysclk == 0) {
10031005                        dev_err(component->dev, "Invalid system clock frequency\n");
10041006                        return -EINVAL;
10051007                }
10061008                ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
10071009                                * (unsigned long long int)rate;
1008
-               do_div(ni, (unsigned long long int)max98088->sysclk);
1010
+               pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler);
1011
+               ni = DIV_ROUND_CLOSEST_ULL(ni, pclk);
10091012                snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI,
10101013                        (ni >> 8) & 0x7F);
10111014                snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO,
....@@ -1064,15 +1067,18 @@
10641067        cdata->rate = rate;
10651068 
10661069        /* Configure NI when operating as master */
1067
-       if (snd_soc_component_read32(component, M98088_REG_1C_DAI2_FORMAT)
1070
+       if (snd_soc_component_read(component, M98088_REG_1C_DAI2_FORMAT)
10681071                & M98088_DAI_MAS) {
1072
+               unsigned long pclk;
1073
+
10691074                if (max98088->sysclk == 0) {
10701075                        dev_err(component->dev, "Invalid system clock frequency\n");
10711076                        return -EINVAL;
10721077                }
10731078                ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
10741079                                * (unsigned long long int)rate;
1075
-               do_div(ni, (unsigned long long int)max98088->sysclk);
1080
+               pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler);
1081
+               ni = DIV_ROUND_CLOSEST_ULL(ni, pclk);
10761082                snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI,
10771083                        (ni >> 8) & 0x7F);
10781084                snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO,
....@@ -1103,20 +1109,27 @@
11031109        if (freq == max98088->sysclk)
11041110                return 0;
11051111 
1112
+	if (!IS_ERR(max98088->mclk)) {
1113
+		freq = clk_round_rate(max98088->mclk, freq);
1114
+		clk_set_rate(max98088->mclk, freq);
1115
+	}
1116
+
11061117        /* Setup clocks for slave mode, and using the PLL
11071118         * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
11081119         *         0x02 (when master clk is 20MHz to 30MHz)..
11091120         */
11101121        if ((freq >= 10000000) && (freq < 20000000)) {
11111122                snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x10);
1123
+               max98088->mclk_prescaler = 1;
11121124        } else if ((freq >= 20000000) && (freq < 30000000)) {
11131125                snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x20);
1126
+               max98088->mclk_prescaler = 2;
11141127        } else {
11151128                dev_err(component->dev, "Invalid master clock frequency\n");
11161129                return -EINVAL;
11171130        }
11181131 
1119
-       if (snd_soc_component_read32(component, M98088_REG_51_PWR_SYS)  & M98088_SHDNRUN) {
1132
+       if (snd_soc_component_read(component, M98088_REG_51_PWR_SYS)  & M98088_SHDNRUN) {
11201133                snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS,
11211134                        M98088_SHDNRUN, 0);
11221135                snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS,
....@@ -1270,7 +1283,8 @@
12701283        return 0;
12711284 }
12721285 
1273
-static int max98088_dai1_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1286
+static int max98088_dai1_mute(struct snd_soc_dai *codec_dai, int mute,
1287
+			      int direction)
12741288 {
12751289        struct snd_soc_component *component = codec_dai->component;
12761290        int reg;
....@@ -1285,7 +1299,8 @@
12851299        return 0;
12861300 }
12871301 
1288
-static int max98088_dai2_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1302
+static int max98088_dai2_mute(struct snd_soc_dai *codec_dai, int mute,
1303
+			      int direction)
12891304 {
12901305        struct snd_soc_component *component = codec_dai->component;
12911306        int reg;
....@@ -1310,6 +1325,20 @@
13101325 		break;
13111326 
13121327 	case SND_SOC_BIAS_PREPARE:
1328
+		/*
1329
+		 * SND_SOC_BIAS_PREPARE is called while preparing for a
1330
+		 * transition to ON or away from ON. If current bias_level
1331
+		 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1332
+		 * away from ON. Disable the clock in that case, otherwise
1333
+		 * enable it.
1334
+		 */
1335
+		if (!IS_ERR(max98088->mclk)) {
1336
+			if (snd_soc_component_get_bias_level(component) ==
1337
+			    SND_SOC_BIAS_ON)
1338
+				clk_disable_unprepare(max98088->mclk);
1339
+			else
1340
+				clk_prepare_enable(max98088->mclk);
1341
+		}
13131342 		break;
13141343 
13151344 	case SND_SOC_BIAS_STANDBY:
....@@ -1336,14 +1365,16 @@
13361365        .set_sysclk = max98088_dai_set_sysclk,
13371366        .set_fmt = max98088_dai1_set_fmt,
13381367        .hw_params = max98088_dai1_hw_params,
1339
-       .digital_mute = max98088_dai1_digital_mute,
1368
+       .mute_stream = max98088_dai1_mute,
1369
+       .no_capture_mute = 1,
13401370 };
13411371 
13421372 static const struct snd_soc_dai_ops max98088_dai2_ops = {
13431373        .set_sysclk = max98088_dai_set_sysclk,
13441374        .set_fmt = max98088_dai2_set_fmt,
13451375        .hw_params = max98088_dai2_hw_params,
1346
-       .digital_mute = max98088_dai2_digital_mute,
1376
+       .mute_stream = max98088_dai2_mute,
1377
+       .no_capture_mute = 1,
13471378 };
13481379 
13491380 static struct snd_soc_dai_driver max98088_dai[] = {
....@@ -1422,7 +1453,7 @@
14221453                pdata->eq_cfg[best].rate, fs);
14231454 
14241455        /* Disable EQ while configuring, and save current on/off state */
1425
-       save = snd_soc_component_read32(component, M98088_REG_49_CFG_LEVEL);
1456
+       save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL);
14261457        snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0);
14271458 
14281459        coef_set = &pdata->eq_cfg[sel];
....@@ -1469,7 +1500,7 @@
14691500                pdata->eq_cfg[best].rate, fs);
14701501 
14711502        /* Disable EQ while configuring, and save current on/off state */
1472
-       save = snd_soc_component_read32(component, M98088_REG_49_CFG_LEVEL);
1503
+       save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL);
14731504        snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0);
14741505 
14751506        coef_set = &pdata->eq_cfg[sel];
....@@ -1655,7 +1686,7 @@
16551686        max98088->mic1pre = 0;
16561687        max98088->mic2pre = 0;
16571688 
1658
-       ret = snd_soc_component_read32(component, M98088_REG_FF_REV_ID);
1689
+       ret = snd_soc_component_read(component, M98088_REG_FF_REV_ID);
16591690        if (ret < 0) {
16601691                dev_err(component->dev, "Failed to read device revision: %d\n",
16611692                        ret);
....@@ -1725,6 +1756,11 @@
17251756        if (IS_ERR(max98088->regmap))
17261757 	       return PTR_ERR(max98088->regmap);
17271758 
1759
+	max98088->mclk = devm_clk_get(&i2c->dev, "mclk");
1760
+	if (IS_ERR(max98088->mclk))
1761
+		if (PTR_ERR(max98088->mclk) == -EPROBE_DEFER)
1762
+			return PTR_ERR(max98088->mclk);
1763
+
17281764        max98088->devtype = id->driver_data;
17291765 
17301766        i2c_set_clientdata(i2c, max98088);
....@@ -1742,9 +1778,19 @@
17421778 };
17431779 MODULE_DEVICE_TABLE(i2c, max98088_i2c_id);
17441780 
1781
+#if defined(CONFIG_OF)
1782
+static const struct of_device_id max98088_of_match[] = {
1783
+	{ .compatible = "maxim,max98088" },
1784
+	{ .compatible = "maxim,max98089" },
1785
+	{ }
1786
+};
1787
+MODULE_DEVICE_TABLE(of, max98088_of_match);
1788
+#endif
1789
+
17451790 static struct i2c_driver max98088_i2c_driver = {
17461791 	.driver = {
17471792 		.name = "max98088",
1793
+		.of_match_table = of_match_ptr(max98088_of_match),
17481794 	},
17491795 	.probe  = max98088_i2c_probe,
17501796 	.id_table = max98088_i2c_id,