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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/sound/soc/atmel/atmel_ssc_dai.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * atmel_ssc_dai.c  --  ALSA SoC ATMEL SSC Audio Layer Platform driver
34  *
....@@ -11,20 +12,6 @@
1112  * Frank Mandarino <fmandarino@endrelia.com>
1213  * Based on pxa2xx Platform drivers by
1314  * Liam Girdwood <lrg@slimlogic.co.uk>
14
- *
15
- * This program is free software; you can redistribute it and/or modify
16
- * it under the terms of the GNU General Public License as published by
17
- * the Free Software Foundation; either version 2 of the License, or
18
- * (at your option) any later version.
19
- *
20
- * This program is distributed in the hope that it will be useful,
21
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
22
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23
- * GNU General Public License for more details.
24
- *
25
- * You should have received a copy of the GNU General Public License
26
- * along with this program; if not, write to the Free Software
27
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2815  */
2916 
3017 #include <linux/init.h>
....@@ -129,19 +116,16 @@
129116 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
130117 	{
131118 	.name		= "ssc0",
132
-	.lock		= __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
133119 	.dir_mask	= SSC_DIR_MASK_UNUSED,
134120 	.initialized	= 0,
135121 	},
136122 	{
137123 	.name		= "ssc1",
138
-	.lock		= __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
139124 	.dir_mask	= SSC_DIR_MASK_UNUSED,
140125 	.initialized	= 0,
141126 	},
142127 	{
143128 	.name		= "ssc2",
144
-	.lock		= __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
145129 	.dir_mask	= SSC_DIR_MASK_UNUSED,
146130 	.initialized	= 0,
147131 	},
....@@ -296,7 +280,10 @@
296280 
297281 	/* Enable PMC peripheral clock for this SSC */
298282 	pr_debug("atmel_ssc_dai: Starting clock\n");
299
-	clk_enable(ssc_p->ssc->clk);
283
+	ret = clk_enable(ssc_p->ssc->clk);
284
+	if (ret)
285
+		return ret;
286
+
300287 	ssc_p->mck_rate = clk_get_rate(ssc_p->ssc->clk);
301288 
302289 	/* Reset the SSC unless initialized to keep it in a clean state */
....@@ -330,13 +317,10 @@
330317 
331318 	snd_soc_dai_set_dma_data(dai, substream, dma_params);
332319 
333
-	spin_lock_irq(&ssc_p->lock);
334
-	if (ssc_p->dir_mask & dir_mask) {
335
-		spin_unlock_irq(&ssc_p->lock);
320
+	if (ssc_p->dir_mask & dir_mask)
336321 		return -EBUSY;
337
-	}
322
+
338323 	ssc_p->dir_mask |= dir_mask;
339
-	spin_unlock_irq(&ssc_p->lock);
340324 
341325 	return 0;
342326 }
....@@ -368,7 +352,6 @@
368352 
369353 	dir_mask = 1 << dir;
370354 
371
-	spin_lock_irq(&ssc_p->lock);
372355 	ssc_p->dir_mask &= ~dir_mask;
373356 	if (!ssc_p->dir_mask) {
374357 		if (ssc_p->initialized) {
....@@ -382,7 +365,6 @@
382365 		ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
383366 		ssc_p->forced_divider = 0;
384367 	}
385
-	spin_unlock_irq(&ssc_p->lock);
386368 
387369 	/* Shutdown the SSC clock. */
388370 	pr_debug("atmel_ssc_dai: Stopping clock\n");
....@@ -484,7 +466,7 @@
484466 	int dir, channels, bits;
485467 	u32 tfmr, rfmr, tcmr, rcmr;
486468 	int ret;
487
-	int fslen, fslen_ext;
469
+	int fslen, fslen_ext, fs_osync, fs_edge;
488470 	u32 cmr_div;
489471 	u32 tcmr_period;
490472 	u32 rcmr_period;
....@@ -571,226 +553,45 @@
571553 	/*
572554 	 * Compute SSC register settings.
573555 	 */
574
-	switch (ssc_p->daifmt
575
-		& (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
576556 
577
-	case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
557
+	fslen_ext = (bits - 1) / 16;
558
+	fslen = (bits - 1) % 16;
559
+
560
+	switch (ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) {
561
+
562
+	case SND_SOC_DAIFMT_LEFT_J:
563
+		fs_osync = SSC_FSOS_POSITIVE;
564
+		fs_edge = SSC_START_RISING_RF;
565
+
566
+		rcmr =	  SSC_BF(RCMR_STTDLY, 0);
567
+		tcmr =	  SSC_BF(TCMR_STTDLY, 0);
568
+
569
+		break;
570
+
571
+	case SND_SOC_DAIFMT_I2S:
572
+		fs_osync = SSC_FSOS_NEGATIVE;
573
+		fs_edge = SSC_START_FALLING_RF;
574
+
575
+		rcmr =	  SSC_BF(RCMR_STTDLY, 1);
576
+		tcmr =	  SSC_BF(TCMR_STTDLY, 1);
577
+
578
+		break;
579
+
580
+	case SND_SOC_DAIFMT_DSP_A:
578581 		/*
579
-		 * I2S format, SSC provides BCLK and LRC clocks.
580
-		 *
581
-		 * The SSC transmit and receive clocks are generated
582
-		 * from the MCK divider, and the BCLK signal
583
-		 * is output on the SSC TK line.
584
-		 */
585
-
586
-		if (bits > 16 && !ssc->pdata->has_fslen_ext) {
587
-			dev_err(dai->dev,
588
-				"sample size %d is too large for SSC device\n",
589
-				bits);
590
-			return -EINVAL;
591
-		}
592
-
593
-		fslen_ext = (bits - 1) / 16;
594
-		fslen = (bits - 1) % 16;
595
-
596
-		rcmr =	  SSC_BF(RCMR_PERIOD, rcmr_period)
597
-			| SSC_BF(RCMR_STTDLY, START_DELAY)
598
-			| SSC_BF(RCMR_START, SSC_START_FALLING_RF)
599
-			| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
600
-			| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
601
-			| SSC_BF(RCMR_CKS, SSC_CKS_DIV);
602
-
603
-		rfmr =    SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
604
-			| SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
605
-			| SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
606
-			| SSC_BF(RFMR_FSLEN, fslen)
607
-			| SSC_BF(RFMR_DATNB, (channels - 1))
608
-			| SSC_BIT(RFMR_MSBF)
609
-			| SSC_BF(RFMR_LOOP, 0)
610
-			| SSC_BF(RFMR_DATLEN, (bits - 1));
611
-
612
-		tcmr =	  SSC_BF(TCMR_PERIOD, tcmr_period)
613
-			| SSC_BF(TCMR_STTDLY, START_DELAY)
614
-			| SSC_BF(TCMR_START, SSC_START_FALLING_RF)
615
-			| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
616
-			| SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
617
-			| SSC_BF(TCMR_CKS, SSC_CKS_DIV);
618
-
619
-		tfmr =    SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
620
-			| SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
621
-			| SSC_BF(TFMR_FSDEN, 0)
622
-			| SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
623
-			| SSC_BF(TFMR_FSLEN, fslen)
624
-			| SSC_BF(TFMR_DATNB, (channels - 1))
625
-			| SSC_BIT(TFMR_MSBF)
626
-			| SSC_BF(TFMR_DATDEF, 0)
627
-			| SSC_BF(TFMR_DATLEN, (bits - 1));
628
-		break;
629
-
630
-	case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
631
-		/* I2S format, CODEC supplies BCLK and LRC clocks. */
632
-		rcmr =	  SSC_BF(RCMR_PERIOD, 0)
633
-			| SSC_BF(RCMR_STTDLY, START_DELAY)
634
-			| SSC_BF(RCMR_START, SSC_START_FALLING_RF)
635
-			| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
636
-			| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
637
-			| SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
638
-					   SSC_CKS_PIN : SSC_CKS_CLOCK);
639
-
640
-		rfmr =	  SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
641
-			| SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
642
-			| SSC_BF(RFMR_FSLEN, 0)
643
-			| SSC_BF(RFMR_DATNB, (channels - 1))
644
-			| SSC_BIT(RFMR_MSBF)
645
-			| SSC_BF(RFMR_LOOP, 0)
646
-			| SSC_BF(RFMR_DATLEN, (bits - 1));
647
-
648
-		tcmr =	  SSC_BF(TCMR_PERIOD, 0)
649
-			| SSC_BF(TCMR_STTDLY, START_DELAY)
650
-			| SSC_BF(TCMR_START, SSC_START_FALLING_RF)
651
-			| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
652
-			| SSC_BF(TCMR_CKO, SSC_CKO_NONE)
653
-			| SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
654
-					   SSC_CKS_CLOCK : SSC_CKS_PIN);
655
-
656
-		tfmr =	  SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
657
-			| SSC_BF(TFMR_FSDEN, 0)
658
-			| SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
659
-			| SSC_BF(TFMR_FSLEN, 0)
660
-			| SSC_BF(TFMR_DATNB, (channels - 1))
661
-			| SSC_BIT(TFMR_MSBF)
662
-			| SSC_BF(TFMR_DATDEF, 0)
663
-			| SSC_BF(TFMR_DATLEN, (bits - 1));
664
-		break;
665
-
666
-	case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFS:
667
-		/* I2S format, CODEC supplies BCLK, SSC supplies LRCLK. */
668
-		if (bits > 16 && !ssc->pdata->has_fslen_ext) {
669
-			dev_err(dai->dev,
670
-				"sample size %d is too large for SSC device\n",
671
-				bits);
672
-			return -EINVAL;
673
-		}
674
-
675
-		fslen_ext = (bits - 1) / 16;
676
-		fslen = (bits - 1) % 16;
677
-
678
-		rcmr =	  SSC_BF(RCMR_PERIOD, rcmr_period)
679
-			| SSC_BF(RCMR_STTDLY, START_DELAY)
680
-			| SSC_BF(RCMR_START, SSC_START_FALLING_RF)
681
-			| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
682
-			| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
683
-			| SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
684
-					   SSC_CKS_PIN : SSC_CKS_CLOCK);
685
-
686
-		rfmr =    SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
687
-			| SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
688
-			| SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
689
-			| SSC_BF(RFMR_FSLEN, fslen)
690
-			| SSC_BF(RFMR_DATNB, (channels - 1))
691
-			| SSC_BIT(RFMR_MSBF)
692
-			| SSC_BF(RFMR_LOOP, 0)
693
-			| SSC_BF(RFMR_DATLEN, (bits - 1));
694
-
695
-		tcmr =	  SSC_BF(TCMR_PERIOD, tcmr_period)
696
-			| SSC_BF(TCMR_STTDLY, START_DELAY)
697
-			| SSC_BF(TCMR_START, SSC_START_FALLING_RF)
698
-			| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
699
-			| SSC_BF(TCMR_CKO, SSC_CKO_NONE)
700
-			| SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
701
-					   SSC_CKS_CLOCK : SSC_CKS_PIN);
702
-
703
-		tfmr =    SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
704
-			| SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_NEGATIVE)
705
-			| SSC_BF(TFMR_FSDEN, 0)
706
-			| SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
707
-			| SSC_BF(TFMR_FSLEN, fslen)
708
-			| SSC_BF(TFMR_DATNB, (channels - 1))
709
-			| SSC_BIT(TFMR_MSBF)
710
-			| SSC_BF(TFMR_DATDEF, 0)
711
-			| SSC_BF(TFMR_DATLEN, (bits - 1));
712
-		break;
713
-
714
-	case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
715
-		/*
716
-		 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
717
-		 *
718
-		 * The SSC transmit and receive clocks are generated from the
719
-		 * MCK divider, and the BCLK signal is output
720
-		 * on the SSC TK line.
721
-		 */
722
-		rcmr =	  SSC_BF(RCMR_PERIOD, rcmr_period)
723
-			| SSC_BF(RCMR_STTDLY, 1)
724
-			| SSC_BF(RCMR_START, SSC_START_RISING_RF)
725
-			| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
726
-			| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
727
-			| SSC_BF(RCMR_CKS, SSC_CKS_DIV);
728
-
729
-		rfmr =	  SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
730
-			| SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
731
-			| SSC_BF(RFMR_FSLEN, 0)
732
-			| SSC_BF(RFMR_DATNB, (channels - 1))
733
-			| SSC_BIT(RFMR_MSBF)
734
-			| SSC_BF(RFMR_LOOP, 0)
735
-			| SSC_BF(RFMR_DATLEN, (bits - 1));
736
-
737
-		tcmr =	  SSC_BF(TCMR_PERIOD, tcmr_period)
738
-			| SSC_BF(TCMR_STTDLY, 1)
739
-			| SSC_BF(TCMR_START, SSC_START_RISING_RF)
740
-			| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
741
-			| SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
742
-			| SSC_BF(TCMR_CKS, SSC_CKS_DIV);
743
-
744
-		tfmr =	  SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
745
-			| SSC_BF(TFMR_FSDEN, 0)
746
-			| SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
747
-			| SSC_BF(TFMR_FSLEN, 0)
748
-			| SSC_BF(TFMR_DATNB, (channels - 1))
749
-			| SSC_BIT(TFMR_MSBF)
750
-			| SSC_BF(TFMR_DATDEF, 0)
751
-			| SSC_BF(TFMR_DATLEN, (bits - 1));
752
-		break;
753
-
754
-	case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
755
-		/*
756
-		 * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks.
582
+		 * DSP/PCM Mode A format
757583 		 *
758584 		 * Data is transferred on first BCLK after LRC pulse rising
759585 		 * edge.If stereo, the right channel data is contiguous with
760586 		 * the left channel data.
761587 		 */
762
-		rcmr =	  SSC_BF(RCMR_PERIOD, 0)
763
-			| SSC_BF(RCMR_STTDLY, START_DELAY)
764
-			| SSC_BF(RCMR_START, SSC_START_RISING_RF)
765
-			| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
766
-			| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
767
-			| SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
768
-					   SSC_CKS_PIN : SSC_CKS_CLOCK);
588
+		fs_osync = SSC_FSOS_POSITIVE;
589
+		fs_edge = SSC_START_RISING_RF;
590
+		fslen = fslen_ext = 0;
769591 
770
-		rfmr =	  SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
771
-			| SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
772
-			| SSC_BF(RFMR_FSLEN, 0)
773
-			| SSC_BF(RFMR_DATNB, (channels - 1))
774
-			| SSC_BIT(RFMR_MSBF)
775
-			| SSC_BF(RFMR_LOOP, 0)
776
-			| SSC_BF(RFMR_DATLEN, (bits - 1));
592
+		rcmr =	  SSC_BF(RCMR_STTDLY, 1);
593
+		tcmr =	  SSC_BF(TCMR_STTDLY, 1);
777594 
778
-		tcmr =	  SSC_BF(TCMR_PERIOD, 0)
779
-			| SSC_BF(TCMR_STTDLY, START_DELAY)
780
-			| SSC_BF(TCMR_START, SSC_START_RISING_RF)
781
-			| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
782
-			| SSC_BF(TCMR_CKO, SSC_CKO_NONE)
783
-			| SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
784
-					   SSC_CKS_CLOCK : SSC_CKS_PIN);
785
-
786
-		tfmr =	  SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
787
-			| SSC_BF(TFMR_FSDEN, 0)
788
-			| SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
789
-			| SSC_BF(TFMR_FSLEN, 0)
790
-			| SSC_BF(TFMR_DATNB, (channels - 1))
791
-			| SSC_BIT(TFMR_MSBF)
792
-			| SSC_BF(TFMR_DATDEF, 0)
793
-			| SSC_BF(TFMR_DATLEN, (bits - 1));
794595 		break;
795596 
796597 	default:
....@@ -798,6 +599,70 @@
798599 			ssc_p->daifmt);
799600 		return -EINVAL;
800601 	}
602
+
603
+	if (!atmel_ssc_cfs(ssc_p)) {
604
+		fslen = fslen_ext = 0;
605
+		rcmr_period = tcmr_period = 0;
606
+		fs_osync = SSC_FSOS_NONE;
607
+	}
608
+
609
+	rcmr |=	  SSC_BF(RCMR_START, fs_edge);
610
+	tcmr |=	  SSC_BF(TCMR_START, fs_edge);
611
+
612
+	if (atmel_ssc_cbs(ssc_p)) {
613
+		/*
614
+		 * SSC provides BCLK
615
+		 *
616
+		 * The SSC transmit and receive clocks are generated from the
617
+		 * MCK divider, and the BCLK signal is output
618
+		 * on the SSC TK line.
619
+		 */
620
+		rcmr |=	  SSC_BF(RCMR_CKS, SSC_CKS_DIV)
621
+			| SSC_BF(RCMR_CKO, SSC_CKO_NONE);
622
+
623
+		tcmr |=	  SSC_BF(TCMR_CKS, SSC_CKS_DIV)
624
+			| SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS);
625
+	} else {
626
+		rcmr |=	  SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
627
+					SSC_CKS_PIN : SSC_CKS_CLOCK)
628
+			| SSC_BF(RCMR_CKO, SSC_CKO_NONE);
629
+
630
+		tcmr |=	  SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
631
+					SSC_CKS_CLOCK : SSC_CKS_PIN)
632
+			| SSC_BF(TCMR_CKO, SSC_CKO_NONE);
633
+	}
634
+
635
+	rcmr |=	  SSC_BF(RCMR_PERIOD, rcmr_period)
636
+		| SSC_BF(RCMR_CKI, SSC_CKI_RISING);
637
+
638
+	tcmr |=   SSC_BF(TCMR_PERIOD, tcmr_period)
639
+		| SSC_BF(TCMR_CKI, SSC_CKI_FALLING);
640
+
641
+	rfmr =    SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
642
+		| SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
643
+		| SSC_BF(RFMR_FSOS, fs_osync)
644
+		| SSC_BF(RFMR_FSLEN, fslen)
645
+		| SSC_BF(RFMR_DATNB, (channels - 1))
646
+		| SSC_BIT(RFMR_MSBF)
647
+		| SSC_BF(RFMR_LOOP, 0)
648
+		| SSC_BF(RFMR_DATLEN, (bits - 1));
649
+
650
+	tfmr =    SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
651
+		| SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
652
+		| SSC_BF(TFMR_FSDEN, 0)
653
+		| SSC_BF(TFMR_FSOS, fs_osync)
654
+		| SSC_BF(TFMR_FSLEN, fslen)
655
+		| SSC_BF(TFMR_DATNB, (channels - 1))
656
+		| SSC_BIT(TFMR_MSBF)
657
+		| SSC_BF(TFMR_DATDEF, 0)
658
+		| SSC_BF(TFMR_DATLEN, (bits - 1));
659
+
660
+	if (fslen_ext && !ssc->pdata->has_fslen_ext) {
661
+		dev_err(dai->dev, "sample size %d is too large for SSC device\n",
662
+			bits);
663
+		return -EINVAL;
664
+	}
665
+
801666 	pr_debug("atmel_ssc_hw_params: "
802667 			"RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
803668 			rcmr, rfmr, tcmr, tfmr);
....@@ -898,12 +763,12 @@
898763 }
899764 
900765 #ifdef CONFIG_PM
901
-static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
766
+static int atmel_ssc_suspend(struct snd_soc_component *component)
902767 {
903768 	struct atmel_ssc_info *ssc_p;
904
-	struct platform_device *pdev = to_platform_device(cpu_dai->dev);
769
+	struct platform_device *pdev = to_platform_device(component->dev);
905770 
906
-	if (!cpu_dai->active)
771
+	if (!snd_soc_component_active(component))
907772 		return 0;
908773 
909774 	ssc_p = &ssc_info[pdev->id];
....@@ -925,15 +790,13 @@
925790 	return 0;
926791 }
927792 
928
-
929
-
930
-static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
793
+static int atmel_ssc_resume(struct snd_soc_component *component)
931794 {
932795 	struct atmel_ssc_info *ssc_p;
933
-	struct platform_device *pdev = to_platform_device(cpu_dai->dev);
796
+	struct platform_device *pdev = to_platform_device(component->dev);
934797 	u32 cr;
935798 
936
-	if (!cpu_dai->active)
799
+	if (!snd_soc_component_active(component))
937800 		return 0;
938801 
939802 	ssc_p = &ssc_info[pdev->id];
....@@ -977,8 +840,6 @@
977840 };
978841 
979842 static struct snd_soc_dai_driver atmel_ssc_dai = {
980
-		.suspend = atmel_ssc_suspend,
981
-		.resume = atmel_ssc_resume,
982843 		.playback = {
983844 			.channels_min = 1,
984845 			.channels_max = 2,
....@@ -998,6 +859,8 @@
998859 
999860 static const struct snd_soc_component_driver atmel_ssc_component = {
1000861 	.name		= "atmel-ssc",
862
+	.suspend	= atmel_ssc_suspend,
863
+	.resume		= atmel_ssc_resume,
1001864 };
1002865 
1003866 static int asoc_ssc_init(struct device *dev)
....@@ -1005,11 +868,11 @@
1005868 	struct ssc_device *ssc = dev_get_drvdata(dev);
1006869 	int ret;
1007870 
1008
-	ret = snd_soc_register_component(dev, &atmel_ssc_component,
871
+	ret = devm_snd_soc_register_component(dev, &atmel_ssc_component,
1009872 					 &atmel_ssc_dai, 1);
1010873 	if (ret) {
1011874 		dev_err(dev, "Could not register DAI: %d\n", ret);
1012
-		goto err;
875
+		return ret;
1013876 	}
1014877 
1015878 	if (ssc->pdata->use_dma)
....@@ -1019,31 +882,15 @@
1019882 
1020883 	if (ret) {
1021884 		dev_err(dev, "Could not register PCM: %d\n", ret);
1022
-		goto err_unregister_dai;
885
+		return ret;
1023886 	}
1024887 
1025888 	return 0;
1026
-
1027
-err_unregister_dai:
1028
-	snd_soc_unregister_component(dev);
1029
-err:
1030
-	return ret;
1031
-}
1032
-
1033
-static void asoc_ssc_exit(struct device *dev)
1034
-{
1035
-	struct ssc_device *ssc = dev_get_drvdata(dev);
1036
-
1037
-	if (ssc->pdata->use_dma)
1038
-		atmel_pcm_dma_platform_unregister(dev);
1039
-	else
1040
-		atmel_pcm_pdc_platform_unregister(dev);
1041
-
1042
-	snd_soc_unregister_component(dev);
1043889 }
1044890 
1045891 /**
1046892  * atmel_ssc_set_audio - Allocate the specified SSC for audio use.
893
+ * @ssc_id: SSD ID in [0, NUM_SSC_DEVICES[
1047894  */
1048895 int atmel_ssc_set_audio(int ssc_id)
1049896 {
....@@ -1070,7 +917,6 @@
1070917 {
1071918 	struct ssc_device *ssc = ssc_info[ssc_id].ssc;
1072919 
1073
-	asoc_ssc_exit(&ssc->pdev->dev);
1074920 	ssc_free(ssc);
1075921 }
1076922 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio);