~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,3 +1,4 @@
	1	+// SPDX-License-Identifier: GPL-2.0-or-later
1	2	/*
2	3	* HD audio interface patch for Creative CA0132 chip
3	4	*
..	..	@@ -5,20 +6,6 @@
5	6	*
6	7	* Based on patch_ca0110.c
7	8	* Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8		- *
9		- * This driver is free software; you can redistribute it and/or modify
10		- * it under the terms of the GNU General Public License as published by
11		- * the Free Software Foundation; either version 2 of the License, or
12		- * (at your option) any later version.
13		- *
14		- * This driver is distributed in the hope that it will be useful,
15		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
16		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17		- * GNU General Public License for more details.
18		- *
19		- * You should have received a copy of the GNU General Public License
20		- * along with this program; if not, write to the Free Software
21		- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22	9	*/
23	10
24	11	#include <linux/init.h>
..	..	@@ -33,7 +20,7 @@
33	20	#include <linux/pci.h>
34	21	#include <asm/io.h>
35	22	#include <sound/core.h>
36		-#include "hda_codec.h"
	23	+#include <sound/hda_codec.h>
37	24	#include "hda_local.h"
38	25	#include "hda_auto_parser.h"
39	26	#include "hda_jack.h"
..	..	@@ -51,6 +38,8 @@
51	38	#define FLOAT_ONE 0x3f800000
52	39	#define FLOAT_TWO 0x40000000
53	40	#define FLOAT_THREE 0x40400000
	41	+#define FLOAT_FIVE 0x40a00000
	42	+#define FLOAT_SIX 0x40c00000
54	43	#define FLOAT_EIGHT 0x41000000
55	44	#define FLOAT_MINUS_5 0xc0a00000
56	45
..	..	@@ -82,22 +71,22 @@
82	71	#define SCP_GET 1
83	72
84	73	#define EFX_FILE "ctefx.bin"
85		-#define SBZ_EFX_FILE "ctefx-sbz.bin"
	74	+#define DESKTOP_EFX_FILE "ctefx-desktop.bin"
86	75	#define R3DI_EFX_FILE "ctefx-r3di.bin"
87	76
88	77	#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
89	78	MODULE_FIRMWARE(EFX_FILE);
90		-MODULE_FIRMWARE(SBZ_EFX_FILE);
	79	+MODULE_FIRMWARE(DESKTOP_EFX_FILE);
91	80	MODULE_FIRMWARE(R3DI_EFX_FILE);
92	81	#endif
93	82
94	83	static const char *const dirstr[2] = { "Playback", "Capture" };
95	84
96		-#define NUM_OF_OUTPUTS 3
	85	+#define NUM_OF_OUTPUTS 2
	86	+static const char *const out_type_str[2] = { "Speakers", "Headphone" };
97	87	enum {
98	88	SPEAKER_OUT,
99	89	HEADPHONE_OUT,
100		- SURROUND_OUT
101	90	};
102	91
103	92	enum {
..	..	@@ -153,7 +142,15 @@
153	142	XBASS_XOVER,
154	143	EQ_PRESET_ENUM,
155	144	SMART_VOLUME_ENUM,
156		- MIC_BOOST_ENUM
	145	+ MIC_BOOST_ENUM,
	146	+ AE5_HEADPHONE_GAIN_ENUM,
	147	+ AE5_SOUND_FILTER_ENUM,
	148	+ ZXR_HEADPHONE_GAIN,
	149	+ SPEAKER_CHANNEL_CFG_ENUM,
	150	+ SPEAKER_FULL_RANGE_FRONT,
	151	+ SPEAKER_FULL_RANGE_REAR,
	152	+ BASS_REDIRECTION,
	153	+ BASS_REDIRECTION_XOVER,
157	154	#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
158	155	};
159	156
..	..	@@ -599,46 +596,108 @@
599	596	}
600	597	};
601	598
602		-/* DSP command sequences for ca0132_alt_select_out */
603		-#define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
604		-struct ca0132_alt_out_set {
605		- char name; /preset name*/
606		- unsigned char commands;
607		- unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
608		- unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
609		- unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
	599	+/*
	600	+ * DSP reqs for handling full-range speakers/bass redirection. If a speaker is
	601	+ * set as not being full range, and bass redirection is enabled, all
	602	+ * frequencies below the crossover frequency are redirected to the LFE
	603	+ * channel. If the surround configuration has no LFE channel, this can't be
	604	+ * enabled. X-Bass must be disabled when using these.
	605	+ */
	606	+enum speaker_range_reqs {
	607	+ SPEAKER_BASS_REDIRECT = 0x15,
	608	+ SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
	609	+ /* Between 0x16-0x1a are the X-Bass reqs. */
	610	+ SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a,
	611	+ SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b,
	612	+ SPEAKER_FULL_RANGE_REAR_L_R = 0x1c,
	613	+ SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d,
	614	+ SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e,
610	615	};
611	616
612		-static const struct ca0132_alt_out_set alt_out_presets[] = {
613		- { .name = "Line Out",
614		- .commands = 7,
615		- .mids = { 0x96, 0x96, 0x96, 0x8F,
616		- 0x96, 0x96, 0x96 },
617		- .reqs = { 0x19, 0x17, 0x18, 0x01,
618		- 0x1F, 0x15, 0x3A },
619		- .vals = { 0x3F000000, 0x42A00000, 0x00000000,
620		- 0x00000000, 0x00000000, 0x00000000,
621		- 0x00000000 }
	617	+/*
	618	+ * Definitions for the DSP req's to handle speaker tuning. These all belong to
	619	+ * module ID 0x96, the output effects module.
	620	+ */
	621	+enum speaker_tuning_reqs {
	622	+ /*
	623	+ * Currently, this value is always set to 0.0f. However, on Windows,
	624	+ * when selecting certain headphone profiles on the new Sound Blaster
	625	+ * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
	626	+ * sent. This gets the speaker EQ address area, which is then used to
	627	+ * send over (presumably) an equalizer profile for the specific
	628	+ * headphone setup. It is sent using the same method the DSP
	629	+ * firmware is uploaded with, which I believe is why the 'ctspeq.bin'
	630	+ * file exists in linux firmware tree but goes unused. It would also
	631	+ * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused.
	632	+ * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is
	633	+ * set to 1.0f.
	634	+ */
	635	+ SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f,
	636	+ SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20,
	637	+ SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21,
	638	+ SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22,
	639	+ SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23,
	640	+ SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24,
	641	+ SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25,
	642	+ SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26,
	643	+ SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27,
	644	+ SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
	645	+ /*
	646	+ * Inversion is used when setting headphone virtualization to line
	647	+ * out. Not sure why this is, but it's the only place it's ever used.
	648	+ */
	649	+ SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29,
	650	+ SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a,
	651	+ SPEAKER_TUNING_CENTER_INVERT = 0x2b,
	652	+ SPEAKER_TUNING_LFE_INVERT = 0x2c,
	653	+ SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d,
	654	+ SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e,
	655	+ SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f,
	656	+ SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30,
	657	+ /* Delay is used when setting surround speaker distance in Windows. */
	658	+ SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31,
	659	+ SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32,
	660	+ SPEAKER_TUNING_CENTER_DELAY = 0x33,
	661	+ SPEAKER_TUNING_LFE_DELAY = 0x34,
	662	+ SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35,
	663	+ SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36,
	664	+ SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37,
	665	+ SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38,
	666	+ /* Of these two, only mute seems to ever be used. */
	667	+ SPEAKER_TUNING_MAIN_VOLUME = 0x39,
	668	+ SPEAKER_TUNING_MUTE = 0x3a,
	669	+};
	670	+
	671	+/* Surround output channel count configuration structures. */
	672	+#define SPEAKER_CHANNEL_CFG_COUNT 5
	673	+enum {
	674	+ SPEAKER_CHANNELS_2_0,
	675	+ SPEAKER_CHANNELS_2_1,
	676	+ SPEAKER_CHANNELS_4_0,
	677	+ SPEAKER_CHANNELS_4_1,
	678	+ SPEAKER_CHANNELS_5_1,
	679	+};
	680	+
	681	+struct ca0132_alt_speaker_channel_cfg {
	682	+ char *name;
	683	+ unsigned int val;
	684	+};
	685	+
	686	+static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = {
	687	+ { .name = "2.0",
	688	+ .val = FLOAT_ONE
622	689	},
623		- { .name = "Headphone",
624		- .commands = 7,
625		- .mids = { 0x96, 0x96, 0x96, 0x8F,
626		- 0x96, 0x96, 0x96 },
627		- .reqs = { 0x19, 0x17, 0x18, 0x01,
628		- 0x1F, 0x15, 0x3A },
629		- .vals = { 0x3F000000, 0x42A00000, 0x00000000,
630		- 0x00000000, 0x00000000, 0x00000000,
631		- 0x00000000 }
	690	+ { .name = "2.1",
	691	+ .val = FLOAT_TWO
632	692	},
633		- { .name = "Surround",
634		- .commands = 8,
635		- .mids = { 0x96, 0x8F, 0x96, 0x96,
636		- 0x96, 0x96, 0x96, 0x96 },
637		- .reqs = { 0x18, 0x01, 0x1F, 0x15,
638		- 0x3A, 0x1A, 0x1B, 0x1C },
639		- .vals = { 0x00000000, 0x00000000, 0x00000000,
640		- 0x00000000, 0x00000000, 0x00000000,
641		- 0x00000000, 0x00000000 }
	693	+ { .name = "4.0",
	694	+ .val = FLOAT_FIVE
	695	+ },
	696	+ { .name = "4.1",
	697	+ .val = FLOAT_SIX
	698	+ },
	699	+ { .name = "5.1",
	700	+ .val = FLOAT_EIGHT
642	701	}
643	702	};
644	703
..	..	@@ -667,6 +726,68 @@
667	726	}
668	727	};
669	728
	729	+/* Values for ca0113_mmio_command_set for selecting output. */
	730	+#define AE_CA0113_OUT_SET_COMMANDS 6
	731	+struct ae_ca0113_output_set {
	732	+ unsigned int group[AE_CA0113_OUT_SET_COMMANDS];
	733	+ unsigned int target[AE_CA0113_OUT_SET_COMMANDS];
	734	+ unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS];
	735	+};
	736	+
	737	+static const struct ae_ca0113_output_set ae5_ca0113_output_presets = {
	738	+ .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
	739	+ .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
	740	+ /* Speakers. */
	741	+ .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
	742	+ /* Headphones. */
	743	+ { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
	744	+};
	745	+
	746	+static const struct ae_ca0113_output_set ae7_ca0113_output_presets = {
	747	+ .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
	748	+ .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
	749	+ /* Speakers. */
	750	+ .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
	751	+ /* Headphones. */
	752	+ { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
	753	+};
	754	+
	755	+/* ae5 ca0113 command sequences to set headphone gain levels. */
	756	+#define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
	757	+struct ae5_headphone_gain_set {
	758	+ char *name;
	759	+ unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
	760	+};
	761	+
	762	+static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
	763	+ { .name = "Low (16-31",
	764	+ .vals = { 0xff, 0x2c, 0xf5, 0x32 }
	765	+ },
	766	+ { .name = "Medium (32-149",
	767	+ .vals = { 0x38, 0xa8, 0x3e, 0x4c }
	768	+ },
	769	+ { .name = "High (150-600",
	770	+ .vals = { 0xff, 0xff, 0xff, 0x7f }
	771	+ }
	772	+};
	773	+
	774	+struct ae5_filter_set {
	775	+ char *name;
	776	+ unsigned int val;
	777	+};
	778	+
	779	+static const struct ae5_filter_set ae5_filter_presets[] = {
	780	+ { .name = "Slow Roll Off",
	781	+ .val = 0xa0
	782	+ },
	783	+ { .name = "Minimum Phase",
	784	+ .val = 0xc0
	785	+ },
	786	+ { .name = "Fast Roll Off",
	787	+ .val = 0x80
	788	+ }
	789	+};
	790	+
670	791	enum hda_cmd_vendor_io {
671	792	/* for DspIO node */
672	793	VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
..	..	@@ -686,6 +807,9 @@
686	807	VENDOR_CHIPIO_DATA_LOW = 0x300,
687	808	VENDOR_CHIPIO_DATA_HIGH = 0x400,
688	809
	810	+ VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
	811	+ VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
	812	+
689	813	VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
690	814	VENDOR_CHIPIO_STATUS = 0xF01,
691	815	VENDOR_CHIPIO_HIC_POST_READ = 0x702,
..	..	@@ -693,6 +817,9 @@
693	817
694	818	VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
695	819	VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
	820	+ VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
	821	+ VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
	822	+ VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
696	823
697	824	VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
698	825	VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
..	..	@@ -798,6 +925,12 @@
798	925	/* Port D output stage gain setting to use when 16 Ohm output
799	926	* impedance is selected*/
800	927	CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
	928	+
	929	+ /*
	930	+ * This control param name was found in the 8051 memory, and makes
	931	+ * sense given the fact the AE-5 uses it and has the ASI flag set.
	932	+ */
	933	+ CONTROL_PARAM_ASI = 23,
801	934
802	935	/* Stream Control */
803	936
..	..	@@ -931,7 +1064,6 @@
931	1064	unsigned int scp_resp_header;
932	1065	unsigned int scp_resp_data[4];
933	1066	unsigned int scp_resp_count;
934		- bool alt_firmware_present;
935	1067	bool startup_check_entered;
936	1068	bool dsp_reload;
937	1069
..	..	@@ -949,14 +1081,22 @@
949	1081	/* ca0132_alt control related values */
950	1082	unsigned char in_enum_val;
951	1083	unsigned char out_enum_val;
	1084	+ unsigned char channel_cfg_val;
	1085	+ unsigned char speaker_range_val[2];
952	1086	unsigned char mic_boost_enum_val;
953	1087	unsigned char smart_volume_setting;
	1088	+ unsigned char bass_redirection_val;
	1089	+ long bass_redirect_xover_freq;
954	1090	long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
955	1091	long xbass_xover_freq;
956	1092	long eq_preset_val;
957	1093	unsigned int tlv[4];
958	1094	struct hda_vmaster_mute_hook vmaster_mute;
959		-
	1095	+ /* AE-5 Control values */
	1096	+ unsigned char ae5_headphone_gain_val;
	1097	+ unsigned char ae5_filter_val;
	1098	+ /* ZxR Control Values */
	1099	+ unsigned char zxr_gain_set;
960	1100
961	1101	struct hda_codec *codec;
962	1102	struct delayed_work unsol_hp_work;
..	..	@@ -996,9 +1136,25 @@
996	1136	QUIRK_ALIENWARE,
997	1137	QUIRK_ALIENWARE_M17XR4,
998	1138	QUIRK_SBZ,
	1139	+ QUIRK_ZXR,
	1140	+ QUIRK_ZXR_DBPRO,
999	1141	QUIRK_R3DI,
1000	1142	QUIRK_R3D,
	1143	+ QUIRK_AE5,
	1144	+ QUIRK_AE7,
1001	1145	};
	1146	+
	1147	+#ifdef CONFIG_PCI
	1148	+#define ca0132_quirk(spec) ((spec)->quirk)
	1149	+#define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio)
	1150	+#define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions)
	1151	+#define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls)
	1152	+#else
	1153	+#define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; })
	1154	+#define ca0132_use_alt_functions(spec) ({ (void)(spec); false; })
	1155	+#define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; })
	1156	+#define ca0132_use_alt_controls(spec) ({ (void)(spec); false; })
	1157	+#endif
1002	1158
1003	1159	static const struct hda_pintbl alienware_pincfgs[] = {
1004	1160	{ 0x0b, 0x90170110 }, /* Builtin Speaker */
..	..	@@ -1029,6 +1185,21 @@
1029	1185	{}
1030	1186	};
1031	1187
	1188	+/* Sound Blaster ZxR pin configs taken from Windows Driver */
	1189	+static const struct hda_pintbl zxr_pincfgs[] = {
	1190	+ { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
	1191	+ { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
	1192	+ { 0x0d, 0x014510f0 }, /* Digital Out */
	1193	+ { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
	1194	+ { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
	1195	+ { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
	1196	+ { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
	1197	+ { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
	1198	+ { 0x13, 0x908700f0 }, /* What U Hear In*/
	1199	+ { 0x18, 0x50d000f0 }, /* N/A */
	1200	+ {}
	1201	+};
	1202	+
1032	1203	/* Recon3D pin configs taken from Windows Driver */
1033	1204	static const struct hda_pintbl r3d_pincfgs[] = {
1034	1205	{ 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
..	..	@@ -1039,6 +1210,21 @@
1039	1210	{ 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1040	1211	{ 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1041	1212	{ 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
	1213	+ { 0x13, 0x908700f0 }, /* What U Hear In*/
	1214	+ { 0x18, 0x50d000f0 }, /* N/A */
	1215	+ {}
	1216	+};
	1217	+
	1218	+/* Sound Blaster AE-5 pin configs taken from Windows Driver */
	1219	+static const struct hda_pintbl ae5_pincfgs[] = {
	1220	+ { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
	1221	+ { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
	1222	+ { 0x0d, 0x014510f0 }, /* Digital Out */
	1223	+ { 0x0e, 0x01c510f0 }, /* SPDIF In */
	1224	+ { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
	1225	+ { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
	1226	+ { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
	1227	+ { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1042	1228	{ 0x13, 0x908700f0 }, /* What U Hear In*/
1043	1229	{ 0x18, 0x50d000f0 }, /* N/A */
1044	1230	{}
..	..	@@ -1059,6 +1245,20 @@
1059	1245	{}
1060	1246	};
1061	1247
	1248	+static const struct hda_pintbl ae7_pincfgs[] = {
	1249	+ { 0x0b, 0x01017010 },
	1250	+ { 0x0c, 0x014510f0 },
	1251	+ { 0x0d, 0x414510f0 },
	1252	+ { 0x0e, 0x01c520f0 },
	1253	+ { 0x0f, 0x01017114 },
	1254	+ { 0x10, 0x01017011 },
	1255	+ { 0x11, 0x018170ff },
	1256	+ { 0x12, 0x01a170f0 },
	1257	+ { 0x13, 0x908700f0 },
	1258	+ { 0x18, 0x500000f0 },
	1259	+ {}
	1260	+};
	1261	+
1062	1262	static const struct snd_pci_quirk ca0132_quirks[] = {
1063	1263	SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1064	1264	SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
..	..	@@ -1066,12 +1266,212 @@
1066	1266	SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1067	1267	SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1068	1268	SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
	1269	+ SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
	1270	+ SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1069	1271	SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1070	1272	SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1071	1273	SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1072	1274	SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
	1275	+ SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1073	1276	SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
	1277	+ SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
	1278	+ SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
	1279	+ SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
	1280	+ SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1074	1281	{}
	1282	+};
	1283	+
	1284	+/* Output selection quirk info structures. */
	1285	+#define MAX_QUIRK_MMIO_GPIO_SET_VALS 3
	1286	+#define MAX_QUIRK_SCP_SET_VALS 2
	1287	+struct ca0132_alt_out_set_info {
	1288	+ unsigned int dac2port; /* ParamID 0x0d value. */
	1289	+
	1290	+ bool has_hda_gpio;
	1291	+ char hda_gpio_pin;
	1292	+ char hda_gpio_set;
	1293	+
	1294	+ unsigned int mmio_gpio_count;
	1295	+ char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS];
	1296	+ char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS];
	1297	+
	1298	+ unsigned int scp_cmds_count;
	1299	+ unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS];
	1300	+ unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS];
	1301	+ unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS];
	1302	+
	1303	+ bool has_chipio_write;
	1304	+ unsigned int chipio_write_addr;
	1305	+ unsigned int chipio_write_data;
	1306	+};
	1307	+
	1308	+struct ca0132_alt_out_set_quirk_data {
	1309	+ int quirk_id;
	1310	+
	1311	+ bool has_headphone_gain;
	1312	+ bool is_ae_series;
	1313	+
	1314	+ struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS];
	1315	+};
	1316	+
	1317	+static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = {
	1318	+ { .quirk_id = QUIRK_R3DI,
	1319	+ .has_headphone_gain = false,
	1320	+ .is_ae_series = false,
	1321	+ .out_set_info = {
	1322	+ /* Speakers. */
	1323	+ { .dac2port = 0x24,
	1324	+ .has_hda_gpio = true,
	1325	+ .hda_gpio_pin = 2,
	1326	+ .hda_gpio_set = 1,
	1327	+ .mmio_gpio_count = 0,
	1328	+ .scp_cmds_count = 0,
	1329	+ .has_chipio_write = false,
	1330	+ },
	1331	+ /* Headphones. */
	1332	+ { .dac2port = 0x21,
	1333	+ .has_hda_gpio = true,
	1334	+ .hda_gpio_pin = 2,
	1335	+ .hda_gpio_set = 0,
	1336	+ .mmio_gpio_count = 0,
	1337	+ .scp_cmds_count = 0,
	1338	+ .has_chipio_write = false,
	1339	+ } },
	1340	+ },
	1341	+ { .quirk_id = QUIRK_R3D,
	1342	+ .has_headphone_gain = false,
	1343	+ .is_ae_series = false,
	1344	+ .out_set_info = {
	1345	+ /* Speakers. */
	1346	+ { .dac2port = 0x24,
	1347	+ .has_hda_gpio = false,
	1348	+ .mmio_gpio_count = 1,
	1349	+ .mmio_gpio_pin = { 1 },
	1350	+ .mmio_gpio_set = { 1 },
	1351	+ .scp_cmds_count = 0,
	1352	+ .has_chipio_write = false,
	1353	+ },
	1354	+ /* Headphones. */
	1355	+ { .dac2port = 0x21,
	1356	+ .has_hda_gpio = false,
	1357	+ .mmio_gpio_count = 1,
	1358	+ .mmio_gpio_pin = { 1 },
	1359	+ .mmio_gpio_set = { 0 },
	1360	+ .scp_cmds_count = 0,
	1361	+ .has_chipio_write = false,
	1362	+ } },
	1363	+ },
	1364	+ { .quirk_id = QUIRK_SBZ,
	1365	+ .has_headphone_gain = false,
	1366	+ .is_ae_series = false,
	1367	+ .out_set_info = {
	1368	+ /* Speakers. */
	1369	+ { .dac2port = 0x18,
	1370	+ .has_hda_gpio = false,
	1371	+ .mmio_gpio_count = 3,
	1372	+ .mmio_gpio_pin = { 7, 4, 1 },
	1373	+ .mmio_gpio_set = { 0, 1, 1 },
	1374	+ .scp_cmds_count = 0,
	1375	+ .has_chipio_write = false, },
	1376	+ /* Headphones. */
	1377	+ { .dac2port = 0x12,
	1378	+ .has_hda_gpio = false,
	1379	+ .mmio_gpio_count = 3,
	1380	+ .mmio_gpio_pin = { 7, 4, 1 },
	1381	+ .mmio_gpio_set = { 1, 1, 0 },
	1382	+ .scp_cmds_count = 0,
	1383	+ .has_chipio_write = false,
	1384	+ } },
	1385	+ },
	1386	+ { .quirk_id = QUIRK_ZXR,
	1387	+ .has_headphone_gain = true,
	1388	+ .is_ae_series = false,
	1389	+ .out_set_info = {
	1390	+ /* Speakers. */
	1391	+ { .dac2port = 0x24,
	1392	+ .has_hda_gpio = false,
	1393	+ .mmio_gpio_count = 3,
	1394	+ .mmio_gpio_pin = { 2, 3, 5 },
	1395	+ .mmio_gpio_set = { 1, 1, 0 },
	1396	+ .scp_cmds_count = 0,
	1397	+ .has_chipio_write = false,
	1398	+ },
	1399	+ /* Headphones. */
	1400	+ { .dac2port = 0x21,
	1401	+ .has_hda_gpio = false,
	1402	+ .mmio_gpio_count = 3,
	1403	+ .mmio_gpio_pin = { 2, 3, 5 },
	1404	+ .mmio_gpio_set = { 0, 1, 1 },
	1405	+ .scp_cmds_count = 0,
	1406	+ .has_chipio_write = false,
	1407	+ } },
	1408	+ },
	1409	+ { .quirk_id = QUIRK_AE5,
	1410	+ .has_headphone_gain = true,
	1411	+ .is_ae_series = true,
	1412	+ .out_set_info = {
	1413	+ /* Speakers. */
	1414	+ { .dac2port = 0xa4,
	1415	+ .has_hda_gpio = false,
	1416	+ .mmio_gpio_count = 0,
	1417	+ .scp_cmds_count = 2,
	1418	+ .scp_cmd_mid = { 0x96, 0x96 },
	1419	+ .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
	1420	+ SPEAKER_TUNING_FRONT_RIGHT_INVERT },
	1421	+ .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO },
	1422	+ .has_chipio_write = true,
	1423	+ .chipio_write_addr = 0x0018b03c,
	1424	+ .chipio_write_data = 0x00000012
	1425	+ },
	1426	+ /* Headphones. */
	1427	+ { .dac2port = 0xa1,
	1428	+ .has_hda_gpio = false,
	1429	+ .mmio_gpio_count = 0,
	1430	+ .scp_cmds_count = 2,
	1431	+ .scp_cmd_mid = { 0x96, 0x96 },
	1432	+ .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
	1433	+ SPEAKER_TUNING_FRONT_RIGHT_INVERT },
	1434	+ .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE },
	1435	+ .has_chipio_write = true,
	1436	+ .chipio_write_addr = 0x0018b03c,
	1437	+ .chipio_write_data = 0x00000012
	1438	+ } },
	1439	+ },
	1440	+ { .quirk_id = QUIRK_AE7,
	1441	+ .has_headphone_gain = true,
	1442	+ .is_ae_series = true,
	1443	+ .out_set_info = {
	1444	+ /* Speakers. */
	1445	+ { .dac2port = 0x58,
	1446	+ .has_hda_gpio = false,
	1447	+ .mmio_gpio_count = 1,
	1448	+ .mmio_gpio_pin = { 0 },
	1449	+ .mmio_gpio_set = { 1 },
	1450	+ .scp_cmds_count = 2,
	1451	+ .scp_cmd_mid = { 0x96, 0x96 },
	1452	+ .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
	1453	+ SPEAKER_TUNING_FRONT_RIGHT_INVERT },
	1454	+ .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO },
	1455	+ .has_chipio_write = true,
	1456	+ .chipio_write_addr = 0x0018b03c,
	1457	+ .chipio_write_data = 0x00000000
	1458	+ },
	1459	+ /* Headphones. */
	1460	+ { .dac2port = 0x58,
	1461	+ .has_hda_gpio = false,
	1462	+ .mmio_gpio_count = 1,
	1463	+ .mmio_gpio_pin = { 0 },
	1464	+ .mmio_gpio_set = { 1 },
	1465	+ .scp_cmds_count = 2,
	1466	+ .scp_cmd_mid = { 0x96, 0x96 },
	1467	+ .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
	1468	+ SPEAKER_TUNING_FRONT_RIGHT_INVERT },
	1469	+ .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE },
	1470	+ .has_chipio_write = true,
	1471	+ .chipio_write_addr = 0x0018b03c,
	1472	+ .chipio_write_data = 0x00000010
	1473	+ } },
	1474	+ }
1075	1475	};
1076	1476
1077	1477	/*
..	..	@@ -1456,6 +1856,20 @@
1456	1856	}
1457	1857
1458	1858	/*
	1859	+ * Writes to the 8051's internal address space directly instead of indirectly,
	1860	+ * giving access to the special function registers located at addresses
	1861	+ * 0x80-0xFF.
	1862	+ */
	1863	+static void chipio_8051_write_direct(struct hda_codec *codec,
	1864	+ unsigned int addr, unsigned int data)
	1865	+{
	1866	+ unsigned int verb;
	1867	+
	1868	+ verb = VENDOR_CHIPIO_8051_WRITE_DIRECT \| data;
	1869	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
	1870	+}
	1871	+
	1872	+/*
1459	1873	* Enable clocks.
1460	1874	*/
1461	1875	static void chipio_enable_clocks(struct hda_codec *codec)
..	..	@@ -1798,6 +2212,7 @@
1798	2212	* Prepare and send the SCP message to DSP
1799	2213	* @codec: the HDA codec
1800	2214	* @mod_id: ID of the DSP module to send the command
	2215	+ * @src_id: ID of the source
1801	2216	* @req: ID of request to send to the DSP module
1802	2217	* @dir: SET or GET
1803	2218	* @data: pointer to the data to send with the request, request specific
..	..	@@ -2572,7 +2987,7 @@
2572	2987	u32 magic;
2573	2988	u32 chip_addr;
2574	2989	u32 count;
2575		- u32 data[0];
	2990	+ u32 data[];
2576	2991	};
2577	2992
2578	2993	static const u32 g_magic_value = 0x4c46584d;
..	..	@@ -2595,7 +3010,7 @@
2595	3010
2596	3011	static size_t dsp_sizeof(const struct dsp_image_seg *p)
2597	3012	{
2598		- return sizeof(p) + p->countsizeof(u32);
	3013	+ return struct_size(p, data, p->count);
2599	3014	}
2600	3015
2601	3016	static const struct dsp_image_seg *get_next_seg_ptr(
..	..	@@ -2701,7 +3116,7 @@
2701	3116	}
2702	3117
2703	3118	data = fls->data;
2704		- chip_addx = fls->chip_addr,
	3119	+ chip_addx = fls->chip_addr;
2705	3120	words_to_write = fls->count;
2706	3121
2707	3122	if (!words_to_write)
..	..	@@ -2976,7 +3391,7 @@
2976	3391	{
2977	3392	struct ca0132_spec *spec = codec->spec;
2978	3393	codec_dbg(codec, "---- dspload_post_setup ------\n");
2979		- if (!spec->use_alt_functions) {
	3394	+ if (!ca0132_use_alt_functions(spec)) {
2980	3395	/set DSP speaker to 2.0 configuration/
2981	3396	chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2982	3397	chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
..	..	@@ -3091,7 +3506,9 @@
3091	3506	}
3092	3507
3093	3508	/*
3094		- * Setup GPIO for the other variants of Core3D.
	3509	+ * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
	3510	+ * based cards, and has a second mmio region, region2, that's used for special
	3511	+ * commands.
3095	3512	*/
3096	3513
3097	3514	/*
..	..	@@ -3099,8 +3516,11 @@
3099	3516	* the mmio address 0x320 is used to set GPIO pins. The format for the data
3100	3517	* The first eight bits are just the number of the pin. So far, I've only seen
3101	3518	* this number go to 7.
	3519	+ * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
	3520	+ * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
	3521	+ * then off to send that bit.
3102	3522	*/
3103		-static void ca0132_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
	3523	+static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3104	3524	bool enable)
3105	3525	{
3106	3526	struct ca0132_spec *spec = codec->spec;
..	..	@@ -3113,6 +3533,89 @@
3113	3533	}
3114	3534
3115	3535	/*
	3536	+ * Special pci region2 commands that are only used by the AE-5. They follow
	3537	+ * a set format, and require reads at certain points to seemingly 'clear'
	3538	+ * the response data. My first tests didn't do these reads, and would cause
	3539	+ * the card to get locked up until the memory was read. These commands
	3540	+ * seem to work with three distinct values that I've taken to calling group,
	3541	+ * target-id, and value.
	3542	+ */
	3543	+static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
	3544	+ unsigned int target, unsigned int value)
	3545	+{
	3546	+ struct ca0132_spec *spec = codec->spec;
	3547	+ unsigned int write_val;
	3548	+
	3549	+ writel(0x0000007e, spec->mem_base + 0x210);
	3550	+ readl(spec->mem_base + 0x210);
	3551	+ writel(0x0000005a, spec->mem_base + 0x210);
	3552	+ readl(spec->mem_base + 0x210);
	3553	+ readl(spec->mem_base + 0x210);
	3554	+
	3555	+ writel(0x00800005, spec->mem_base + 0x20c);
	3556	+ writel(group, spec->mem_base + 0x804);
	3557	+
	3558	+ writel(0x00800005, spec->mem_base + 0x20c);
	3559	+ write_val = (target & 0xff);
	3560	+ write_val \|= (value << 8);
	3561	+
	3562	+
	3563	+ writel(write_val, spec->mem_base + 0x204);
	3564	+ /*
	3565	+ * Need delay here or else it goes too fast and works inconsistently.
	3566	+ */
	3567	+ msleep(20);
	3568	+
	3569	+ readl(spec->mem_base + 0x860);
	3570	+ readl(spec->mem_base + 0x854);
	3571	+ readl(spec->mem_base + 0x840);
	3572	+
	3573	+ writel(0x00800004, spec->mem_base + 0x20c);
	3574	+ writel(0x00000000, spec->mem_base + 0x210);
	3575	+ readl(spec->mem_base + 0x210);
	3576	+ readl(spec->mem_base + 0x210);
	3577	+}
	3578	+
	3579	+/*
	3580	+ * This second type of command is used for setting the sound filter type.
	3581	+ */
	3582	+static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
	3583	+ unsigned int group, unsigned int target, unsigned int value)
	3584	+{
	3585	+ struct ca0132_spec *spec = codec->spec;
	3586	+ unsigned int write_val;
	3587	+
	3588	+ writel(0x0000007e, spec->mem_base + 0x210);
	3589	+ readl(spec->mem_base + 0x210);
	3590	+ writel(0x0000005a, spec->mem_base + 0x210);
	3591	+ readl(spec->mem_base + 0x210);
	3592	+ readl(spec->mem_base + 0x210);
	3593	+
	3594	+ writel(0x00800003, spec->mem_base + 0x20c);
	3595	+ writel(group, spec->mem_base + 0x804);
	3596	+
	3597	+ writel(0x00800005, spec->mem_base + 0x20c);
	3598	+ write_val = (target & 0xff);
	3599	+ write_val \|= (value << 8);
	3600	+
	3601	+
	3602	+ writel(write_val, spec->mem_base + 0x204);
	3603	+ msleep(20);
	3604	+ readl(spec->mem_base + 0x860);
	3605	+ readl(spec->mem_base + 0x854);
	3606	+ readl(spec->mem_base + 0x840);
	3607	+
	3608	+ writel(0x00800004, spec->mem_base + 0x20c);
	3609	+ writel(0x00000000, spec->mem_base + 0x210);
	3610	+ readl(spec->mem_base + 0x210);
	3611	+ readl(spec->mem_base + 0x210);
	3612	+}
	3613	+
	3614	+/*
	3615	+ * Setup GPIO for the other variants of Core3D.
	3616	+ */
	3617	+
	3618	+/*
3116	3619	* Sets up the GPIO pins so that they are discoverable. If this isn't done,
3117	3620	* the card shows as having no GPIO pins.
3118	3621	*/
..	..	@@ -3120,8 +3623,10 @@
3120	3623	{
3121	3624	struct ca0132_spec *spec = codec->spec;
3122	3625
3123		- switch (spec->quirk) {
	3626	+ switch (ca0132_quirk(spec)) {
3124	3627	case QUIRK_SBZ:
	3628	+ case QUIRK_AE5:
	3629	+ case QUIRK_AE7:
3125	3630	snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3126	3631	snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3127	3632	snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
..	..	@@ -3129,6 +3634,8 @@
3129	3634	case QUIRK_R3DI:
3130	3635	snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3131	3636	snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
	3637	+ break;
	3638	+ default:
3132	3639	break;
3133	3640	}
3134	3641
..	..	@@ -3139,7 +3646,7 @@
3139	3646	{
3140	3647	struct ca0132_spec *spec = codec->spec;
3141	3648
3142		- switch (spec->quirk) {
	3649	+ switch (ca0132_quirk(spec)) {
3143	3650	case QUIRK_SBZ:
3144	3651	snd_hda_codec_write(codec, 0x01, 0,
3145	3652	AC_VERB_SET_GPIO_DIRECTION, 0x07);
..	..	@@ -3157,6 +3664,8 @@
3157	3664	AC_VERB_SET_GPIO_MASK, 0x1F);
3158	3665	snd_hda_codec_write(codec, 0x01, 0,
3159	3666	AC_VERB_SET_GPIO_DATA, 0x0C);
	3667	+ break;
	3668	+ default:
3160	3669	break;
3161	3670	}
3162	3671	}
..	..	@@ -3217,26 +3726,6 @@
3217	3726	break;
3218	3727	case R3DI_FRONT_MIC:
3219	3728	cur_gpio \|= (1 << R3DI_MIC_SELECT_BIT);
3220		- break;
3221		- }
3222		- snd_hda_codec_write(codec, codec->core.afg, 0,
3223		- AC_VERB_SET_GPIO_DATA, cur_gpio);
3224		-}
3225		-
3226		-static void r3di_gpio_out_set(struct hda_codec *codec,
3227		- enum r3di_out_select cur_out)
3228		-{
3229		- unsigned int cur_gpio;
3230		-
3231		- /* Get the current GPIO Data setup */
3232		- cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3233		-
3234		- switch (cur_out) {
3235		- case R3DI_HEADPHONE_OUT:
3236		- cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3237		- break;
3238		- case R3DI_LINE_OUT:
3239		- cur_gpio \|= (1 << R3DI_OUT_SELECT_BIT);
3240	3729	break;
3241	3730	}
3242	3731	snd_hda_codec_write(codec, codec->core.afg, 0,
..	..	@@ -3550,7 +4039,7 @@
3550	4039	/* The following are for tuning of products */
3551	4040	#ifdef ENABLE_TUNING_CONTROLS
3552	4041
3553		-static unsigned int voice_focus_vals_lookup[] = {
	4042	+static const unsigned int voice_focus_vals_lookup[] = {
3554	4043	0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
3555	4044	0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
3556	4045	0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
..	..	@@ -3580,7 +4069,7 @@
3580	4069	0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3581	4070	};
3582	4071
3583		-static unsigned int mic_svm_vals_lookup[] = {
	4072	+static const unsigned int mic_svm_vals_lookup[] = {
3584	4073	0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3585	4074	0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3586	4075	0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
..	..	@@ -3600,7 +4089,7 @@
3600	4089	0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3601	4090	};
3602	4091
3603		-static unsigned int equalizer_vals_lookup[] = {
	4092	+static const unsigned int equalizer_vals_lookup[] = {
3604	4093	0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3605	4094	0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3606	4095	0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
..	..	@@ -3613,7 +4102,7 @@
3613	4102	};
3614	4103
3615	4104	static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3616		- unsigned int *lookup, int idx)
	4105	+ const unsigned int *lookup, int idx)
3617	4106	{
3618	4107	int i = 0;
3619	4108
..	..	@@ -3931,24 +4420,221 @@
3931	4420	return err < 0 ? err : 0;
3932	4421	}
3933	4422
	4423	+static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
	4424	+static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
	4425	+static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
	4426	+
	4427	+static void ae5_mmio_select_out(struct hda_codec *codec)
	4428	+{
	4429	+ struct ca0132_spec *spec = codec->spec;
	4430	+ const struct ae_ca0113_output_set *out_cmds;
	4431	+ unsigned int i;
	4432	+
	4433	+ if (ca0132_quirk(spec) == QUIRK_AE5)
	4434	+ out_cmds = &ae5_ca0113_output_presets;
	4435	+ else
	4436	+ out_cmds = &ae7_ca0113_output_presets;
	4437	+
	4438	+ for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++)
	4439	+ ca0113_mmio_command_set(codec, out_cmds->group[i],
	4440	+ out_cmds->target[i],
	4441	+ out_cmds->vals[spec->cur_out_type][i]);
	4442	+}
	4443	+
	4444	+static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)
	4445	+{
	4446	+ struct ca0132_spec *spec = codec->spec;
	4447	+ int quirk = ca0132_quirk(spec);
	4448	+ unsigned int tmp;
	4449	+ int err;
	4450	+
	4451	+ /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */
	4452	+ if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0
	4453	+ \|\| spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
	4454	+ return 0;
	4455	+
	4456	+ /* Set front L/R full range. Zero for full-range, one for redirection. */
	4457	+ tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
	4458	+ err = dspio_set_uint_param(codec, 0x96,
	4459	+ SPEAKER_FULL_RANGE_FRONT_L_R, tmp);
	4460	+ if (err < 0)
	4461	+ return err;
	4462	+
	4463	+ /* When setting full-range rear, both rear and center/lfe are set. */
	4464	+ tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE;
	4465	+ err = dspio_set_uint_param(codec, 0x96,
	4466	+ SPEAKER_FULL_RANGE_CENTER_LFE, tmp);
	4467	+ if (err < 0)
	4468	+ return err;
	4469	+
	4470	+ err = dspio_set_uint_param(codec, 0x96,
	4471	+ SPEAKER_FULL_RANGE_REAR_L_R, tmp);
	4472	+ if (err < 0)
	4473	+ return err;
	4474	+
	4475	+ /*
	4476	+ * Only the AE series cards set this value when setting full-range,
	4477	+ * and it's always 1.0f.
	4478	+ */
	4479	+ if (quirk == QUIRK_AE5 \|\| quirk == QUIRK_AE7) {
	4480	+ err = dspio_set_uint_param(codec, 0x96,
	4481	+ SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE);
	4482	+ if (err < 0)
	4483	+ return err;
	4484	+ }
	4485	+
	4486	+ return 0;
	4487	+}
	4488	+
	4489	+static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec,
	4490	+ bool val)
	4491	+{
	4492	+ struct ca0132_spec *spec = codec->spec;
	4493	+ unsigned int tmp;
	4494	+ int err;
	4495	+
	4496	+ if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 &&
	4497	+ spec->channel_cfg_val != SPEAKER_CHANNELS_2_0)
	4498	+ tmp = FLOAT_ONE;
	4499	+ else
	4500	+ tmp = FLOAT_ZERO;
	4501	+
	4502	+ err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
	4503	+ if (err < 0)
	4504	+ return err;
	4505	+
	4506	+ /* If it is enabled, make sure to set the crossover frequency. */
	4507	+ if (tmp) {
	4508	+ tmp = float_xbass_xover_lookup[spec->xbass_xover_freq];
	4509	+ err = dspio_set_uint_param(codec, 0x96,
	4510	+ SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp);
	4511	+ if (err < 0)
	4512	+ return err;
	4513	+ }
	4514	+
	4515	+ return 0;
	4516	+}
	4517	+
	4518	+/*
	4519	+ * These are the commands needed to setup output on each of the different card
	4520	+ * types.
	4521	+ */
	4522	+static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec,
	4523	+ const struct ca0132_alt_out_set_quirk_data **quirk_data)
	4524	+{
	4525	+ struct ca0132_spec *spec = codec->spec;
	4526	+ int quirk = ca0132_quirk(spec);
	4527	+ unsigned int i;
	4528	+
	4529	+ *quirk_data = NULL;
	4530	+ for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) {
	4531	+ if (quirk_out_set_data[i].quirk_id == quirk) {
	4532	+ *quirk_data = &quirk_out_set_data[i];
	4533	+ return;
	4534	+ }
	4535	+ }
	4536	+}
	4537	+
	4538	+static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)
	4539	+{
	4540	+ const struct ca0132_alt_out_set_quirk_data *quirk_data;
	4541	+ const struct ca0132_alt_out_set_info *out_info;
	4542	+ struct ca0132_spec *spec = codec->spec;
	4543	+ unsigned int i, gpio_data;
	4544	+ int err;
	4545	+
	4546	+ ca0132_alt_select_out_get_quirk_data(codec, &quirk_data);
	4547	+ if (!quirk_data)
	4548	+ return 0;
	4549	+
	4550	+ out_info = &quirk_data->out_set_info[spec->cur_out_type];
	4551	+ if (quirk_data->is_ae_series)
	4552	+ ae5_mmio_select_out(codec);
	4553	+
	4554	+ if (out_info->has_hda_gpio) {
	4555	+ gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
	4556	+ AC_VERB_GET_GPIO_DATA, 0);
	4557	+
	4558	+ if (out_info->hda_gpio_set)
	4559	+ gpio_data \|= (1 << out_info->hda_gpio_pin);
	4560	+ else
	4561	+ gpio_data &= ~(1 << out_info->hda_gpio_pin);
	4562	+
	4563	+ snd_hda_codec_write(codec, codec->core.afg, 0,
	4564	+ AC_VERB_SET_GPIO_DATA, gpio_data);
	4565	+ }
	4566	+
	4567	+ if (out_info->mmio_gpio_count) {
	4568	+ for (i = 0; i < out_info->mmio_gpio_count; i++) {
	4569	+ ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i],
	4570	+ out_info->mmio_gpio_set[i]);
	4571	+ }
	4572	+ }
	4573	+
	4574	+ if (out_info->scp_cmds_count) {
	4575	+ for (i = 0; i < out_info->scp_cmds_count; i++) {
	4576	+ err = dspio_set_uint_param(codec,
	4577	+ out_info->scp_cmd_mid[i],
	4578	+ out_info->scp_cmd_req[i],
	4579	+ out_info->scp_cmd_val[i]);
	4580	+ if (err < 0)
	4581	+ return err;
	4582	+ }
	4583	+ }
	4584	+
	4585	+ chipio_set_control_param(codec, 0x0d, out_info->dac2port);
	4586	+
	4587	+ if (out_info->has_chipio_write) {
	4588	+ chipio_write(codec, out_info->chipio_write_addr,
	4589	+ out_info->chipio_write_data);
	4590	+ }
	4591	+
	4592	+ if (quirk_data->has_headphone_gain) {
	4593	+ if (spec->cur_out_type != HEADPHONE_OUT) {
	4594	+ if (quirk_data->is_ae_series)
	4595	+ ae5_headphone_gain_set(codec, 2);
	4596	+ else
	4597	+ zxr_headphone_gain_set(codec, 0);
	4598	+ } else {
	4599	+ if (quirk_data->is_ae_series)
	4600	+ ae5_headphone_gain_set(codec,
	4601	+ spec->ae5_headphone_gain_val);
	4602	+ else
	4603	+ zxr_headphone_gain_set(codec,
	4604	+ spec->zxr_gain_set);
	4605	+ }
	4606	+ }
	4607	+
	4608	+ return 0;
	4609	+}
	4610	+
	4611	+static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid,
	4612	+ bool out_enable, bool hp_enable)
	4613	+{
	4614	+ unsigned int pin_ctl;
	4615	+
	4616	+ pin_ctl = snd_hda_codec_read(codec, nid, 0,
	4617	+ AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
	4618	+
	4619	+ pin_ctl = hp_enable ? pin_ctl \| PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP;
	4620	+ pin_ctl = out_enable ? pin_ctl \| PIN_OUT : pin_ctl & ~PIN_OUT;
	4621	+ snd_hda_set_pin_ctl(codec, nid, pin_ctl);
	4622	+}
	4623	+
3934	4624	/*
3935	4625	* This function behaves similarly to the ca0132_select_out funciton above,
3936	4626	* except with a few differences. It adds the ability to select the current
3937	4627	* output with an enumerated control "output source" if the auto detect
3938	4628	* mute switch is set to off. If the auto detect mute switch is enabled, it
3939	4629	* will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
3940		- * It also adds the ability to auto-detect the front headphone port. The only
3941		- * way to select surround is to disable auto detect, and set Surround with the
3942		- * enumerated control.
	4630	+ * It also adds the ability to auto-detect the front headphone port.
3943	4631	*/
3944	4632	static int ca0132_alt_select_out(struct hda_codec *codec)
3945	4633	{
3946	4634	struct ca0132_spec *spec = codec->spec;
3947		- unsigned int pin_ctl;
	4635	+ unsigned int tmp, outfx_set;
3948	4636	int jack_present;
3949	4637	int auto_jack;
3950		- unsigned int i;
3951		- unsigned int tmp;
3952	4638	int err;
3953	4639	/* Default Headphone is rear headphone */
3954	4640	hda_nid_t headphone_nid = spec->out_pins[1];
..	..	@@ -3975,156 +4661,112 @@
3975	4661	} else
3976	4662	spec->cur_out_type = spec->out_enum_val;
3977	4663
3978		- /* Begin DSP output switch */
3979		- tmp = FLOAT_ONE;
3980		- err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
	4664	+ outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID];
	4665	+
	4666	+ /* Begin DSP output switch, mute DSP volume. */
	4667	+ err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);
3981	4668	if (err < 0)
	4669	+ goto exit;
	4670	+
	4671	+ if (ca0132_alt_select_out_quirk_set(codec) < 0)
3982	4672	goto exit;
3983	4673
3984	4674	switch (spec->cur_out_type) {
3985	4675	case SPEAKER_OUT:
3986	4676	codec_dbg(codec, "%s speaker\n", __func__);
3987		- /speaker out config/
3988		- switch (spec->quirk) {
3989		- case QUIRK_SBZ:
3990		- ca0132_mmio_gpio_set(codec, 7, false);
3991		- ca0132_mmio_gpio_set(codec, 4, true);
3992		- ca0132_mmio_gpio_set(codec, 1, true);
3993		- chipio_set_control_param(codec, 0x0D, 0x18);
3994		- break;
3995		- case QUIRK_R3DI:
3996		- chipio_set_control_param(codec, 0x0D, 0x24);
3997		- r3di_gpio_out_set(codec, R3DI_LINE_OUT);
3998		- break;
3999		- case QUIRK_R3D:
4000		- chipio_set_control_param(codec, 0x0D, 0x24);
4001		- ca0132_mmio_gpio_set(codec, 1, true);
4002		- break;
4003		- }
4004	4677
4005		- /* disable headphone node */
4006		- pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4007		- AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4008		- snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4009		- pin_ctl & ~PIN_HP);
4010		- /* enable line-out node */
4011		- pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4012		- AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4013		- snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4014		- pin_ctl \| PIN_OUT);
4015	4678	/* Enable EAPD */
4016	4679	snd_hda_codec_write(codec, spec->out_pins[0], 0,
4017	4680	AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4018	4681
4019		- /* If PlayEnhancement is enabled, set different source */
4020		- if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4021		- dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
	4682	+ /* Disable headphone node. */
	4683	+ ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);
	4684	+ /* Set front L-R to output. */
	4685	+ ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);
	4686	+ /* Set Center/LFE to output. */
	4687	+ ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);
	4688	+ /* Set rear surround to output. */
	4689	+ ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);
	4690	+
	4691	+ /*
	4692	+ * Without PlayEnhancement being enabled, if we've got a 2.0
	4693	+ * setup, set it to floating point eight to disable any DSP
	4694	+ * processing effects.
	4695	+ */
	4696	+ if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
	4697	+ tmp = FLOAT_EIGHT;
4022	4698	else
4023		- dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
	4699	+ tmp = speaker_channel_cfgs[spec->channel_cfg_val].val;
	4700	+
	4701	+ err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
	4702	+ if (err < 0)
	4703	+ goto exit;
	4704	+
4024	4705	break;
4025	4706	case HEADPHONE_OUT:
4026	4707	codec_dbg(codec, "%s hp\n", __func__);
4027		- /* Headphone out config*/
4028		- switch (spec->quirk) {
4029		- case QUIRK_SBZ:
4030		- ca0132_mmio_gpio_set(codec, 7, true);
4031		- ca0132_mmio_gpio_set(codec, 4, true);
4032		- ca0132_mmio_gpio_set(codec, 1, false);
4033		- chipio_set_control_param(codec, 0x0D, 0x12);
4034		- break;
4035		- case QUIRK_R3DI:
4036		- chipio_set_control_param(codec, 0x0D, 0x21);
4037		- r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4038		- break;
4039		- case QUIRK_R3D:
4040		- chipio_set_control_param(codec, 0x0D, 0x21);
4041		- ca0132_mmio_gpio_set(codec, 0x1, false);
4042		- break;
4043		- }
4044		-
4045	4708	snd_hda_codec_write(codec, spec->out_pins[0], 0,
4046	4709	AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4047	4710
4048		- /* disable speaker*/
4049		- pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4050		- AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4051		- snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4052		- pin_ctl & ~PIN_HP);
	4711	+ /* Disable all speaker nodes. */
	4712	+ ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);
	4713	+ ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);
	4714	+ ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);
4053	4715
4054	4716	/* enable headphone, either front or rear */
4055		-
4056	4717	if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4057	4718	headphone_nid = spec->out_pins[2];
4058	4719	else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4059	4720	headphone_nid = spec->out_pins[1];
4060	4721
4061		- pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4062		- AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4063		- snd_hda_set_pin_ctl(codec, headphone_nid,
4064		- pin_ctl \| PIN_HP);
	4722	+ ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1);
4065	4723
4066		- if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4067		- dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
	4724	+ if (outfx_set)
	4725	+ err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4068	4726	else
4069		- dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4070		- break;
4071		- case SURROUND_OUT:
4072		- codec_dbg(codec, "%s surround\n", __func__);
4073		- /* Surround out config*/
4074		- switch (spec->quirk) {
4075		- case QUIRK_SBZ:
4076		- ca0132_mmio_gpio_set(codec, 7, false);
4077		- ca0132_mmio_gpio_set(codec, 4, true);
4078		- ca0132_mmio_gpio_set(codec, 1, true);
4079		- chipio_set_control_param(codec, 0x0D, 0x18);
4080		- break;
4081		- case QUIRK_R3DI:
4082		- chipio_set_control_param(codec, 0x0D, 0x24);
4083		- r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4084		- break;
4085		- case QUIRK_R3D:
4086		- ca0132_mmio_gpio_set(codec, 1, true);
4087		- chipio_set_control_param(codec, 0x0D, 0x24);
4088		- break;
4089		- }
4090		- /* enable line out node */
4091		- pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4092		- AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4093		- snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4094		- pin_ctl \| PIN_OUT);
4095		- /* Disable headphone out */
4096		- pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4097		- AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4098		- snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4099		- pin_ctl & ~PIN_HP);
4100		- /* Enable EAPD on line out */
4101		- snd_hda_codec_write(codec, spec->out_pins[0], 0,
4102		- AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4103		- /* enable center/lfe out node */
4104		- pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4105		- AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4106		- snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4107		- pin_ctl \| PIN_OUT);
4108		- /* Now set rear surround node as out. */
4109		- pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4110		- AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4111		- snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4112		- pin_ctl \| PIN_OUT);
	4727	+ err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4113	4728
4114		- if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4115		- dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4116		- else
4117		- dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
	4729	+ if (err < 0)
	4730	+ goto exit;
4118	4731	break;
4119	4732	}
	4733	+ /*
	4734	+ * If output effects are enabled, set the X-Bass effect value again to
	4735	+ * make sure that it's properly enabled/disabled for speaker
	4736	+ * configurations with an LFE channel.
	4737	+ */
	4738	+ if (outfx_set)
	4739	+ ca0132_effects_set(codec, X_BASS,
	4740	+ spec->effects_switch[X_BASS - EFFECT_START_NID]);
4120	4741
4121		- /* run through the output dsp commands for line-out */
4122		- for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4123		- err = dspio_set_uint_param(codec,
4124		- alt_out_presets[spec->cur_out_type].mids[i],
4125		- alt_out_presets[spec->cur_out_type].reqs[i],
4126		- alt_out_presets[spec->cur_out_type].vals[i]);
	4742	+ /* Set speaker EQ bypass attenuation to 0. */
	4743	+ err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);
	4744	+ if (err < 0)
	4745	+ goto exit;
4127	4746
	4747	+ /*
	4748	+ * Although unused on all cards but the AE series, this is always set
	4749	+ * to zero when setting the output.
	4750	+ */
	4751	+ err = dspio_set_uint_param(codec, 0x96,
	4752	+ SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO);
	4753	+ if (err < 0)
	4754	+ goto exit;
	4755	+
	4756	+ if (spec->cur_out_type == SPEAKER_OUT)
	4757	+ err = ca0132_alt_surround_set_bass_redirection(codec,
	4758	+ spec->bass_redirection_val);
	4759	+ else
	4760	+ err = ca0132_alt_surround_set_bass_redirection(codec, 0);
	4761	+
	4762	+ /* Unmute DSP now that we're done with output selection. */
	4763	+ err = dspio_set_uint_param(codec, 0x96,
	4764	+ SPEAKER_TUNING_MUTE, FLOAT_ZERO);
	4765	+ if (err < 0)
	4766	+ goto exit;
	4767	+
	4768	+ if (spec->cur_out_type == SPEAKER_OUT) {
	4769	+ err = ca0132_alt_set_full_range_speaker(codec);
4128	4770	if (err < 0)
4129	4771	goto exit;
4130	4772	}
..	..	@@ -4141,7 +4783,7 @@
4141	4783	to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4142	4784	struct hda_jack_tbl *jack;
4143	4785
4144		- if (spec->use_alt_functions)
	4786	+ if (ca0132_use_alt_functions(spec))
4145	4787	ca0132_alt_select_out(spec->codec);
4146	4788	else
4147	4789	ca0132_select_out(spec->codec);
..	..	@@ -4155,7 +4797,6 @@
4155	4797
4156	4798	static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4157	4799	static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4158		-static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4159	4800	static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4160	4801	static int stop_mic1(struct hda_codec *codec);
4161	4802	static int ca0132_cvoice_switch_set(struct hda_codec *codec);
..	..	@@ -4226,14 +4867,14 @@
4226	4867
4227	4868	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4228	4869	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4229		- if (spec->quirk == QUIRK_R3DI)
	4870	+ if (ca0132_quirk(spec) == QUIRK_R3DI)
4230	4871	chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4231	4872
4232	4873
4233	4874	if (spec->in_enum_val == REAR_LINE_IN)
4234	4875	tmp = FLOAT_ZERO;
4235	4876	else {
4236		- if (spec->quirk == QUIRK_SBZ)
	4877	+ if (ca0132_quirk(spec) == QUIRK_SBZ)
4237	4878	tmp = FLOAT_THREE;
4238	4879	else
4239	4880	tmp = FLOAT_ONE;
..	..	@@ -4245,7 +4886,7 @@
4245	4886	codec_dbg(codec, "%s: on.", __func__);
4246	4887	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4247	4888	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4248		- if (spec->quirk == QUIRK_R3DI)
	4889	+ if (ca0132_quirk(spec) == QUIRK_R3DI)
4249	4890	chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4250	4891
4251	4892	if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
..	..	@@ -4341,15 +4982,31 @@
4341	4982
4342	4983	switch (spec->cur_mic_type) {
4343	4984	case REAR_MIC:
4344		- switch (spec->quirk) {
	4985	+ switch (ca0132_quirk(spec)) {
4345	4986	case QUIRK_SBZ:
4346	4987	case QUIRK_R3D:
4347		- ca0132_mmio_gpio_set(codec, 0, false);
	4988	+ ca0113_mmio_gpio_set(codec, 0, false);
	4989	+ tmp = FLOAT_THREE;
	4990	+ break;
	4991	+ case QUIRK_ZXR:
4348	4992	tmp = FLOAT_THREE;
4349	4993	break;
4350	4994	case QUIRK_R3DI:
4351	4995	r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4352	4996	tmp = FLOAT_ONE;
	4997	+ break;
	4998	+ case QUIRK_AE5:
	4999	+ ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
	5000	+ tmp = FLOAT_THREE;
	5001	+ break;
	5002	+ case QUIRK_AE7:
	5003	+ ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
	5004	+ tmp = FLOAT_THREE;
	5005	+ chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
	5006	+ SR_96_000);
	5007	+ chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
	5008	+ SR_96_000);
	5009	+ dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
4353	5010	break;
4354	5011	default:
4355	5012	tmp = FLOAT_ONE;
..	..	@@ -4358,60 +5015,95 @@
4358	5015
4359	5016	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4360	5017	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4361		- if (spec->quirk == QUIRK_R3DI)
	5018	+ if (ca0132_quirk(spec) == QUIRK_R3DI)
4362	5019	chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4363	5020
4364	5021	dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4365	5022
4366	5023	chipio_set_stream_control(codec, 0x03, 1);
4367	5024	chipio_set_stream_control(codec, 0x04, 1);
4368		-
4369		- if (spec->quirk == QUIRK_SBZ) {
	5025	+ switch (ca0132_quirk(spec)) {
	5026	+ case QUIRK_SBZ:
4370	5027	chipio_write(codec, 0x18B098, 0x0000000C);
4371	5028	chipio_write(codec, 0x18B09C, 0x0000000C);
	5029	+ break;
	5030	+ case QUIRK_ZXR:
	5031	+ chipio_write(codec, 0x18B098, 0x0000000C);
	5032	+ chipio_write(codec, 0x18B09C, 0x000000CC);
	5033	+ break;
	5034	+ case QUIRK_AE5:
	5035	+ chipio_write(codec, 0x18B098, 0x0000000C);
	5036	+ chipio_write(codec, 0x18B09C, 0x0000004C);
	5037	+ break;
	5038	+ default:
	5039	+ break;
4372	5040	}
4373	5041	ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4374	5042	break;
4375	5043	case REAR_LINE_IN:
4376	5044	ca0132_mic_boost_set(codec, 0);
4377		- switch (spec->quirk) {
	5045	+ switch (ca0132_quirk(spec)) {
4378	5046	case QUIRK_SBZ:
4379	5047	case QUIRK_R3D:
4380		- ca0132_mmio_gpio_set(codec, 0, false);
	5048	+ ca0113_mmio_gpio_set(codec, 0, false);
4381	5049	break;
4382	5050	case QUIRK_R3DI:
4383	5051	r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
	5052	+ break;
	5053	+ case QUIRK_AE5:
	5054	+ ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
	5055	+ break;
	5056	+ case QUIRK_AE7:
	5057	+ ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
	5058	+ chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
	5059	+ SR_96_000);
	5060	+ chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
	5061	+ SR_96_000);
	5062	+ dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
	5063	+ break;
	5064	+ default:
4384	5065	break;
4385	5066	}
4386	5067
4387	5068	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4388	5069	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4389		- if (spec->quirk == QUIRK_R3DI)
	5070	+ if (ca0132_quirk(spec) == QUIRK_R3DI)
4390	5071	chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4391	5072
4392		- tmp = FLOAT_ZERO;
	5073	+ if (ca0132_quirk(spec) == QUIRK_AE7)
	5074	+ tmp = FLOAT_THREE;
	5075	+ else
	5076	+ tmp = FLOAT_ZERO;
4393	5077	dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4394	5078
4395		- if (spec->quirk == QUIRK_SBZ) {
	5079	+ switch (ca0132_quirk(spec)) {
	5080	+ case QUIRK_SBZ:
	5081	+ case QUIRK_AE5:
4396	5082	chipio_write(codec, 0x18B098, 0x00000000);
4397	5083	chipio_write(codec, 0x18B09C, 0x00000000);
	5084	+ break;
	5085	+ default:
	5086	+ break;
4398	5087	}
4399		-
4400	5088	chipio_set_stream_control(codec, 0x03, 1);
4401	5089	chipio_set_stream_control(codec, 0x04, 1);
4402	5090	break;
4403	5091	case FRONT_MIC:
4404		- switch (spec->quirk) {
	5092	+ switch (ca0132_quirk(spec)) {
4405	5093	case QUIRK_SBZ:
4406	5094	case QUIRK_R3D:
4407		- ca0132_mmio_gpio_set(codec, 0, true);
4408		- ca0132_mmio_gpio_set(codec, 5, false);
	5095	+ ca0113_mmio_gpio_set(codec, 0, true);
	5096	+ ca0113_mmio_gpio_set(codec, 5, false);
4409	5097	tmp = FLOAT_THREE;
4410	5098	break;
4411	5099	case QUIRK_R3DI:
4412	5100	r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4413	5101	tmp = FLOAT_ONE;
4414	5102	break;
	5103	+ case QUIRK_AE5:
	5104	+ ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
	5105	+ tmp = FLOAT_THREE;
	5106	+ break;
4415	5107	default:
4416	5108	tmp = FLOAT_ONE;
4417	5109	break;
..	..	@@ -4419,7 +5111,7 @@
4419	5111
4420	5112	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4421	5113	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4422		- if (spec->quirk == QUIRK_R3DI)
	5114	+ if (ca0132_quirk(spec) == QUIRK_R3DI)
4423	5115	chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4424	5116
4425	5117	dspio_set_uint_param(codec, 0x80, 0x00, tmp);
..	..	@@ -4427,9 +5119,17 @@
4427	5119	chipio_set_stream_control(codec, 0x03, 1);
4428	5120	chipio_set_stream_control(codec, 0x04, 1);
4429	5121
4430		- if (spec->quirk == QUIRK_SBZ) {
	5122	+ switch (ca0132_quirk(spec)) {
	5123	+ case QUIRK_SBZ:
4431	5124	chipio_write(codec, 0x18B098, 0x0000000C);
4432	5125	chipio_write(codec, 0x18B09C, 0x000000CC);
	5126	+ break;
	5127	+ case QUIRK_AE5:
	5128	+ chipio_write(codec, 0x18B098, 0x0000000C);
	5129	+ chipio_write(codec, 0x18B09C, 0x0000004C);
	5130	+ break;
	5131	+ default:
	5132	+ break;
4433	5133	}
4434	5134	ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4435	5135	break;
..	..	@@ -4438,7 +5138,6 @@
4438	5138
4439	5139	snd_hda_power_down_pm(codec);
4440	5140	return 0;
4441		-
4442	5141	}
4443	5142
4444	5143	/*
..	..	@@ -4497,7 +5196,7 @@
4497	5196	static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4498	5197	{
4499	5198	struct ca0132_spec *spec = codec->spec;
4500		- unsigned int on, tmp;
	5199	+ unsigned int on, tmp, channel_cfg;
4501	5200	int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4502	5201	int err = 0;
4503	5202	int idx = nid - EFFECT_START_NID;
..	..	@@ -4510,6 +5209,12 @@
4510	5209	/* if PE if off, turn off out effects. */
4511	5210	if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4512	5211	val = 0;
	5212	+ if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) {
	5213	+ channel_cfg = spec->channel_cfg_val;
	5214	+ if (channel_cfg != SPEAKER_CHANNELS_2_0 &&
	5215	+ channel_cfg != SPEAKER_CHANNELS_4_0)
	5216	+ val = 0;
	5217	+ }
4513	5218	}
4514	5219
4515	5220	/* for in effect, qualify with CrystalVoice */
..	..	@@ -4523,7 +5228,7 @@
4523	5228	val = 0;
4524	5229
4525	5230	/* If Voice Focus on SBZ, set to two channel. */
4526		- if ((nid == VOICE_FOCUS) && (spec->use_pci_mmio)
	5231	+ if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)
4527	5232	&& (spec->cur_mic_type != REAR_LINE_IN)) {
4528	5233	if (spec->effects_switch[CRYSTAL_VOICE -
4529	5234	EFFECT_START_NID]) {
..	..	@@ -4542,7 +5247,7 @@
4542	5247	* For SBZ noise reduction, there's an extra command
4543	5248	* to module ID 0x47. No clue why.
4544	5249	*/
4545		- if ((nid == NOISE_REDUCTION) && (spec->use_pci_mmio)
	5250	+ if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)
4546	5251	&& (spec->cur_mic_type != REAR_LINE_IN)) {
4547	5252	if (spec->effects_switch[CRYSTAL_VOICE -
4548	5253	EFFECT_START_NID]) {
..	..	@@ -4558,7 +5263,7 @@
4558	5263	}
4559	5264
4560	5265	/* If rear line in disable effects. */
4561		- if (spec->use_alt_functions &&
	5266	+ if (ca0132_use_alt_functions(spec) &&
4562	5267	spec->in_enum_val == REAR_LINE_IN)
4563	5268	val = 0;
4564	5269	}
..	..	@@ -4588,7 +5293,7 @@
4588	5293	codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
4589	5294	spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4590	5295
4591		- if (spec->use_alt_functions)
	5296	+ if (ca0132_use_alt_functions(spec))
4592	5297	ca0132_alt_select_out(codec);
4593	5298
4594	5299	i = OUT_EFFECT_START_NID - EFFECT_START_NID;
..	..	@@ -4648,7 +5353,7 @@
4648	5353
4649	5354	/* set correct vipsource */
4650	5355	oldval = stop_mic1(codec);
4651		- if (spec->use_alt_functions)
	5356	+ if (ca0132_use_alt_functions(spec))
4652	5357	ret \|= ca0132_alt_set_vipsource(codec, 1);
4653	5358	else
4654	5359	ret \|= ca0132_set_vipsource(codec, 1);
..	..	@@ -4681,6 +5386,27 @@
4681	5386	return ret;
4682	5387	}
4683	5388
	5389	+static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
	5390	+{
	5391	+ unsigned int i;
	5392	+
	5393	+ for (i = 0; i < 4; i++)
	5394	+ ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
	5395	+ ae5_headphone_gain_presets[val].vals[i]);
	5396	+ return 0;
	5397	+}
	5398	+
	5399	+/*
	5400	+ * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
	5401	+ * amplifier to handle a 600 ohm load.
	5402	+ */
	5403	+static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
	5404	+{
	5405	+ ca0113_mmio_gpio_set(codec, 1, val);
	5406	+
	5407	+ return 0;
	5408	+}
	5409	+
4684	5410	static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4685	5411	struct snd_ctl_elem_value *ucontrol)
4686	5412	{
..	..	@@ -4696,7 +5422,7 @@
4696	5422	auto_jack =
4697	5423	spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4698	5424	if (!auto_jack) {
4699		- if (spec->use_alt_functions)
	5425	+ if (ca0132_use_alt_functions(spec))
4700	5426	ca0132_alt_select_out(codec);
4701	5427	else
4702	5428	ca0132_select_out(codec);
..	..	@@ -4713,7 +5439,7 @@
4713	5439	}
4714	5440
4715	5441	if (nid == VNID_HP_ASEL) {
4716		- if (spec->use_alt_functions)
	5442	+ if (ca0132_use_alt_functions(spec))
4717	5443	ca0132_alt_select_out(codec);
4718	5444	else
4719	5445	ca0132_select_out(codec);
..	..	@@ -4744,6 +5470,18 @@
4744	5470	return ret;
4745	5471	}
4746	5472	/* End of control change helpers. */
	5473	+
	5474	+static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec,
	5475	+ long idx)
	5476	+{
	5477	+ snd_hda_power_up(codec);
	5478	+
	5479	+ dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ,
	5480	+ &(float_xbass_xover_lookup[idx]), sizeof(unsigned int));
	5481	+
	5482	+ snd_hda_power_down(codec);
	5483	+}
	5484	+
4747	5485	/*
4748	5486	* Below I've added controls to mess with the effect levels, I've only enabled
4749	5487	* them on the Sound Blaster Z, but they would probably also work on the
..	..	@@ -4752,6 +5490,7 @@
4752	5490	*/
4753	5491
4754	5492	/* Sets DSP effect level from the sliders above the controls */
	5493	+
4755	5494	static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4756	5495	const unsigned int *lookup, int idx)
4757	5496	{
..	..	@@ -4797,8 +5536,13 @@
4797	5536	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4798	5537	struct ca0132_spec *spec = codec->spec;
4799	5538	long *valp = ucontrol->value.integer.value;
	5539	+ hda_nid_t nid = get_amp_nid(kcontrol);
4800	5540
4801		- *valp = spec->xbass_xover_freq;
	5541	+ if (nid == BASS_REDIRECTION_XOVER)
	5542	+ *valp = spec->bass_redirect_xover_freq;
	5543	+ else
	5544	+ *valp = spec->xbass_xover_freq;
	5545	+
4802	5546	return 0;
4803	5547	}
4804	5548
..	..	@@ -4852,16 +5596,25 @@
4852	5596	struct ca0132_spec *spec = codec->spec;
4853	5597	hda_nid_t nid = get_amp_nid(kcontrol);
4854	5598	long *valp = ucontrol->value.integer.value;
	5599	+ long *cur_val;
4855	5600	int idx;
4856	5601
	5602	+ if (nid == BASS_REDIRECTION_XOVER)
	5603	+ cur_val = &spec->bass_redirect_xover_freq;
	5604	+ else
	5605	+ cur_val = &spec->xbass_xover_freq;
	5606	+
4857	5607	/* any change? */
4858		- if (spec->xbass_xover_freq == *valp)
	5608	+ if (cur_val == valp)
4859	5609	return 0;
4860	5610
4861		- spec->xbass_xover_freq = *valp;
	5611	+ cur_val = valp;
4862	5612
4863	5613	idx = *valp;
4864		- ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
	5614	+ if (nid == BASS_REDIRECTION_XOVER)
	5615	+ ca0132_alt_bass_redirection_xover_set(codec, *cur_val);
	5616	+ else
	5617	+ ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
4865	5618
4866	5619	return 0;
4867	5620	}
..	..	@@ -4945,6 +5698,112 @@
4945	5698	return 1;
4946	5699	}
4947	5700
	5701	+/*
	5702	+ * Sound BlasterX AE-5 Headphone Gain Controls.
	5703	+ */
	5704	+#define AE5_HEADPHONE_GAIN_MAX 3
	5705	+static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
	5706	+ struct snd_ctl_elem_info *uinfo)
	5707	+{
	5708	+ char *sfx = " Ohms)";
	5709	+ char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
	5710	+
	5711	+ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
	5712	+ uinfo->count = 1;
	5713	+ uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
	5714	+ if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
	5715	+ uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
	5716	+ sprintf(namestr, "%s %s",
	5717	+ ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
	5718	+ sfx);
	5719	+ strcpy(uinfo->value.enumerated.name, namestr);
	5720	+ return 0;
	5721	+}
	5722	+
	5723	+static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
	5724	+ struct snd_ctl_elem_value *ucontrol)
	5725	+{
	5726	+ struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	5727	+ struct ca0132_spec *spec = codec->spec;
	5728	+
	5729	+ ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
	5730	+ return 0;
	5731	+}
	5732	+
	5733	+static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
	5734	+ struct snd_ctl_elem_value *ucontrol)
	5735	+{
	5736	+ struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	5737	+ struct ca0132_spec *spec = codec->spec;
	5738	+ int sel = ucontrol->value.enumerated.item[0];
	5739	+ unsigned int items = AE5_HEADPHONE_GAIN_MAX;
	5740	+
	5741	+ if (sel >= items)
	5742	+ return 0;
	5743	+
	5744	+ codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
	5745	+ sel);
	5746	+
	5747	+ spec->ae5_headphone_gain_val = sel;
	5748	+
	5749	+ if (spec->out_enum_val == HEADPHONE_OUT)
	5750	+ ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
	5751	+
	5752	+ return 1;
	5753	+}
	5754	+
	5755	+/*
	5756	+ * Sound BlasterX AE-5 sound filter enumerated control.
	5757	+ */
	5758	+#define AE5_SOUND_FILTER_MAX 3
	5759	+
	5760	+static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
	5761	+ struct snd_ctl_elem_info *uinfo)
	5762	+{
	5763	+ char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
	5764	+
	5765	+ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
	5766	+ uinfo->count = 1;
	5767	+ uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
	5768	+ if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
	5769	+ uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
	5770	+ sprintf(namestr, "%s",
	5771	+ ae5_filter_presets[uinfo->value.enumerated.item].name);
	5772	+ strcpy(uinfo->value.enumerated.name, namestr);
	5773	+ return 0;
	5774	+}
	5775	+
	5776	+static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
	5777	+ struct snd_ctl_elem_value *ucontrol)
	5778	+{
	5779	+ struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	5780	+ struct ca0132_spec *spec = codec->spec;
	5781	+
	5782	+ ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
	5783	+ return 0;
	5784	+}
	5785	+
	5786	+static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
	5787	+ struct snd_ctl_elem_value *ucontrol)
	5788	+{
	5789	+ struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	5790	+ struct ca0132_spec *spec = codec->spec;
	5791	+ int sel = ucontrol->value.enumerated.item[0];
	5792	+ unsigned int items = AE5_SOUND_FILTER_MAX;
	5793	+
	5794	+ if (sel >= items)
	5795	+ return 0;
	5796	+
	5797	+ codec_dbg(codec, "ae5_sound_filter: %s\n",
	5798	+ ae5_filter_presets[sel].name);
	5799	+
	5800	+ spec->ae5_filter_val = sel;
	5801	+
	5802	+ ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
	5803	+ ae5_filter_presets[sel].val);
	5804	+
	5805	+ return 1;
	5806	+}
4948	5807
4949	5808	/*
4950	5809	* Input Select Control for alternative ca0132 codecs. This exists because
..	..	@@ -4982,6 +5841,13 @@
4982	5841	int sel = ucontrol->value.enumerated.item[0];
4983	5842	unsigned int items = IN_SRC_NUM_OF_INPUTS;
4984	5843
	5844	+ /*
	5845	+ * The AE-7 has no front microphone, so limit items to 2: rear mic and
	5846	+ * line-in.
	5847	+ */
	5848	+ if (ca0132_quirk(spec) == QUIRK_AE7)
	5849	+ items = 2;
	5850	+
4985	5851	if (sel >= items)
4986	5852	return 0;
4987	5853
..	..	@@ -5005,7 +5871,7 @@
5005	5871	if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5006	5872	uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5007	5873	strcpy(uinfo->value.enumerated.name,
5008		- alt_out_presets[uinfo->value.enumerated.item].name);
	5874	+ out_type_str[uinfo->value.enumerated.item]);
5009	5875	return 0;
5010	5876	}
5011	5877
..	..	@@ -5032,13 +5898,61 @@
5032	5898	return 0;
5033	5899
5034	5900	codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5035		- sel, alt_out_presets[sel].name);
	5901	+ sel, out_type_str[sel]);
5036	5902
5037	5903	spec->out_enum_val = sel;
5038	5904
5039	5905	auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5040	5906
5041	5907	if (!auto_jack)
	5908	+ ca0132_alt_select_out(codec);
	5909	+
	5910	+ return 1;
	5911	+}
	5912	+
	5913	+/* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */
	5914	+static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol,
	5915	+ struct snd_ctl_elem_info *uinfo)
	5916	+{
	5917	+ unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
	5918	+
	5919	+ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
	5920	+ uinfo->count = 1;
	5921	+ uinfo->value.enumerated.items = items;
	5922	+ if (uinfo->value.enumerated.item >= items)
	5923	+ uinfo->value.enumerated.item = items - 1;
	5924	+ strcpy(uinfo->value.enumerated.name,
	5925	+ speaker_channel_cfgs[uinfo->value.enumerated.item].name);
	5926	+ return 0;
	5927	+}
	5928	+
	5929	+static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol,
	5930	+ struct snd_ctl_elem_value *ucontrol)
	5931	+{
	5932	+ struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	5933	+ struct ca0132_spec *spec = codec->spec;
	5934	+
	5935	+ ucontrol->value.enumerated.item[0] = spec->channel_cfg_val;
	5936	+ return 0;
	5937	+}
	5938	+
	5939	+static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol,
	5940	+ struct snd_ctl_elem_value *ucontrol)
	5941	+{
	5942	+ struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
	5943	+ struct ca0132_spec *spec = codec->spec;
	5944	+ int sel = ucontrol->value.enumerated.item[0];
	5945	+ unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
	5946	+
	5947	+ if (sel >= items)
	5948	+ return 0;
	5949	+
	5950	+ codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n",
	5951	+ sel, speaker_channel_cfgs[sel].name);
	5952	+
	5953	+ spec->channel_cfg_val = sel;
	5954	+
	5955	+ if (spec->out_enum_val == SPEAKER_OUT)
5042	5956	ca0132_alt_select_out(codec);
5043	5957
5044	5958	return 1;
..	..	@@ -5265,6 +6179,21 @@
5265	6179	return 0;
5266	6180	}
5267	6181
	6182	+ if (nid == ZXR_HEADPHONE_GAIN) {
	6183	+ *valp = spec->zxr_gain_set;
	6184	+ return 0;
	6185	+ }
	6186	+
	6187	+ if (nid == SPEAKER_FULL_RANGE_FRONT \|\| nid == SPEAKER_FULL_RANGE_REAR) {
	6188	+ *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT];
	6189	+ return 0;
	6190	+ }
	6191	+
	6192	+ if (nid == BASS_REDIRECTION) {
	6193	+ *valp = spec->bass_redirection_val;
	6194	+ return 0;
	6195	+ }
	6196	+
5268	6197	return 0;
5269	6198	}
5270	6199
..	..	@@ -5321,7 +6250,7 @@
5321	6250	/* mic boost */
5322	6251	if (nid == spec->input_pins[0]) {
5323	6252	spec->cur_mic_boost = *valp;
5324		- if (spec->use_alt_functions) {
	6253	+ if (ca0132_use_alt_functions(spec)) {
5325	6254	if (spec->in_enum_val != REAR_LINE_IN)
5326	6255	changed = ca0132_mic_boost_set(codec, *valp);
5327	6256	} else {
..	..	@@ -5331,6 +6260,32 @@
5331	6260	}
5332	6261
5333	6262	goto exit;
	6263	+ }
	6264	+
	6265	+ if (nid == ZXR_HEADPHONE_GAIN) {
	6266	+ spec->zxr_gain_set = *valp;
	6267	+ if (spec->cur_out_type == HEADPHONE_OUT)
	6268	+ changed = zxr_headphone_gain_set(codec, *valp);
	6269	+ else
	6270	+ changed = 0;
	6271	+
	6272	+ goto exit;
	6273	+ }
	6274	+
	6275	+ if (nid == SPEAKER_FULL_RANGE_FRONT \|\| nid == SPEAKER_FULL_RANGE_REAR) {
	6276	+ spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp;
	6277	+ if (spec->cur_out_type == SPEAKER_OUT)
	6278	+ ca0132_alt_set_full_range_speaker(codec);
	6279	+
	6280	+ changed = 0;
	6281	+ }
	6282	+
	6283	+ if (nid == BASS_REDIRECTION) {
	6284	+ spec->bass_redirection_val = *valp;
	6285	+ if (spec->cur_out_type == SPEAKER_OUT)
	6286	+ ca0132_alt_surround_set_bass_redirection(codec, *valp);
	6287	+
	6288	+ changed = 0;
5334	6289	}
5335	6290
5336	6291	exit:
..	..	@@ -5491,7 +6446,7 @@
5491	6446	int ch = get_amp_channels(kcontrol);
5492	6447	long *valp = ucontrol->value.integer.value;
5493	6448	hda_nid_t vnid = 0;
5494		- int changed = 1;
	6449	+ int changed;
5495	6450
5496	6451	switch (nid) {
5497	6452	case 0x02:
..	..	@@ -5607,7 +6562,7 @@
5607	6562	/* If using alt_controls, add FX: prefix. But, don't add FX:
5608	6563	* prefix to OutFX or InFX enable controls.
5609	6564	*/
5610		- if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
	6565	+ if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID))
5611	6566	sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
5612	6567	else
5613	6568	sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
..	..	@@ -5674,6 +6629,81 @@
5674	6629	}
5675	6630
5676	6631	/*
	6632	+ * Add a control for selecting channel count on speaker output. Setting this
	6633	+ * allows the DSP to do bass redirection and channel upmixing on surround
	6634	+ * configurations.
	6635	+ */
	6636	+static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec)
	6637	+{
	6638	+ struct snd_kcontrol_new knew =
	6639	+ HDA_CODEC_MUTE_MONO("Surround Channel Config",
	6640	+ SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT);
	6641	+ knew.info = ca0132_alt_speaker_channel_cfg_get_info;
	6642	+ knew.get = ca0132_alt_speaker_channel_cfg_get;
	6643	+ knew.put = ca0132_alt_speaker_channel_cfg_put;
	6644	+ return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM,
	6645	+ snd_ctl_new1(&knew, codec));
	6646	+}
	6647	+
	6648	+/*
	6649	+ * Full range front stereo and rear surround switches. When these are set to
	6650	+ * full range, the lower frequencies from these channels are no longer
	6651	+ * redirected to the LFE channel.
	6652	+ */
	6653	+static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec)
	6654	+{
	6655	+ struct snd_kcontrol_new knew =
	6656	+ CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers",
	6657	+ SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT);
	6658	+
	6659	+ return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT,
	6660	+ snd_ctl_new1(&knew, codec));
	6661	+}
	6662	+
	6663	+static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec)
	6664	+{
	6665	+ struct snd_kcontrol_new knew =
	6666	+ CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers",
	6667	+ SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT);
	6668	+
	6669	+ return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR,
	6670	+ snd_ctl_new1(&knew, codec));
	6671	+}
	6672	+
	6673	+/*
	6674	+ * Bass redirection redirects audio below the crossover frequency to the LFE
	6675	+ * channel on speakers that are set as not being full-range. On configurations
	6676	+ * without an LFE channel, it does nothing. Bass redirection seems to be the
	6677	+ * replacement for X-Bass on configurations with an LFE channel.
	6678	+ */
	6679	+static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec)
	6680	+{
	6681	+ const char *namestr = "Bass Redirection Crossover";
	6682	+ struct snd_kcontrol_new knew =
	6683	+ HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0,
	6684	+ HDA_OUTPUT);
	6685	+
	6686	+ knew.tlv.c = NULL;
	6687	+ knew.info = ca0132_alt_xbass_xover_slider_info;
	6688	+ knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
	6689	+ knew.put = ca0132_alt_xbass_xover_slider_put;
	6690	+
	6691	+ return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER,
	6692	+ snd_ctl_new1(&knew, codec));
	6693	+}
	6694	+
	6695	+static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec)
	6696	+{
	6697	+ const char *namestr = "Bass Redirection";
	6698	+ struct snd_kcontrol_new knew =
	6699	+ CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1,
	6700	+ HDA_OUTPUT);
	6701	+
	6702	+ return snd_hda_ctl_add(codec, BASS_REDIRECTION,
	6703	+ snd_ctl_new1(&knew, codec));
	6704	+}
	6705	+
	6706	+/*
5677	6707	* Create an Input Source enumerated control for the alternate ca0132 codecs
5678	6708	* because the front microphone has no auto-detect, and Line-in has to be set
5679	6709	* somehow.
..	..	@@ -5708,10 +6738,54 @@
5708	6738	}
5709	6739
5710	6740	/*
5711		- * Need to create slave controls for the alternate codecs that have surround
	6741	+ * Add headphone gain enumerated control for the AE-5. This switches between
	6742	+ * three modes, low, medium, and high. When non-headphone outputs are selected,
	6743	+ * it is automatically set to high. This is the same behavior as Windows.
	6744	+ */
	6745	+static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
	6746	+{
	6747	+ struct snd_kcontrol_new knew =
	6748	+ HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
	6749	+ AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
	6750	+ knew.info = ae5_headphone_gain_info;
	6751	+ knew.get = ae5_headphone_gain_get;
	6752	+ knew.put = ae5_headphone_gain_put;
	6753	+ return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
	6754	+ snd_ctl_new1(&knew, codec));
	6755	+}
	6756	+
	6757	+/*
	6758	+ * Add sound filter enumerated control for the AE-5. This adds three different
	6759	+ * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
	6760	+ * read into it, it changes the DAC's interpolation filter.
	6761	+ */
	6762	+static int ae5_add_sound_filter_enum(struct hda_codec *codec)
	6763	+{
	6764	+ struct snd_kcontrol_new knew =
	6765	+ HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
	6766	+ AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
	6767	+ knew.info = ae5_sound_filter_info;
	6768	+ knew.get = ae5_sound_filter_get;
	6769	+ knew.put = ae5_sound_filter_put;
	6770	+ return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
	6771	+ snd_ctl_new1(&knew, codec));
	6772	+}
	6773	+
	6774	+static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
	6775	+{
	6776	+ struct snd_kcontrol_new knew =
	6777	+ CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
	6778	+ ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
	6779	+
	6780	+ return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
	6781	+ snd_ctl_new1(&knew, codec));
	6782	+}
	6783	+
	6784	+/*
	6785	+ * Need to create follower controls for the alternate codecs that have surround
5712	6786	* capabilities.
5713	6787	*/
5714		-static const char * const ca0132_alt_slave_pfxs[] = {
	6788	+static const char * const ca0132_alt_follower_pfxs[] = {
5715	6789	"Front", "Surround", "Center", "LFE", NULL,
5716	6790	};
5717	6791
..	..	@@ -5839,18 +6913,19 @@
5839	6913	if (err < 0)
5840	6914	return err;
5841	6915	}
5842		- /* Setup vmaster with surround slaves for desktop ca0132 devices */
5843		- if (spec->use_alt_functions) {
	6916	+ /* Setup vmaster with surround followers for desktop ca0132 devices */
	6917	+ if (ca0132_use_alt_functions(spec)) {
5844	6918	snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
5845	6919	spec->tlv);
5846	6920	snd_hda_add_vmaster(codec, "Master Playback Volume",
5847		- spec->tlv, ca0132_alt_slave_pfxs,
	6921	+ spec->tlv, ca0132_alt_follower_pfxs,
5848	6922	"Playback Volume");
5849	6923	err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
5850		- NULL, ca0132_alt_slave_pfxs,
	6924	+ NULL, ca0132_alt_follower_pfxs,
5851	6925	"Playback Switch",
5852	6926	true, &spec->vmaster_mute.sw_kctl);
5853		-
	6927	+ if (err < 0)
	6928	+ return err;
5854	6929	}
5855	6930
5856	6931	/* Add in and out effects controls.
..	..	@@ -5859,7 +6934,7 @@
5859	6934	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5860	6935	for (i = 0; i < num_fx; i++) {
5861	6936	/* Desktop cards break if Echo Cancellation is used. */
5862		- if (spec->use_pci_mmio) {
	6937	+ if (ca0132_use_pci_mmio(spec)) {
5863	6938	if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
5864	6939	OUT_EFFECTS_COUNT))
5865	6940	continue;
..	..	@@ -5876,9 +6951,15 @@
5876	6951	* EQ presets, and Smart Volume presets. Also, change names to add FX
5877	6952	* prefix, and change PlayEnhancement and CrystalVoice to match.
5878	6953	*/
5879		- if (spec->use_alt_controls) {
5880		- ca0132_alt_add_svm_enum(codec);
5881		- add_ca0132_alt_eq_presets(codec);
	6954	+ if (ca0132_use_alt_controls(spec)) {
	6955	+ err = ca0132_alt_add_svm_enum(codec);
	6956	+ if (err < 0)
	6957	+ return err;
	6958	+
	6959	+ err = add_ca0132_alt_eq_presets(codec);
	6960	+ if (err < 0)
	6961	+ return err;
	6962	+
5882	6963	err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5883	6964	"Enable OutFX", 0);
5884	6965	if (err < 0)
..	..	@@ -5915,18 +6996,67 @@
5915	6996	if (err < 0)
5916	6997	return err;
5917	6998	}
5918		- add_voicefx(codec);
	6999	+ err = add_voicefx(codec);
	7000	+ if (err < 0)
	7001	+ return err;
5919	7002
5920	7003	/*
5921	7004	* If the codec uses alt_functions, you need the enumerated controls
5922	7005	* to select the new outputs and inputs, plus add the new mic boost
5923	7006	* setting control.
5924	7007	*/
5925		- if (spec->use_alt_functions) {
5926		- ca0132_alt_add_output_enum(codec);
5927		- ca0132_alt_add_input_enum(codec);
5928		- ca0132_alt_add_mic_boost_enum(codec);
	7008	+ if (ca0132_use_alt_functions(spec)) {
	7009	+ err = ca0132_alt_add_output_enum(codec);
	7010	+ if (err < 0)
	7011	+ return err;
	7012	+ err = ca0132_alt_add_speaker_channel_cfg_enum(codec);
	7013	+ if (err < 0)
	7014	+ return err;
	7015	+ err = ca0132_alt_add_front_full_range_switch(codec);
	7016	+ if (err < 0)
	7017	+ return err;
	7018	+ err = ca0132_alt_add_rear_full_range_switch(codec);
	7019	+ if (err < 0)
	7020	+ return err;
	7021	+ err = ca0132_alt_add_bass_redirection_crossover(codec);
	7022	+ if (err < 0)
	7023	+ return err;
	7024	+ err = ca0132_alt_add_bass_redirection_switch(codec);
	7025	+ if (err < 0)
	7026	+ return err;
	7027	+ err = ca0132_alt_add_mic_boost_enum(codec);
	7028	+ if (err < 0)
	7029	+ return err;
	7030	+ /*
	7031	+ * ZxR only has microphone input, there is no front panel
	7032	+ * header on the card, and aux-in is handled by the DBPro board.
	7033	+ */
	7034	+ if (ca0132_quirk(spec) != QUIRK_ZXR) {
	7035	+ err = ca0132_alt_add_input_enum(codec);
	7036	+ if (err < 0)
	7037	+ return err;
	7038	+ }
5929	7039	}
	7040	+
	7041	+ switch (ca0132_quirk(spec)) {
	7042	+ case QUIRK_AE5:
	7043	+ case QUIRK_AE7:
	7044	+ err = ae5_add_headphone_gain_enum(codec);
	7045	+ if (err < 0)
	7046	+ return err;
	7047	+ err = ae5_add_sound_filter_enum(codec);
	7048	+ if (err < 0)
	7049	+ return err;
	7050	+ break;
	7051	+ case QUIRK_ZXR:
	7052	+ err = zxr_add_headphone_gain_switch(codec);
	7053	+ if (err < 0)
	7054	+ return err;
	7055	+ break;
	7056	+ default:
	7057	+ break;
	7058	+ }
	7059	+
5930	7060	#ifdef ENABLE_TUNING_CONTROLS
5931	7061	add_tuning_ctls(codec);
5932	7062	#endif
..	..	@@ -5952,8 +7082,29 @@
5952	7082	return err;
5953	7083	}
5954	7084
5955		- if (spec->use_alt_functions)
	7085	+ if (ca0132_use_alt_functions(spec))
5956	7086	ca0132_alt_add_chmap_ctls(codec);
	7087	+
	7088	+ return 0;
	7089	+}
	7090	+
	7091	+static int dbpro_build_controls(struct hda_codec *codec)
	7092	+{
	7093	+ struct ca0132_spec *spec = codec->spec;
	7094	+ int err = 0;
	7095	+
	7096	+ if (spec->dig_out) {
	7097	+ err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
	7098	+ spec->dig_out);
	7099	+ if (err < 0)
	7100	+ return err;
	7101	+ }
	7102	+
	7103	+ if (spec->dig_in) {
	7104	+ err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
	7105	+ if (err < 0)
	7106	+ return err;
	7107	+ }
5957	7108
5958	7109	return 0;
5959	7110	}
..	..	@@ -6009,7 +7160,7 @@
6009	7160	info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6010	7161	if (!info)
6011	7162	return -ENOMEM;
6012		- if (spec->use_alt_functions) {
	7163	+ if (ca0132_use_alt_functions(spec)) {
6013	7164	info->own_chmap = true;
6014	7165	info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6015	7166	= ca0132_alt_chmaps;
..	..	@@ -6023,7 +7174,7 @@
6023	7174	info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
6024	7175
6025	7176	/* With the DSP enabled, desktops don't use this ADC. */
6026		- if (!spec->use_alt_functions) {
	7177	+ if (!ca0132_use_alt_functions(spec)) {
6027	7178	info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6028	7179	if (!info)
6029	7180	return -ENOMEM;
..	..	@@ -6039,6 +7190,40 @@
6039	7190	info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6040	7191	info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6041	7192	info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
	7193	+
	7194	+ if (!spec->dig_out && !spec->dig_in)
	7195	+ return 0;
	7196	+
	7197	+ info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
	7198	+ if (!info)
	7199	+ return -ENOMEM;
	7200	+ info->pcm_type = HDA_PCM_TYPE_SPDIF;
	7201	+ if (spec->dig_out) {
	7202	+ info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
	7203	+ ca0132_pcm_digital_playback;
	7204	+ info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
	7205	+ }
	7206	+ if (spec->dig_in) {
	7207	+ info->stream[SNDRV_PCM_STREAM_CAPTURE] =
	7208	+ ca0132_pcm_digital_capture;
	7209	+ info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
	7210	+ }
	7211	+
	7212	+ return 0;
	7213	+}
	7214	+
	7215	+static int dbpro_build_pcms(struct hda_codec *codec)
	7216	+{
	7217	+ struct ca0132_spec *spec = codec->spec;
	7218	+ struct hda_pcm *info;
	7219	+
	7220	+ info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
	7221	+ if (!info)
	7222	+ return -ENOMEM;
	7223	+ info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
	7224	+ info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
	7225	+ info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
	7226	+
6042	7227
6043	7228	if (!spec->dig_out && !spec->dig_in)
6044	7229	return 0;
..	..	@@ -6187,7 +7372,7 @@
6187	7372	* Bit 6: set to select Data2, clear for Data1
6188	7373	* Bit 7: set to enable DMic, clear for AMic
6189	7374	*/
6190		- if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
	7375	+ if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4)
6191	7376	val = 0x33;
6192	7377	else
6193	7378	val = 0x23;
..	..	@@ -6241,69 +7426,110 @@
6241	7426	}
6242	7427
6243	7428	/*
6244		- * Recon3D r3d_setup_defaults sub functions.
	7429	+ * Default speaker tuning values setup for alternative codecs.
6245	7430	*/
	7431	+static const unsigned int sbz_default_delay_values[] = {
	7432	+ /* Non-zero values are floating point 0.000198. */
	7433	+ 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000
	7434	+};
6246	7435
6247		-static void r3d_dsp_scp_startup(struct hda_codec *codec)
	7436	+static const unsigned int zxr_default_delay_values[] = {
	7437	+ /* Non-zero values are floating point 0.000220. */
	7438	+ 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd
	7439	+};
	7440	+
	7441	+static const unsigned int ae5_default_delay_values[] = {
	7442	+ /* Non-zero values are floating point 0.000100. */
	7443	+ 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717
	7444	+};
	7445	+
	7446	+/*
	7447	+ * If we never change these, probably only need them on initialization.
	7448	+ */
	7449	+static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec)
6248	7450	{
6249		- unsigned int tmp;
	7451	+ struct ca0132_spec *spec = codec->spec;
	7452	+ unsigned int i, tmp, start_req, end_req;
	7453	+ const unsigned int *values;
6250	7454
6251		- tmp = 0x00000000;
6252		- dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
	7455	+ switch (ca0132_quirk(spec)) {
	7456	+ case QUIRK_SBZ:
	7457	+ values = sbz_default_delay_values;
	7458	+ break;
	7459	+ case QUIRK_ZXR:
	7460	+ values = zxr_default_delay_values;
	7461	+ break;
	7462	+ case QUIRK_AE5:
	7463	+ case QUIRK_AE7:
	7464	+ values = ae5_default_delay_values;
	7465	+ break;
	7466	+ default:
	7467	+ values = sbz_default_delay_values;
	7468	+ break;
	7469	+ }
6253	7470
6254		- tmp = 0x00000001;
6255		- dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6256		-
6257		- tmp = 0x00000004;
6258		- dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6259		-
6260		- tmp = 0x00000005;
6261		- dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6262		-
6263		- tmp = 0x00000000;
6264		- dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6265		-
6266		-}
6267		-
6268		-static void r3d_dsp_initial_mic_setup(struct hda_codec *codec)
6269		-{
6270		- unsigned int tmp;
6271		-
6272		- /* Mic 1 Setup */
6273		- chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6274		- chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6275		- /* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */
6276		- chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6277		- tmp = FLOAT_ONE;
6278		- dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6279		-
6280		- /* Mic 2 Setup, even though it isn't connected on SBZ */
6281		- chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6282		- chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6283		- chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6284	7471	tmp = FLOAT_ZERO;
6285		- dspio_set_uint_param(codec, 0x80, 0x01, tmp);
	7472	+ dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp);
	7473	+
	7474	+ start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL;
	7475	+ end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL;
	7476	+ for (i = start_req; i < end_req + 1; i++)
	7477	+ dspio_set_uint_param(codec, 0x96, i, tmp);
	7478	+
	7479	+ start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT;
	7480	+ end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT;
	7481	+ for (i = start_req; i < end_req + 1; i++)
	7482	+ dspio_set_uint_param(codec, 0x96, i, tmp);
	7483	+
	7484	+
	7485	+ for (i = 0; i < 6; i++)
	7486	+ dspio_set_uint_param(codec, 0x96,
	7487	+ SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]);
6286	7488	}
6287	7489
6288	7490	/*
6289		- * Initialize Sound Blaster Z analog microphones.
	7491	+ * Creates a dummy stream to bind the output to. This seems to have to be done
	7492	+ * after changing the main outputs source and destination streams.
6290	7493	*/
6291		-static void sbz_init_analog_mics(struct hda_codec *codec)
	7494	+static void ca0132_alt_create_dummy_stream(struct hda_codec *codec)
6292	7495	{
	7496	+ struct ca0132_spec *spec = codec->spec;
	7497	+ unsigned int stream_format;
	7498	+
	7499	+ stream_format = snd_hdac_calc_stream_format(48000, 2,
	7500	+ SNDRV_PCM_FORMAT_S32_LE, 32, 0);
	7501	+
	7502	+ snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
	7503	+ 0, stream_format);
	7504	+
	7505	+ snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
	7506	+}
	7507	+
	7508	+/*
	7509	+ * Initialize mic for non-chromebook ca0132 implementations.
	7510	+ */
	7511	+static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
	7512	+{
	7513	+ struct ca0132_spec *spec = codec->spec;
6293	7514	unsigned int tmp;
6294	7515
6295	7516	/* Mic 1 Setup */
6296	7517	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6297	7518	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6298		- tmp = FLOAT_THREE;
	7519	+ if (ca0132_quirk(spec) == QUIRK_R3DI) {
	7520	+ chipio_set_conn_rate(codec, 0x0F, SR_96_000);
	7521	+ tmp = FLOAT_ONE;
	7522	+ } else
	7523	+ tmp = FLOAT_THREE;
6299	7524	dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6300	7525
6301		- /* Mic 2 Setup, even though it isn't connected on SBZ */
	7526	+ /* Mic 2 setup (not present on desktop cards) */
6302	7527	chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6303	7528	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
	7529	+ if (ca0132_quirk(spec) == QUIRK_R3DI)
	7530	+ chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6304	7531	tmp = FLOAT_ZERO;
6305	7532	dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6306		-
6307	7533	}
6308	7534
6309	7535	/*
..	..	@@ -6336,7 +7562,6 @@
6336	7562	codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6337	7563
6338	7564	mutex_unlock(&spec->chipio_mutex);
6339		-
6340	7565	}
6341	7566
6342	7567	/*
..	..	@@ -6363,19 +7588,29 @@
6363	7588	chipio_set_stream_channels(codec, 0x0C, 6);
6364	7589	chipio_set_stream_control(codec, 0x0C, 1);
6365	7590	/* No clue what these control */
6366		- chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6367		- chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6368		- chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6369		- chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6370		- chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6371		- chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6372		- chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6373		- chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6374		- chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6375		- chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6376		- chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6377		- chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6378		-
	7591	+ if (ca0132_quirk(spec) == QUIRK_SBZ) {
	7592	+ chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
	7593	+ chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
	7594	+ chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
	7595	+ chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
	7596	+ chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
	7597	+ chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
	7598	+ chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
	7599	+ chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
	7600	+ chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
	7601	+ chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
	7602	+ chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
	7603	+ chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
	7604	+ } else if (ca0132_quirk(spec) == QUIRK_ZXR) {
	7605	+ chipio_write_no_mutex(codec, 0x190038, 0x000140c2);
	7606	+ chipio_write_no_mutex(codec, 0x19003c, 0x000141c3);
	7607	+ chipio_write_no_mutex(codec, 0x190040, 0x000150c4);
	7608	+ chipio_write_no_mutex(codec, 0x190044, 0x000151c5);
	7609	+ chipio_write_no_mutex(codec, 0x190050, 0x000142c8);
	7610	+ chipio_write_no_mutex(codec, 0x190054, 0x000143c9);
	7611	+ chipio_write_no_mutex(codec, 0x190058, 0x000152ca);
	7612	+ chipio_write_no_mutex(codec, 0x19005c, 0x000153cb);
	7613	+ }
6379	7614	chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6380	7615
6381	7616	codec_dbg(codec, "Startup Data exited, mutex released.\n");
..	..	@@ -6383,35 +7618,59 @@
6383	7618	}
6384	7619
6385	7620	/*
6386		- * Sound Blaster Z uses these after DSP is loaded. Weird SCP commands
6387		- * without a 0x20 source like normal.
	7621	+ * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is
	7622	+ * done after the DSP is loaded.
6388	7623	*/
6389		-static void sbz_dsp_scp_startup(struct hda_codec *codec)
	7624	+static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec)
6390	7625	{
6391		- unsigned int tmp;
	7626	+ struct ca0132_spec *spec = codec->spec;
	7627	+ unsigned int tmp, i;
6392	7628
6393		- tmp = 0x00000003;
6394		- dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6395		-
6396		- tmp = 0x00000000;
6397		- dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6398		-
6399		- tmp = 0x00000001;
6400		- dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6401		-
6402		- tmp = 0x00000004;
6403		- dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6404		-
6405		- tmp = 0x00000005;
6406		- dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6407		-
6408		- tmp = 0x00000000;
6409		- dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6410		-
	7629	+ /*
	7630	+ * Gotta run these twice, or else mic works inconsistently. Not clear
	7631	+ * why this is, but multiple tests have confirmed it.
	7632	+ */
	7633	+ for (i = 0; i < 2; i++) {
	7634	+ switch (ca0132_quirk(spec)) {
	7635	+ case QUIRK_SBZ:
	7636	+ case QUIRK_AE5:
	7637	+ case QUIRK_AE7:
	7638	+ tmp = 0x00000003;
	7639	+ dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
	7640	+ tmp = 0x00000000;
	7641	+ dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
	7642	+ tmp = 0x00000001;
	7643	+ dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
	7644	+ tmp = 0x00000004;
	7645	+ dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
	7646	+ tmp = 0x00000005;
	7647	+ dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
	7648	+ tmp = 0x00000000;
	7649	+ dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
	7650	+ break;
	7651	+ case QUIRK_R3D:
	7652	+ case QUIRK_R3DI:
	7653	+ tmp = 0x00000000;
	7654	+ dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
	7655	+ tmp = 0x00000001;
	7656	+ dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
	7657	+ tmp = 0x00000004;
	7658	+ dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
	7659	+ tmp = 0x00000005;
	7660	+ dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
	7661	+ tmp = 0x00000000;
	7662	+ dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
	7663	+ break;
	7664	+ default:
	7665	+ break;
	7666	+ }
	7667	+ msleep(100);
	7668	+ }
6411	7669	}
6412	7670
6413		-static void sbz_dsp_initial_mic_setup(struct hda_codec *codec)
	7671	+static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
6414	7672	{
	7673	+ struct ca0132_spec *spec = codec->spec;
6415	7674	unsigned int tmp;
6416	7675
6417	7676	chipio_set_stream_control(codec, 0x03, 0);
..	..	@@ -6426,8 +7685,369 @@
6426	7685	chipio_set_stream_control(codec, 0x03, 1);
6427	7686	chipio_set_stream_control(codec, 0x04, 1);
6428	7687
6429		- chipio_write(codec, 0x18b098, 0x0000000c);
6430		- chipio_write(codec, 0x18b09C, 0x0000000c);
	7688	+ switch (ca0132_quirk(spec)) {
	7689	+ case QUIRK_SBZ:
	7690	+ chipio_write(codec, 0x18b098, 0x0000000c);
	7691	+ chipio_write(codec, 0x18b09C, 0x0000000c);
	7692	+ break;
	7693	+ case QUIRK_AE5:
	7694	+ chipio_write(codec, 0x18b098, 0x0000000c);
	7695	+ chipio_write(codec, 0x18b09c, 0x0000004c);
	7696	+ break;
	7697	+ default:
	7698	+ break;
	7699	+ }
	7700	+}
	7701	+
	7702	+static void ae5_post_dsp_register_set(struct hda_codec *codec)
	7703	+{
	7704	+ struct ca0132_spec *spec = codec->spec;
	7705	+
	7706	+ chipio_8051_write_direct(codec, 0x93, 0x10);
	7707	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7708	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
	7709	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7710	+ VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
	7711	+
	7712	+ writeb(0xff, spec->mem_base + 0x304);
	7713	+ writeb(0xff, spec->mem_base + 0x304);
	7714	+ writeb(0xff, spec->mem_base + 0x304);
	7715	+ writeb(0xff, spec->mem_base + 0x304);
	7716	+ writeb(0x00, spec->mem_base + 0x100);
	7717	+ writeb(0xff, spec->mem_base + 0x304);
	7718	+ writeb(0x00, spec->mem_base + 0x100);
	7719	+ writeb(0xff, spec->mem_base + 0x304);
	7720	+ writeb(0x00, spec->mem_base + 0x100);
	7721	+ writeb(0xff, spec->mem_base + 0x304);
	7722	+ writeb(0x00, spec->mem_base + 0x100);
	7723	+ writeb(0xff, spec->mem_base + 0x304);
	7724	+
	7725	+ ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
	7726	+ ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
	7727	+ ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
	7728	+}
	7729	+
	7730	+static void ae5_post_dsp_param_setup(struct hda_codec *codec)
	7731	+{
	7732	+ /*
	7733	+ * Param3 in the 8051's memory is represented by the ascii string 'mch'
	7734	+ * which seems to be 'multichannel'. This is also mentioned in the
	7735	+ * AE-5's registry values in Windows.
	7736	+ */
	7737	+ chipio_set_control_param(codec, 3, 0);
	7738	+ /*
	7739	+ * I believe ASI is 'audio serial interface' and that it's used to
	7740	+ * change colors on the external LED strip connected to the AE-5.
	7741	+ */
	7742	+ chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
	7743	+
	7744	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
	7745	+ chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
	7746	+
	7747	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7748	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
	7749	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7750	+ VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
	7751	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7752	+ VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
	7753	+}
	7754	+
	7755	+static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
	7756	+{
	7757	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7758	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
	7759	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7760	+ VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
	7761	+
	7762	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7763	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
	7764	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7765	+ VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
	7766	+
	7767	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7768	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
	7769	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7770	+ VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
	7771	+
	7772	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7773	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
	7774	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7775	+ VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
	7776	+
	7777	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7778	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
	7779	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7780	+ VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
	7781	+}
	7782	+
	7783	+static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
	7784	+{
	7785	+ struct ca0132_spec *spec = codec->spec;
	7786	+
	7787	+ mutex_lock(&spec->chipio_mutex);
	7788	+
	7789	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
	7790	+
	7791	+ chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
	7792	+
	7793	+ chipio_set_stream_channels(codec, 0x0C, 6);
	7794	+ chipio_set_stream_control(codec, 0x0C, 1);
	7795	+
	7796	+ chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
	7797	+
	7798	+ chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
	7799	+ chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
	7800	+ chipio_set_stream_channels(codec, 0x18, 6);
	7801	+ chipio_set_stream_control(codec, 0x18, 1);
	7802	+
	7803	+ chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
	7804	+
	7805	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7806	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
	7807	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7808	+ VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
	7809	+
	7810	+ ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
	7811	+
	7812	+ mutex_unlock(&spec->chipio_mutex);
	7813	+}
	7814	+
	7815	+static void ae5_post_dsp_startup_data(struct hda_codec *codec)
	7816	+{
	7817	+ struct ca0132_spec *spec = codec->spec;
	7818	+
	7819	+ mutex_lock(&spec->chipio_mutex);
	7820	+
	7821	+ chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
	7822	+ chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
	7823	+ chipio_write_no_mutex(codec, 0x189024, 0x00014004);
	7824	+ chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
	7825	+
	7826	+ ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
	7827	+ chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
	7828	+ ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
	7829	+ ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
	7830	+ ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
	7831	+ ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
	7832	+ ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
	7833	+ ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
	7834	+ ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
	7835	+ ca0113_mmio_gpio_set(codec, 0, true);
	7836	+ ca0113_mmio_gpio_set(codec, 1, true);
	7837	+ ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
	7838	+
	7839	+ chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
	7840	+
	7841	+ ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
	7842	+ ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
	7843	+
	7844	+ mutex_unlock(&spec->chipio_mutex);
	7845	+}
	7846	+
	7847	+static const unsigned int ae7_port_set_data[] = {
	7848	+ 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 0x0001e2c4, 0x0001e3c5,
	7849	+ 0x0001e8c6, 0x0001e9c7, 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb
	7850	+};
	7851	+
	7852	+static void ae7_post_dsp_setup_ports(struct hda_codec *codec)
	7853	+{
	7854	+ struct ca0132_spec *spec = codec->spec;
	7855	+ unsigned int i, count, addr;
	7856	+
	7857	+ mutex_lock(&spec->chipio_mutex);
	7858	+
	7859	+ chipio_set_stream_channels(codec, 0x0c, 6);
	7860	+ chipio_set_stream_control(codec, 0x0c, 1);
	7861	+
	7862	+ count = ARRAY_SIZE(ae7_port_set_data);
	7863	+ addr = 0x190030;
	7864	+ for (i = 0; i < count; i++) {
	7865	+ chipio_write_no_mutex(codec, addr, ae7_port_set_data[i]);
	7866	+
	7867	+ /* Addresses are incremented by 4-bytes. */
	7868	+ addr += 0x04;
	7869	+ }
	7870	+
	7871	+ /*
	7872	+ * Port setting always ends with a write of 0x1 to address 0x19042c.
	7873	+ */
	7874	+ chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
	7875	+
	7876	+ ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
	7877	+ ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
	7878	+ ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00);
	7879	+ ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00);
	7880	+ ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff);
	7881	+ ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff);
	7882	+ ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff);
	7883	+ ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f);
	7884	+
	7885	+ mutex_unlock(&spec->chipio_mutex);
	7886	+}
	7887	+
	7888	+static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec)
	7889	+{
	7890	+ struct ca0132_spec *spec = codec->spec;
	7891	+
	7892	+ mutex_lock(&spec->chipio_mutex);
	7893	+
	7894	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
	7895	+ ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
	7896	+
	7897	+ chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
	7898	+ chipio_set_stream_channels(codec, 0x0c, 6);
	7899	+ chipio_set_stream_control(codec, 0x0c, 1);
	7900	+
	7901	+ chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
	7902	+ chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
	7903	+
	7904	+ chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
	7905	+ chipio_set_stream_channels(codec, 0x18, 6);
	7906	+ chipio_set_stream_control(codec, 0x18, 1);
	7907	+
	7908	+ chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
	7909	+
	7910	+ mutex_unlock(&spec->chipio_mutex);
	7911	+}
	7912	+
	7913	+static void ae7_post_dsp_pll_setup(struct hda_codec *codec)
	7914	+{
	7915	+ static const unsigned int addr[] = {
	7916	+ 0x41, 0x45, 0x40, 0x43, 0x51
	7917	+ };
	7918	+ static const unsigned int data[] = {
	7919	+ 0xc8, 0xcc, 0xcb, 0xc7, 0x8d
	7920	+ };
	7921	+ unsigned int i;
	7922	+
	7923	+ for (i = 0; i < ARRAY_SIZE(addr); i++) {
	7924	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7925	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, addr[i]);
	7926	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7927	+ VENDOR_CHIPIO_PLL_PMU_WRITE, data[i]);
	7928	+ }
	7929	+}
	7930	+
	7931	+static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec)
	7932	+{
	7933	+ struct ca0132_spec *spec = codec->spec;
	7934	+ static const unsigned int target[] = {
	7935	+ 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14
	7936	+ };
	7937	+ static const unsigned int data[] = {
	7938	+ 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f
	7939	+ };
	7940	+ unsigned int i;
	7941	+
	7942	+ mutex_lock(&spec->chipio_mutex);
	7943	+
	7944	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7945	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
	7946	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	7947	+ VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
	7948	+
	7949	+ chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
	7950	+ chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
	7951	+ chipio_write_no_mutex(codec, 0x189024, 0x00014004);
	7952	+ chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
	7953	+
	7954	+ ae7_post_dsp_pll_setup(codec);
	7955	+ chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
	7956	+
	7957	+ for (i = 0; i < ARRAY_SIZE(target); i++)
	7958	+ ca0113_mmio_command_set(codec, 0x48, target[i], data[i]);
	7959	+
	7960	+ ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
	7961	+ ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
	7962	+ ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
	7963	+
	7964	+ chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56);
	7965	+ chipio_set_stream_channels(codec, 0x21, 2);
	7966	+ chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000);
	7967	+
	7968	+ chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09);
	7969	+ /*
	7970	+ * In the 8051's memory, this param is referred to as 'n2sid', which I
	7971	+ * believe is 'node to streamID'. It seems to be a way to assign a
	7972	+ * stream to a given HDA node.
	7973	+ */
	7974	+ chipio_set_control_param_no_mutex(codec, 0x20, 0x21);
	7975	+
	7976	+ chipio_write_no_mutex(codec, 0x18b038, 0x00000088);
	7977	+
	7978	+ /*
	7979	+ * Now, at this point on Windows, an actual stream is setup and
	7980	+ * seemingly sends data to the HDA node 0x09, which is the digital
	7981	+ * audio input node. This is left out here, because obviously I don't
	7982	+ * know what data is being sent. Interestingly, the AE-5 seems to go
	7983	+ * through the motions of getting here and never actually takes this
	7984	+ * step, but the AE-7 does.
	7985	+ */
	7986	+
	7987	+ ca0113_mmio_gpio_set(codec, 0, 1);
	7988	+ ca0113_mmio_gpio_set(codec, 1, 1);
	7989	+
	7990	+ ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
	7991	+ chipio_write_no_mutex(codec, 0x18b03c, 0x00000000);
	7992	+ ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
	7993	+ ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
	7994	+
	7995	+ chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
	7996	+ chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
	7997	+
	7998	+ chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
	7999	+ chipio_set_stream_channels(codec, 0x18, 6);
	8000	+
	8001	+ /*
	8002	+ * Runs again, this has been repeated a few times, but I'm just
	8003	+ * following what the Windows driver does.
	8004	+ */
	8005	+ ae7_post_dsp_pll_setup(codec);
	8006	+ chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
	8007	+
	8008	+ mutex_unlock(&spec->chipio_mutex);
	8009	+}
	8010	+
	8011	+/*
	8012	+ * The Windows driver has commands that seem to setup ASI, which I believe to
	8013	+ * be some sort of audio serial interface. My current speculation is that it's
	8014	+ * related to communicating with the new DAC.
	8015	+ */
	8016	+static void ae7_post_dsp_asi_setup(struct hda_codec *codec)
	8017	+{
	8018	+ chipio_8051_write_direct(codec, 0x93, 0x10);
	8019	+
	8020	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	8021	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
	8022	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	8023	+ VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
	8024	+
	8025	+ ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
	8026	+ ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
	8027	+
	8028	+ chipio_set_control_param(codec, 3, 3);
	8029	+ chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
	8030	+
	8031	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
	8032	+ chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
	8033	+ snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);
	8034	+
	8035	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	8036	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
	8037	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	8038	+ VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
	8039	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	8040	+ VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
	8041	+
	8042	+ ae7_post_dsp_pll_setup(codec);
	8043	+ ae7_post_dsp_asi_stream_setup(codec);
	8044	+
	8045	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	8046	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
	8047	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	8048	+ VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
	8049	+
	8050	+ ae7_post_dsp_asi_setup_ports(codec);
6431	8051	}
6432	8052
6433	8053	/*
..	..	@@ -6488,9 +8108,8 @@
6488	8108	if (spec->dsp_state != DSP_DOWNLOADED)
6489	8109	return;
6490	8110
6491		- r3d_dsp_scp_startup(codec);
6492		-
6493		- r3d_dsp_initial_mic_setup(codec);
	8111	+ ca0132_alt_dsp_scp_startup(codec);
	8112	+ ca0132_alt_init_analog_mics(codec);
6494	8113
6495	8114	/remove DSP headroom/
6496	8115	tmp = FLOAT_ZERO;
..	..	@@ -6504,8 +8123,14 @@
6504	8123	/* Set speaker source? */
6505	8124	dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6506	8125
6507		- if (spec->quirk == QUIRK_R3DI)
	8126	+ if (ca0132_quirk(spec) == QUIRK_R3DI)
6508	8127	r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
	8128	+
	8129	+ /* Disable mute on Center/LFE. */
	8130	+ if (ca0132_quirk(spec) == QUIRK_R3D) {
	8131	+ ca0113_mmio_gpio_set(codec, 2, false);
	8132	+ ca0113_mmio_gpio_set(codec, 4, true);
	8133	+ }
6509	8134
6510	8135	/* Setup effect defaults */
6511	8136	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
..	..	@@ -6526,19 +8151,16 @@
6526	8151	static void sbz_setup_defaults(struct hda_codec *codec)
6527	8152	{
6528	8153	struct ca0132_spec *spec = codec->spec;
6529		- unsigned int tmp, stream_format;
	8154	+ unsigned int tmp;
6530	8155	int num_fx;
6531	8156	int idx, i;
6532	8157
6533	8158	if (spec->dsp_state != DSP_DOWNLOADED)
6534	8159	return;
6535	8160
6536		- sbz_dsp_scp_startup(codec);
6537		-
6538		- sbz_init_analog_mics(codec);
6539		-
	8161	+ ca0132_alt_dsp_scp_startup(codec);
	8162	+ ca0132_alt_init_analog_mics(codec);
6540	8163	sbz_connect_streams(codec);
6541		-
6542	8164	sbz_chipio_startup_data(codec);
6543	8165
6544	8166	chipio_set_stream_control(codec, 0x03, 1);
..	..	@@ -6564,8 +8186,7 @@
6564	8186	/* Set speaker source? */
6565	8187	dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6566	8188
6567		- sbz_dsp_initial_mic_setup(codec);
6568		-
	8189	+ ca0132_alt_dsp_initial_mic_setup(codec);
6569	8190
6570	8191	/* out, in effects + voicefx */
6571	8192	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
..	..	@@ -6578,23 +8199,163 @@
6578	8199	}
6579	8200	}
6580	8201
	8202	+ ca0132_alt_init_speaker_tuning(codec);
	8203	+
	8204	+ ca0132_alt_create_dummy_stream(codec);
	8205	+}
	8206	+
	8207	+/*
	8208	+ * Setup default parameters for the Sound BlasterX AE-5 DSP.
	8209	+ */
	8210	+static void ae5_setup_defaults(struct hda_codec *codec)
	8211	+{
	8212	+ struct ca0132_spec *spec = codec->spec;
	8213	+ unsigned int tmp;
	8214	+ int num_fx;
	8215	+ int idx, i;
	8216	+
	8217	+ if (spec->dsp_state != DSP_DOWNLOADED)
	8218	+ return;
	8219	+
	8220	+ ca0132_alt_dsp_scp_startup(codec);
	8221	+ ca0132_alt_init_analog_mics(codec);
	8222	+ chipio_set_stream_control(codec, 0x03, 1);
	8223	+ chipio_set_stream_control(codec, 0x04, 1);
	8224	+
	8225	+ /* New, unknown SCP req's */
	8226	+ tmp = FLOAT_ZERO;
	8227	+ dspio_set_uint_param(codec, 0x96, 0x29, tmp);
	8228	+ dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
	8229	+ dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
	8230	+ dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
	8231	+
	8232	+ ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
	8233	+ ca0113_mmio_gpio_set(codec, 0, false);
	8234	+ ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
	8235	+
	8236	+ /* Internal loopback off */
	8237	+ tmp = FLOAT_ONE;
	8238	+ dspio_set_uint_param(codec, 0x37, 0x08, tmp);
	8239	+ dspio_set_uint_param(codec, 0x37, 0x10, tmp);
	8240	+
	8241	+ /remove DSP headroom/
	8242	+ tmp = FLOAT_ZERO;
	8243	+ dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
	8244	+
	8245	+ /* set WUH source */
	8246	+ tmp = FLOAT_TWO;
	8247	+ dspio_set_uint_param(codec, 0x31, 0x00, tmp);
	8248	+ chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
	8249	+
	8250	+ /* Set speaker source? */
	8251	+ dspio_set_uint_param(codec, 0x32, 0x00, tmp);
	8252	+
	8253	+ ca0132_alt_dsp_initial_mic_setup(codec);
	8254	+ ae5_post_dsp_register_set(codec);
	8255	+ ae5_post_dsp_param_setup(codec);
	8256	+ ae5_post_dsp_pll_setup(codec);
	8257	+ ae5_post_dsp_stream_setup(codec);
	8258	+ ae5_post_dsp_startup_data(codec);
	8259	+
	8260	+ /* out, in effects + voicefx */
	8261	+ num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
	8262	+ for (idx = 0; idx < num_fx; idx++) {
	8263	+ for (i = 0; i <= ca0132_effects[idx].params; i++) {
	8264	+ dspio_set_uint_param(codec,
	8265	+ ca0132_effects[idx].mid,
	8266	+ ca0132_effects[idx].reqs[i],
	8267	+ ca0132_effects[idx].def_vals[i]);
	8268	+ }
	8269	+ }
	8270	+
	8271	+ ca0132_alt_init_speaker_tuning(codec);
	8272	+
	8273	+ ca0132_alt_create_dummy_stream(codec);
	8274	+}
	8275	+
	8276	+/*
	8277	+ * Setup default parameters for the Sound Blaster AE-7 DSP.
	8278	+ */
	8279	+static void ae7_setup_defaults(struct hda_codec *codec)
	8280	+{
	8281	+ struct ca0132_spec *spec = codec->spec;
	8282	+ unsigned int tmp;
	8283	+ int num_fx;
	8284	+ int idx, i;
	8285	+
	8286	+ if (spec->dsp_state != DSP_DOWNLOADED)
	8287	+ return;
	8288	+
	8289	+ ca0132_alt_dsp_scp_startup(codec);
	8290	+ ca0132_alt_init_analog_mics(codec);
	8291	+ ae7_post_dsp_setup_ports(codec);
	8292	+
	8293	+ tmp = FLOAT_ZERO;
	8294	+ dspio_set_uint_param(codec, 0x96,
	8295	+ SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp);
	8296	+ dspio_set_uint_param(codec, 0x96,
	8297	+ SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp);
	8298	+
	8299	+ ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
	8300	+
	8301	+ /* New, unknown SCP req's */
	8302	+ dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
	8303	+ dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
	8304	+
	8305	+ ca0113_mmio_gpio_set(codec, 0, false);
	8306	+
	8307	+ /* Internal loopback off */
	8308	+ tmp = FLOAT_ONE;
	8309	+ dspio_set_uint_param(codec, 0x37, 0x08, tmp);
	8310	+ dspio_set_uint_param(codec, 0x37, 0x10, tmp);
	8311	+
	8312	+ /remove DSP headroom/
	8313	+ tmp = FLOAT_ZERO;
	8314	+ dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
	8315	+
	8316	+ /* set WUH source */
	8317	+ tmp = FLOAT_TWO;
	8318	+ dspio_set_uint_param(codec, 0x31, 0x00, tmp);
	8319	+ chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
	8320	+
	8321	+ /* Set speaker source? */
	8322	+ dspio_set_uint_param(codec, 0x32, 0x00, tmp);
	8323	+ ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
	8324	+
6581	8325	/*
6582		- * Have to make a stream to bind the sound output to, otherwise
6583		- * you'll get dead audio. Before I did this, it would bind to an
6584		- * audio input, and would never work
	8326	+ * This is the second time we've called this, but this is seemingly
	8327	+ * what Windows does.
6585	8328	*/
6586		- stream_format = snd_hdac_calc_stream_format(48000, 2,
6587		- SNDRV_PCM_FORMAT_S32_LE, 32, 0);
	8329	+ ca0132_alt_init_analog_mics(codec);
6588	8330
6589		- snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6590		- 0, stream_format);
	8331	+ ae7_post_dsp_asi_setup(codec);
6591	8332
6592		- snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
	8333	+ /*
	8334	+ * Not sure why, but these are both set to 1. They're only set to 0
	8335	+ * upon shutdown.
	8336	+ */
	8337	+ ca0113_mmio_gpio_set(codec, 0, true);
	8338	+ ca0113_mmio_gpio_set(codec, 1, true);
6593	8339
6594		- snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6595		- 0, stream_format);
	8340	+ /* Volume control related. */
	8341	+ ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04);
	8342	+ ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04);
	8343	+ ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80);
6596	8344
6597		- snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
	8345	+ /* out, in effects + voicefx */
	8346	+ num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
	8347	+ for (idx = 0; idx < num_fx; idx++) {
	8348	+ for (i = 0; i <= ca0132_effects[idx].params; i++) {
	8349	+ dspio_set_uint_param(codec,
	8350	+ ca0132_effects[idx].mid,
	8351	+ ca0132_effects[idx].reqs[i],
	8352	+ ca0132_effects[idx].def_vals[i]);
	8353	+ }
	8354	+ }
	8355	+
	8356	+ ca0132_alt_init_speaker_tuning(codec);
	8357	+
	8358	+ ca0132_alt_create_dummy_stream(codec);
6598	8359	}
6599	8360
6600	8361	/*
..	..	@@ -6604,7 +8365,7 @@
6604	8365	{
6605	8366	struct ca0132_spec *spec = codec->spec;
6606	8367
6607		- if (spec->use_alt_functions) {
	8368	+ if (ca0132_use_alt_functions(spec)) {
6608	8369	chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
6609	8370	chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
6610	8371	chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
..	..	@@ -6637,7 +8398,7 @@
6637	8398	{
6638	8399	struct ca0132_spec *spec = codec->spec;
6639	8400
6640		- if (spec->use_alt_functions) {
	8401	+ if (ca0132_use_alt_functions(spec)) {
6641	8402	chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6642	8403	chipio_set_conn_rate(codec, 0x0B, SR_48_000);
6643	8404	chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
..	..	@@ -6668,42 +8429,37 @@
6668	8429	bool dsp_loaded = false;
6669	8430	struct ca0132_spec *spec = codec->spec;
6670	8431	const struct dsp_image_seg *dsp_os_image;
6671		- const struct firmware *fw_entry;
	8432	+ const struct firmware *fw_entry = NULL;
6672	8433	/*
6673	8434	* Alternate firmwares for different variants. The Recon3Di apparently
6674	8435	* can use the default firmware, but I'll leave the option in case
6675	8436	* it needs it again.
6676	8437	*/
6677		- switch (spec->quirk) {
	8438	+ switch (ca0132_quirk(spec)) {
6678	8439	case QUIRK_SBZ:
6679		- if (request_firmware(&fw_entry, SBZ_EFX_FILE,
6680		- codec->card->dev) != 0) {
6681		- codec_dbg(codec, "SBZ alt firmware not detected. ");
6682		- spec->alt_firmware_present = false;
6683		- } else {
6684		- codec_dbg(codec, "Sound Blaster Z firmware selected.");
6685		- spec->alt_firmware_present = true;
6686		- }
	8440	+ case QUIRK_R3D:
	8441	+ case QUIRK_AE5:
	8442	+ if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
	8443	+ codec->card->dev) != 0)
	8444	+ codec_dbg(codec, "Desktop firmware not found.");
	8445	+ else
	8446	+ codec_dbg(codec, "Desktop firmware selected.");
6687	8447	break;
6688	8448	case QUIRK_R3DI:
6689	8449	if (request_firmware(&fw_entry, R3DI_EFX_FILE,
6690		- codec->card->dev) != 0) {
	8450	+ codec->card->dev) != 0)
6691	8451	codec_dbg(codec, "Recon3Di alt firmware not detected.");
6692		- spec->alt_firmware_present = false;
6693		- } else {
	8452	+ else
6694	8453	codec_dbg(codec, "Recon3Di firmware selected.");
6695		- spec->alt_firmware_present = true;
6696		- }
6697	8454	break;
6698	8455	default:
6699		- spec->alt_firmware_present = false;
6700	8456	break;
6701	8457	}
6702	8458	/*
6703	8459	* Use default ctefx.bin if no alt firmware is detected, or if none
6704	8460	* exists for your particular codec.
6705	8461	*/
6706		- if (!spec->alt_firmware_present) {
	8462	+ if (!fw_entry) {
6707	8463	codec_dbg(codec, "Default firmware selected.");
6708	8464	if (request_firmware(&fw_entry, EFX_FILE,
6709	8465	codec->card->dev) != 0)
..	..	@@ -6746,7 +8502,7 @@
6746	8502	}
6747	8503
6748	8504	/* For codecs using alt functions, this is already done earlier */
6749		- if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
	8505	+ if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
6750	8506	ca0132_set_dsp_msr(codec, true);
6751	8507	}
6752	8508
..	..	@@ -6784,7 +8540,7 @@
6784	8540	{
6785	8541	struct ca0132_spec *spec = codec->spec;
6786	8542
6787		- if (spec->use_alt_functions)
	8543	+ if (ca0132_use_alt_functions(spec))
6788	8544	ca0132_alt_select_in(codec);
6789	8545	else
6790	8546	ca0132_select_mic(codec);
..	..	@@ -6799,7 +8555,7 @@
6799	8555	snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
6800	8556	ca0132_process_dsp_response);
6801	8557	/* Front headphone jack detection */
6802		- if (spec->use_alt_functions)
	8558	+ if (ca0132_use_alt_functions(spec))
6803	8559	snd_hda_jack_detect_enable_callback(codec,
6804	8560	spec->unsol_tag_front_hp, hp_callback);
6805	8561	}
..	..	@@ -6809,14 +8565,14 @@
6809	8565	*/
6810	8566
6811	8567	/* Sends before DSP download. */
6812		-static struct hda_verb ca0132_base_init_verbs[] = {
	8568	+static const struct hda_verb ca0132_base_init_verbs[] = {
6813	8569	/enable ct extension/
6814	8570	{0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
6815	8571	{}
6816	8572	};
6817	8573
6818	8574	/* Send at exit. */
6819		-static struct hda_verb ca0132_base_exit_verbs[] = {
	8575	+static const struct hda_verb ca0132_base_exit_verbs[] = {
6820	8576	/set afg to D3/
6821	8577	{0x01, AC_VERB_SET_POWER_STATE, 0x03},
6822	8578	/disable ct extension/
..	..	@@ -6826,7 +8582,7 @@
6826	8582
6827	8583	/* Other verbs tables. Sends after DSP download. */
6828	8584
6829		-static struct hda_verb ca0132_init_verbs0[] = {
	8585	+static const struct hda_verb ca0132_init_verbs0[] = {
6830	8586	/* chip init verbs */
6831	8587	{0x15, 0x70D, 0xF0},
6832	8588	{0x15, 0x70E, 0xFE},
..	..	@@ -6859,7 +8615,7 @@
6859	8615	};
6860	8616
6861	8617	/* Extra init verbs for desktop cards. */
6862		-static struct hda_verb ca0132_init_verbs1[] = {
	8618	+static const struct hda_verb ca0132_init_verbs1[] = {
6863	8619	{0x15, 0x70D, 0x20},
6864	8620	{0x15, 0x70E, 0x19},
6865	8621	{0x15, 0x707, 0x00},
..	..	@@ -6889,7 +8645,7 @@
6889	8645	mutex_init(&spec->chipio_mutex);
6890	8646
6891	8647	spec->cur_out_type = SPEAKER_OUT;
6892		- if (!spec->use_alt_functions)
	8648	+ if (!ca0132_use_alt_functions(spec))
6893	8649	spec->cur_mic_type = DIGITAL_MIC;
6894	8650	else
6895	8651	spec->cur_mic_type = REAR_MIC;
..	..	@@ -6915,15 +8671,29 @@
6915	8671	* Sets defaults for the effect slider controls, only for alternative
6916	8672	* ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
6917	8673	*/
6918		- if (spec->use_alt_controls) {
	8674	+ if (ca0132_use_alt_controls(spec)) {
	8675	+ /* Set speakers to default to full range. */
	8676	+ spec->speaker_range_val[0] = 1;
	8677	+ spec->speaker_range_val[1] = 1;
	8678	+
6919	8679	spec->xbass_xover_freq = 8;
6920	8680	for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
6921	8681	spec->fx_ctl_val[i] = effect_slider_defaults[i];
	8682	+
	8683	+ spec->bass_redirect_xover_freq = 8;
6922	8684	}
6923	8685
6924	8686	spec->voicefx_val = 0;
6925	8687	spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
6926	8688	spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
	8689	+
	8690	+ /*
	8691	+ * The ZxR doesn't have a front panel header, and it's line-in is on
	8692	+ * the daughter board. So, there is no input enum control, and we need
	8693	+ * to make sure that spec->in_enum_val is set properly.
	8694	+ */
	8695	+ if (ca0132_quirk(spec) == QUIRK_ZXR)
	8696	+ spec->in_enum_val = REAR_MIC;
6927	8697
6928	8698	#ifdef ENABLE_TUNING_CONTROLS
6929	8699	ca0132_init_tuning_defaults(codec);
..	..	@@ -6952,32 +8722,32 @@
6952	8722	for (i = 0; i < 8; i++)
6953	8723	writeb(0xb3, spec->mem_base + 0x304);
6954	8724
6955		- ca0132_mmio_gpio_set(codec, 0, false);
6956		- ca0132_mmio_gpio_set(codec, 1, false);
6957		- ca0132_mmio_gpio_set(codec, 4, true);
6958		- ca0132_mmio_gpio_set(codec, 5, false);
6959		- ca0132_mmio_gpio_set(codec, 7, false);
	8725	+ ca0113_mmio_gpio_set(codec, 0, false);
	8726	+ ca0113_mmio_gpio_set(codec, 1, false);
	8727	+ ca0113_mmio_gpio_set(codec, 4, true);
	8728	+ ca0113_mmio_gpio_set(codec, 5, false);
	8729	+ ca0113_mmio_gpio_set(codec, 7, false);
6960	8730	}
6961	8731
6962	8732	static void sbz_set_pin_ctl_default(struct hda_codec *codec)
6963	8733	{
6964		- hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
	8734	+ static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
6965	8735	unsigned int i;
6966	8736
6967	8737	snd_hda_codec_write(codec, 0x11, 0,
6968	8738	AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
6969	8739
6970		- for (i = 0; i < 5; i++)
	8740	+ for (i = 0; i < ARRAY_SIZE(pins); i++)
6971	8741	snd_hda_codec_write(codec, pins[i], 0,
6972	8742	AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
6973	8743	}
6974	8744
6975	8745	static void ca0132_clear_unsolicited(struct hda_codec *codec)
6976	8746	{
6977		- hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
	8747	+ static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
6978	8748	unsigned int i;
6979	8749
6980		- for (i = 0; i < 7; i++) {
	8750	+ for (i = 0; i < ARRAY_SIZE(pins); i++) {
6981	8751	snd_hda_codec_write(codec, pins[i], 0,
6982	8752	AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
6983	8753	}
..	..	@@ -6997,6 +8767,16 @@
6997	8767	if (data >= 0)
6998	8768	snd_hda_codec_write(codec, 0x01, 0,
6999	8769	AC_VERB_SET_GPIO_DATA, data);
	8770	+}
	8771	+
	8772	+static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
	8773	+{
	8774	+ static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
	8775	+ unsigned int i;
	8776	+
	8777	+ for (i = 0; i < ARRAY_SIZE(pins); i++)
	8778	+ snd_hda_codec_write(codec, pins[i], 0,
	8779	+ AC_VERB_SET_POWER_STATE, 0x03);
7000	8780	}
7001	8781
7002	8782	static void sbz_exit_chip(struct hda_codec *codec)
..	..	@@ -7039,6 +8819,87 @@
7039	8819	ca0132_clear_unsolicited(codec);
7040	8820	snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7041	8821	snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
	8822	+}
	8823	+
	8824	+static void ae5_exit_chip(struct hda_codec *codec)
	8825	+{
	8826	+ chipio_set_stream_control(codec, 0x03, 0);
	8827	+ chipio_set_stream_control(codec, 0x04, 0);
	8828	+
	8829	+ ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
	8830	+ ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
	8831	+ ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
	8832	+ ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
	8833	+ ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
	8834	+ ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
	8835	+ ca0113_mmio_gpio_set(codec, 0, false);
	8836	+ ca0113_mmio_gpio_set(codec, 1, false);
	8837	+
	8838	+ snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
	8839	+ snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
	8840	+
	8841	+ chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
	8842	+
	8843	+ chipio_set_stream_control(codec, 0x18, 0);
	8844	+ chipio_set_stream_control(codec, 0x0c, 0);
	8845	+
	8846	+ snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
	8847	+}
	8848	+
	8849	+static void ae7_exit_chip(struct hda_codec *codec)
	8850	+{
	8851	+ chipio_set_stream_control(codec, 0x18, 0);
	8852	+ chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);
	8853	+ chipio_set_stream_channels(codec, 0x21, 0);
	8854	+ chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);
	8855	+ chipio_set_control_param(codec, 0x20, 0x01);
	8856	+
	8857	+ chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
	8858	+
	8859	+ chipio_set_stream_control(codec, 0x18, 0);
	8860	+ chipio_set_stream_control(codec, 0x0c, 0);
	8861	+
	8862	+ ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
	8863	+ snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);
	8864	+ ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
	8865	+ ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
	8866	+ ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);
	8867	+ ca0113_mmio_gpio_set(codec, 0, false);
	8868	+ ca0113_mmio_gpio_set(codec, 1, false);
	8869	+ ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
	8870	+
	8871	+ snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
	8872	+ snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
	8873	+}
	8874	+
	8875	+static void zxr_exit_chip(struct hda_codec *codec)
	8876	+{
	8877	+ chipio_set_stream_control(codec, 0x03, 0);
	8878	+ chipio_set_stream_control(codec, 0x04, 0);
	8879	+ chipio_set_stream_control(codec, 0x14, 0);
	8880	+ chipio_set_stream_control(codec, 0x0C, 0);
	8881	+
	8882	+ chipio_set_conn_rate(codec, 0x41, SR_192_000);
	8883	+ chipio_set_conn_rate(codec, 0x91, SR_192_000);
	8884	+
	8885	+ chipio_write(codec, 0x18a020, 0x00000083);
	8886	+
	8887	+ snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
	8888	+ snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
	8889	+
	8890	+ ca0132_clear_unsolicited(codec);
	8891	+ sbz_set_pin_ctl_default(codec);
	8892	+ snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
	8893	+
	8894	+ ca0113_mmio_gpio_set(codec, 5, false);
	8895	+ ca0113_mmio_gpio_set(codec, 2, false);
	8896	+ ca0113_mmio_gpio_set(codec, 3, false);
	8897	+ ca0113_mmio_gpio_set(codec, 0, false);
	8898	+ ca0113_mmio_gpio_set(codec, 4, true);
	8899	+ ca0113_mmio_gpio_set(codec, 0, true);
	8900	+ ca0113_mmio_gpio_set(codec, 5, true);
	8901	+ ca0113_mmio_gpio_set(codec, 2, false);
	8902	+ ca0113_mmio_gpio_set(codec, 3, false);
7042	8903	}
7043	8904
7044	8905	static void ca0132_exit_chip(struct hda_codec *codec)
..	..	@@ -7144,11 +9005,6 @@
7144	9005	writel(0x00820680, spec->mem_base + 0x01C);
7145	9006	writel(0x00820680, spec->mem_base + 0x01C);
7146	9007
7147		- snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7148		- snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7149		- snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7150		- snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7151		-
7152	9008	chipio_write(codec, 0x18b0a4, 0x000000c2);
7153	9009
7154	9010	snd_hda_codec_write(codec, 0x11, 0,
..	..	@@ -7157,12 +9013,6 @@
7157	9013
7158	9014	static void r3d_pre_dsp_setup(struct hda_codec *codec)
7159	9015	{
7160		-
7161		- snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7162		- snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7163		- snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7164		- snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7165		-
7166	9016	chipio_write(codec, 0x18b0a4, 0x000000c2);
7167	9017
7168	9018	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
..	..	@@ -7205,27 +9055,220 @@
7205	9055	* what they do, or if they're necessary. Could possibly
7206	9056	* be removed. Figure they're better to leave in.
7207	9057	*/
	9058	+static const unsigned int ca0113_mmio_init_address_sbz[] = {
	9059	+ 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c,
	9060	+ 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04
	9061	+};
	9062	+
	9063	+static const unsigned int ca0113_mmio_init_data_sbz[] = {
	9064	+ 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
	9065	+ 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7,
	9066	+ 0x000000c1, 0x00000080
	9067	+};
	9068	+
	9069	+static const unsigned int ca0113_mmio_init_data_zxr[] = {
	9070	+ 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003,
	9071	+ 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7,
	9072	+ 0x000000c1, 0x00000080
	9073	+};
	9074	+
	9075	+static const unsigned int ca0113_mmio_init_address_ae5[] = {
	9076	+ 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408,
	9077	+ 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800,
	9078	+ 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c,
	9079	+ 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c
	9080	+};
	9081	+
	9082	+static const unsigned int ca0113_mmio_init_data_ae5[] = {
	9083	+ 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
	9084	+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
	9085	+ 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f,
	9086	+ 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b,
	9087	+ 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030,
	9088	+ 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
	9089	+ 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1,
	9090	+ 0x00000080, 0x00880680
	9091	+};
	9092	+
	9093	+static void ca0132_mmio_init_sbz(struct hda_codec *codec)
	9094	+{
	9095	+ struct ca0132_spec *spec = codec->spec;
	9096	+ unsigned int tmp[2], i, count, cur_addr;
	9097	+ const unsigned int addr, data;
	9098	+
	9099	+ addr = ca0113_mmio_init_address_sbz;
	9100	+ for (i = 0; i < 3; i++)
	9101	+ writel(0x00000000, spec->mem_base + addr[i]);
	9102	+
	9103	+ cur_addr = i;
	9104	+ switch (ca0132_quirk(spec)) {
	9105	+ case QUIRK_ZXR:
	9106	+ tmp[0] = 0x00880480;
	9107	+ tmp[1] = 0x00000080;
	9108	+ break;
	9109	+ case QUIRK_SBZ:
	9110	+ tmp[0] = 0x00820680;
	9111	+ tmp[1] = 0x00000083;
	9112	+ break;
	9113	+ case QUIRK_R3D:
	9114	+ tmp[0] = 0x00880680;
	9115	+ tmp[1] = 0x00000083;
	9116	+ break;
	9117	+ default:
	9118	+ tmp[0] = 0x00000000;
	9119	+ tmp[1] = 0x00000000;
	9120	+ break;
	9121	+ }
	9122	+
	9123	+ for (i = 0; i < 2; i++)
	9124	+ writel(tmp[i], spec->mem_base + addr[cur_addr + i]);
	9125	+
	9126	+ cur_addr += i;
	9127	+
	9128	+ switch (ca0132_quirk(spec)) {
	9129	+ case QUIRK_ZXR:
	9130	+ count = ARRAY_SIZE(ca0113_mmio_init_data_zxr);
	9131	+ data = ca0113_mmio_init_data_zxr;
	9132	+ break;
	9133	+ default:
	9134	+ count = ARRAY_SIZE(ca0113_mmio_init_data_sbz);
	9135	+ data = ca0113_mmio_init_data_sbz;
	9136	+ break;
	9137	+ }
	9138	+
	9139	+ for (i = 0; i < count; i++)
	9140	+ writel(data[i], spec->mem_base + addr[cur_addr + i]);
	9141	+}
	9142	+
	9143	+static void ca0132_mmio_init_ae5(struct hda_codec *codec)
	9144	+{
	9145	+ struct ca0132_spec *spec = codec->spec;
	9146	+ const unsigned int addr, data;
	9147	+ unsigned int i, count;
	9148	+
	9149	+ addr = ca0113_mmio_init_address_ae5;
	9150	+ data = ca0113_mmio_init_data_ae5;
	9151	+ count = ARRAY_SIZE(ca0113_mmio_init_data_ae5);
	9152	+
	9153	+ if (ca0132_quirk(spec) == QUIRK_AE7) {
	9154	+ writel(0x00000680, spec->mem_base + 0x1c);
	9155	+ writel(0x00880680, spec->mem_base + 0x1c);
	9156	+ }
	9157	+
	9158	+ for (i = 0; i < count; i++) {
	9159	+ /*
	9160	+ * AE-7 shares all writes with the AE-5, except that it writes
	9161	+ * a different value to 0x20c.
	9162	+ */
	9163	+ if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) {
	9164	+ writel(0x00800001, spec->mem_base + addr[i]);
	9165	+ continue;
	9166	+ }
	9167	+
	9168	+ writel(data[i], spec->mem_base + addr[i]);
	9169	+ }
	9170	+
	9171	+ if (ca0132_quirk(spec) == QUIRK_AE5)
	9172	+ writel(0x00880680, spec->mem_base + 0x1c);
	9173	+}
	9174	+
7208	9175	static void ca0132_mmio_init(struct hda_codec *codec)
7209	9176	{
7210	9177	struct ca0132_spec *spec = codec->spec;
7211	9178
7212		- writel(0x00000000, spec->mem_base + 0x400);
7213		- writel(0x00000000, spec->mem_base + 0x408);
7214		- writel(0x00000000, spec->mem_base + 0x40C);
7215		- writel(0x00880680, spec->mem_base + 0x01C);
7216		- writel(0x00000083, spec->mem_base + 0xC0C);
7217		- writel(0x00000030, spec->mem_base + 0xC00);
7218		- writel(0x00000000, spec->mem_base + 0xC04);
7219		- writel(0x00000003, spec->mem_base + 0xC0C);
7220		- writel(0x00000003, spec->mem_base + 0xC0C);
7221		- writel(0x00000003, spec->mem_base + 0xC0C);
7222		- writel(0x00000003, spec->mem_base + 0xC0C);
7223		- writel(0x000000C1, spec->mem_base + 0xC08);
7224		- writel(0x000000F1, spec->mem_base + 0xC08);
7225		- writel(0x00000001, spec->mem_base + 0xC08);
7226		- writel(0x000000C7, spec->mem_base + 0xC08);
7227		- writel(0x000000C1, spec->mem_base + 0xC08);
7228		- writel(0x00000080, spec->mem_base + 0xC04);
	9179	+ switch (ca0132_quirk(spec)) {
	9180	+ case QUIRK_R3D:
	9181	+ case QUIRK_SBZ:
	9182	+ case QUIRK_ZXR:
	9183	+ ca0132_mmio_init_sbz(codec);
	9184	+ break;
	9185	+ case QUIRK_AE5:
	9186	+ ca0132_mmio_init_ae5(codec);
	9187	+ break;
	9188	+ default:
	9189	+ break;
	9190	+ }
	9191	+}
	9192	+
	9193	+static const unsigned int ca0132_ae5_register_set_addresses[] = {
	9194	+ 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304,
	9195	+ 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804
	9196	+};
	9197	+
	9198	+static const unsigned char ca0132_ae5_register_set_data[] = {
	9199	+ 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b,
	9200	+ 0x01, 0x6b, 0x57
	9201	+};
	9202	+
	9203	+/*
	9204	+ * This function writes to some SFR's, does some region2 writes, and then
	9205	+ * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
	9206	+ * what it does.
	9207	+ */
	9208	+static void ae5_register_set(struct hda_codec *codec)
	9209	+{
	9210	+ struct ca0132_spec *spec = codec->spec;
	9211	+ unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses);
	9212	+ const unsigned int *addr = ca0132_ae5_register_set_addresses;
	9213	+ const unsigned char *data = ca0132_ae5_register_set_data;
	9214	+ unsigned int i, cur_addr;
	9215	+ unsigned char tmp[3];
	9216	+
	9217	+ if (ca0132_quirk(spec) == QUIRK_AE7) {
	9218	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	9219	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
	9220	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	9221	+ VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
	9222	+ }
	9223	+
	9224	+ chipio_8051_write_direct(codec, 0x93, 0x10);
	9225	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	9226	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
	9227	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	9228	+ VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
	9229	+
	9230	+ if (ca0132_quirk(spec) == QUIRK_AE7) {
	9231	+ tmp[0] = 0x03;
	9232	+ tmp[1] = 0x03;
	9233	+ tmp[2] = 0x07;
	9234	+ } else {
	9235	+ tmp[0] = 0x0f;
	9236	+ tmp[1] = 0x0f;
	9237	+ tmp[2] = 0x0f;
	9238	+ }
	9239	+
	9240	+ for (i = cur_addr = 0; i < 3; i++, cur_addr++)
	9241	+ writeb(tmp[i], spec->mem_base + addr[cur_addr]);
	9242	+
	9243	+ /*
	9244	+ * First writes are in single bytes, final are in 4 bytes. So, we use
	9245	+ * writeb, then writel.
	9246	+ */
	9247	+ for (i = 0; cur_addr < 12; i++, cur_addr++)
	9248	+ writeb(data[i], spec->mem_base + addr[cur_addr]);
	9249	+
	9250	+ for (; cur_addr < count; i++, cur_addr++)
	9251	+ writel(data[i], spec->mem_base + addr[cur_addr]);
	9252	+
	9253	+ writel(0x00800001, spec->mem_base + 0x20c);
	9254	+
	9255	+ if (ca0132_quirk(spec) == QUIRK_AE7) {
	9256	+ ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
	9257	+ ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
	9258	+ } else {
	9259	+ ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
	9260	+ }
	9261	+
	9262	+ chipio_8051_write_direct(codec, 0x90, 0x00);
	9263	+ chipio_8051_write_direct(codec, 0x90, 0x10);
	9264	+
	9265	+ if (ca0132_quirk(spec) == QUIRK_AE5)
	9266	+ ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
	9267	+
	9268	+ chipio_write(codec, 0x18b0a4, 0x000000c2);
	9269	+
	9270	+ snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
	9271	+ snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
7229	9272	}
7230	9273
7231	9274	/*
..	..	@@ -7239,7 +9282,7 @@
7239	9282
7240	9283	ca0132_alt_vol_setup(codec);
7241	9284
7242		- switch (spec->quirk) {
	9285	+ switch (ca0132_quirk(spec)) {
7243	9286	case QUIRK_SBZ:
7244	9287	codec_dbg(codec, "SBZ alt_init");
7245	9288	ca0132_gpio_init(codec);
..	..	@@ -7260,6 +9303,36 @@
7260	9303	r3d_pre_dsp_setup(codec);
7261	9304	snd_hda_sequence_write(codec, spec->chip_init_verbs);
7262	9305	snd_hda_sequence_write(codec, spec->desktop_init_verbs);
	9306	+ break;
	9307	+ case QUIRK_AE5:
	9308	+ ca0132_gpio_init(codec);
	9309	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	9310	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
	9311	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	9312	+ VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
	9313	+ chipio_write(codec, 0x18b030, 0x00000020);
	9314	+ snd_hda_sequence_write(codec, spec->chip_init_verbs);
	9315	+ snd_hda_sequence_write(codec, spec->desktop_init_verbs);
	9316	+ ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
	9317	+ break;
	9318	+ case QUIRK_AE7:
	9319	+ ca0132_gpio_init(codec);
	9320	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	9321	+ VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
	9322	+ snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
	9323	+ VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
	9324	+ snd_hda_sequence_write(codec, spec->chip_init_verbs);
	9325	+ snd_hda_sequence_write(codec, spec->desktop_init_verbs);
	9326	+ chipio_write(codec, 0x18b008, 0x000000f8);
	9327	+ chipio_write(codec, 0x18b008, 0x000000f0);
	9328	+ chipio_write(codec, 0x18b030, 0x00000020);
	9329	+ ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
	9330	+ break;
	9331	+ case QUIRK_ZXR:
	9332	+ snd_hda_sequence_write(codec, spec->chip_init_verbs);
	9333	+ snd_hda_sequence_write(codec, spec->desktop_init_verbs);
	9334	+ break;
	9335	+ default:
7263	9336	break;
7264	9337	}
7265	9338	}
..	..	@@ -7287,7 +9360,7 @@
7287	9360	spec->dsp_reload = true;
7288	9361	spec->dsp_state = DSP_DOWNLOAD_INIT;
7289	9362	} else {
7290		- if (spec->quirk == QUIRK_SBZ)
	9363	+ if (ca0132_quirk(spec) == QUIRK_SBZ)
7291	9364	sbz_dsp_startup_check(codec);
7292	9365	return 0;
7293	9366	}
..	..	@@ -7297,10 +9370,13 @@
7297	9370	spec->dsp_state = DSP_DOWNLOAD_INIT;
7298	9371	spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
7299	9372
7300		- if (spec->use_pci_mmio)
	9373	+ if (ca0132_use_pci_mmio(spec))
7301	9374	ca0132_mmio_init(codec);
7302	9375
7303	9376	snd_hda_power_up_pm(codec);
	9377	+
	9378	+ if (ca0132_quirk(spec) == QUIRK_AE5 \|\| ca0132_quirk(spec) == QUIRK_AE7)
	9379	+ ae5_register_set(codec);
7304	9380
7305	9381	ca0132_init_unsol(codec);
7306	9382	ca0132_init_params(codec);
..	..	@@ -7308,20 +9384,27 @@
7308	9384
7309	9385	snd_hda_sequence_write(codec, spec->base_init_verbs);
7310	9386
7311		- if (spec->use_alt_functions)
	9387	+ if (ca0132_use_alt_functions(spec))
7312	9388	ca0132_alt_init(codec);
7313	9389
7314	9390	ca0132_download_dsp(codec);
7315	9391
7316	9392	ca0132_refresh_widget_caps(codec);
7317	9393
7318		- switch (spec->quirk) {
	9394	+ switch (ca0132_quirk(spec)) {
7319	9395	case QUIRK_R3DI:
7320	9396	case QUIRK_R3D:
7321	9397	r3d_setup_defaults(codec);
7322	9398	break;
7323	9399	case QUIRK_SBZ:
	9400	+ case QUIRK_ZXR:
7324	9401	sbz_setup_defaults(codec);
	9402	+ break;
	9403	+ case QUIRK_AE5:
	9404	+ ae5_setup_defaults(codec);
	9405	+ break;
	9406	+ case QUIRK_AE7:
	9407	+ ae7_setup_defaults(codec);
7325	9408	break;
7326	9409	default:
7327	9410	ca0132_setup_defaults(codec);
..	..	@@ -7340,7 +9423,7 @@
7340	9423
7341	9424	init_input(codec, cfg->dig_in_pin, spec->dig_in);
7342	9425
7343		- if (!spec->use_alt_functions) {
	9426	+ if (!ca0132_use_alt_functions(spec)) {
7344	9427	snd_hda_sequence_write(codec, spec->chip_init_verbs);
7345	9428	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7346	9429	VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
..	..	@@ -7348,11 +9431,11 @@
7348	9431	VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
7349	9432	}
7350	9433
7351		- if (spec->quirk == QUIRK_SBZ)
	9434	+ if (ca0132_quirk(spec) == QUIRK_SBZ)
7352	9435	ca0132_gpio_setup(codec);
7353	9436
7354	9437	snd_hda_sequence_write(codec, spec->spec_init_verbs);
7355		- if (spec->use_alt_functions) {
	9438	+ if (ca0132_use_alt_functions(spec)) {
7356	9439	ca0132_alt_select_out(codec);
7357	9440	ca0132_alt_select_in(codec);
7358	9441	} else {
..	..	@@ -7376,21 +9459,47 @@
7376	9459	return 0;
7377	9460	}
7378	9461
	9462	+static int dbpro_init(struct hda_codec *codec)
	9463	+{
	9464	+ struct ca0132_spec *spec = codec->spec;
	9465	+ struct auto_pin_cfg *cfg = &spec->autocfg;
	9466	+ unsigned int i;
	9467	+
	9468	+ init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
	9469	+ init_input(codec, cfg->dig_in_pin, spec->dig_in);
	9470	+
	9471	+ for (i = 0; i < spec->num_inputs; i++)
	9472	+ init_input(codec, spec->input_pins[i], spec->adcs[i]);
	9473	+
	9474	+ return 0;
	9475	+}
	9476	+
7379	9477	static void ca0132_free(struct hda_codec *codec)
7380	9478	{
7381	9479	struct ca0132_spec *spec = codec->spec;
7382	9480
7383	9481	cancel_delayed_work_sync(&spec->unsol_hp_work);
7384	9482	snd_hda_power_up(codec);
7385		- switch (spec->quirk) {
	9483	+ switch (ca0132_quirk(spec)) {
7386	9484	case QUIRK_SBZ:
7387	9485	sbz_exit_chip(codec);
	9486	+ break;
	9487	+ case QUIRK_ZXR:
	9488	+ zxr_exit_chip(codec);
7388	9489	break;
7389	9490	case QUIRK_R3D:
7390	9491	r3d_exit_chip(codec);
7391	9492	break;
	9493	+ case QUIRK_AE5:
	9494	+ ae5_exit_chip(codec);
	9495	+ break;
	9496	+ case QUIRK_AE7:
	9497	+ ae7_exit_chip(codec);
	9498	+ break;
7392	9499	case QUIRK_R3DI:
7393	9500	r3di_gpio_shutdown(codec);
	9501	+ break;
	9502	+ default:
7394	9503	break;
7395	9504	}
7396	9505
..	..	@@ -7402,6 +9511,16 @@
7402	9511	if (spec->mem_base)
7403	9512	pci_iounmap(codec->bus->pci, spec->mem_base);
7404	9513	#endif
	9514	+ kfree(spec->spec_init_verbs);
	9515	+ kfree(codec->spec);
	9516	+}
	9517	+
	9518	+static void dbpro_free(struct hda_codec *codec)
	9519	+{
	9520	+ struct ca0132_spec *spec = codec->spec;
	9521	+
	9522	+ zxr_dbpro_power_state_shutdown(codec);
	9523	+
7405	9524	kfree(spec->spec_init_verbs);
7406	9525	kfree(codec->spec);
7407	9526	}
..	..	@@ -7433,6 +9552,13 @@
7433	9552	.reboot_notify = ca0132_reboot_notify,
7434	9553	};
7435	9554
	9555	+static const struct hda_codec_ops dbpro_patch_ops = {
	9556	+ .build_controls = dbpro_build_controls,
	9557	+ .build_pcms = dbpro_build_pcms,
	9558	+ .init = dbpro_init,
	9559	+ .free = dbpro_free,
	9560	+};
	9561	+
7436	9562	static void ca0132_config(struct hda_codec *codec)
7437	9563	{
7438	9564	struct ca0132_spec *spec = codec->spec;
..	..	@@ -7444,16 +9570,46 @@
7444	9570	spec->multiout.dac_nids = spec->dacs;
7445	9571	spec->multiout.num_dacs = 3;
7446	9572
7447		- if (!spec->use_alt_functions)
	9573	+ if (!ca0132_use_alt_functions(spec))
7448	9574	spec->multiout.max_channels = 2;
7449	9575	else
7450	9576	spec->multiout.max_channels = 6;
7451	9577
7452		- switch (spec->quirk) {
	9578	+ switch (ca0132_quirk(spec)) {
7453	9579	case QUIRK_ALIENWARE:
7454		- codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
	9580	+ codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
7455	9581	snd_hda_apply_pincfgs(codec, alienware_pincfgs);
	9582	+ break;
	9583	+ case QUIRK_SBZ:
	9584	+ codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
	9585	+ snd_hda_apply_pincfgs(codec, sbz_pincfgs);
	9586	+ break;
	9587	+ case QUIRK_ZXR:
	9588	+ codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
	9589	+ snd_hda_apply_pincfgs(codec, zxr_pincfgs);
	9590	+ break;
	9591	+ case QUIRK_R3D:
	9592	+ codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
	9593	+ snd_hda_apply_pincfgs(codec, r3d_pincfgs);
	9594	+ break;
	9595	+ case QUIRK_R3DI:
	9596	+ codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
	9597	+ snd_hda_apply_pincfgs(codec, r3di_pincfgs);
	9598	+ break;
	9599	+ case QUIRK_AE5:
	9600	+ codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
	9601	+ snd_hda_apply_pincfgs(codec, ae5_pincfgs);
	9602	+ break;
	9603	+ case QUIRK_AE7:
	9604	+ codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__);
	9605	+ snd_hda_apply_pincfgs(codec, ae7_pincfgs);
	9606	+ break;
	9607	+ default:
	9608	+ break;
	9609	+ }
7456	9610
	9611	+ switch (ca0132_quirk(spec)) {
	9612	+ case QUIRK_ALIENWARE:
7457	9613	spec->num_outputs = 2;
7458	9614	spec->out_pins[0] = 0x0b; /* speaker out */
7459	9615	spec->out_pins[1] = 0x0f;
..	..	@@ -7473,15 +9629,6 @@
7473	9629	break;
7474	9630	case QUIRK_SBZ:
7475	9631	case QUIRK_R3D:
7476		- if (spec->quirk == QUIRK_SBZ) {
7477		- codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
7478		- snd_hda_apply_pincfgs(codec, sbz_pincfgs);
7479		- }
7480		- if (spec->quirk == QUIRK_R3D) {
7481		- codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
7482		- snd_hda_apply_pincfgs(codec, r3d_pincfgs);
7483		- }
7484		-
7485	9632	spec->num_outputs = 2;
7486	9633	spec->out_pins[0] = 0x0B; /* Line out */
7487	9634	spec->out_pins[1] = 0x0F; /* Rear headphone out */
..	..	@@ -7506,10 +9653,63 @@
7506	9653	spec->multiout.dig_out_nid = spec->dig_out;
7507	9654	spec->dig_in = 0x09;
7508	9655	break;
7509		- case QUIRK_R3DI:
7510		- codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
7511		- snd_hda_apply_pincfgs(codec, r3di_pincfgs);
	9656	+ case QUIRK_ZXR:
	9657	+ spec->num_outputs = 2;
	9658	+ spec->out_pins[0] = 0x0B; /* Line out */
	9659	+ spec->out_pins[1] = 0x0F; /* Rear headphone out */
	9660	+ spec->out_pins[2] = 0x10; /* Center/LFE */
	9661	+ spec->out_pins[3] = 0x11; /* Rear surround */
	9662	+ spec->shared_out_nid = 0x2;
	9663	+ spec->unsol_tag_hp = spec->out_pins[1];
	9664	+ spec->unsol_tag_front_hp = spec->out_pins[2];
7512	9665
	9666	+ spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
	9667	+ spec->adcs[1] = 0x8; /* Not connected, no front mic */
	9668	+ spec->adcs[2] = 0xa; /* what u hear */
	9669	+
	9670	+ spec->num_inputs = 2;
	9671	+ spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
	9672	+ spec->input_pins[1] = 0x13; /* What U Hear */
	9673	+ spec->shared_mic_nid = 0x7;
	9674	+ spec->unsol_tag_amic1 = spec->input_pins[0];
	9675	+ break;
	9676	+ case QUIRK_ZXR_DBPRO:
	9677	+ spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
	9678	+
	9679	+ spec->num_inputs = 1;
	9680	+ spec->input_pins[0] = 0x11; /* RCA Line-in */
	9681	+
	9682	+ spec->dig_out = 0x05;
	9683	+ spec->multiout.dig_out_nid = spec->dig_out;
	9684	+
	9685	+ spec->dig_in = 0x09;
	9686	+ break;
	9687	+ case QUIRK_AE5:
	9688	+ case QUIRK_AE7:
	9689	+ spec->num_outputs = 2;
	9690	+ spec->out_pins[0] = 0x0B; /* Line out */
	9691	+ spec->out_pins[1] = 0x11; /* Rear headphone out */
	9692	+ spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
	9693	+ spec->out_pins[3] = 0x0F; /* Rear surround */
	9694	+ spec->shared_out_nid = 0x2;
	9695	+ spec->unsol_tag_hp = spec->out_pins[1];
	9696	+ spec->unsol_tag_front_hp = spec->out_pins[2];
	9697	+
	9698	+ spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
	9699	+ spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
	9700	+ spec->adcs[2] = 0xa; /* what u hear */
	9701	+
	9702	+ spec->num_inputs = 2;
	9703	+ spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
	9704	+ spec->input_pins[1] = 0x13; /* What U Hear */
	9705	+ spec->shared_mic_nid = 0x7;
	9706	+ spec->unsol_tag_amic1 = spec->input_pins[0];
	9707	+
	9708	+ /* SPDIF I/O */
	9709	+ spec->dig_out = 0x05;
	9710	+ spec->multiout.dig_out_nid = spec->dig_out;
	9711	+ break;
	9712	+ case QUIRK_R3DI:
7513	9713	spec->num_outputs = 2;
7514	9714	spec->out_pins[0] = 0x0B; /* Line out */
7515	9715	spec->out_pins[1] = 0x0F; /* Rear headphone out */
..	..	@@ -7566,7 +9766,11 @@
7566	9766	struct ca0132_spec *spec = codec->spec;
7567	9767
7568	9768	spec->chip_init_verbs = ca0132_init_verbs0;
7569		- if (spec->quirk == QUIRK_SBZ \|\| spec->quirk == QUIRK_R3D)
	9769	+ /*
	9770	+ * Since desktop cards use pci_mmio, this can be used to determine
	9771	+ * whether or not to use these verbs instead of a separate bool.
	9772	+ */
	9773	+ if (ca0132_use_pci_mmio(spec))
7570	9774	spec->desktop_init_verbs = ca0132_init_verbs1;
7571	9775	spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
7572	9776	sizeof(struct hda_verb),
..	..	@@ -7598,6 +9802,29 @@
7598	9802	return 0;
7599	9803	}
7600	9804
	9805	+/*
	9806	+ * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
	9807	+ * Sound Blaster Z cards. However, they have different HDA codec subsystem
	9808	+ * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
	9809	+ * daughter boards ID.
	9810	+ */
	9811	+static void sbz_detect_quirk(struct hda_codec *codec)
	9812	+{
	9813	+ struct ca0132_spec *spec = codec->spec;
	9814	+
	9815	+ switch (codec->core.subsystem_id) {
	9816	+ case 0x11020033:
	9817	+ spec->quirk = QUIRK_ZXR;
	9818	+ break;
	9819	+ case 0x1102003f:
	9820	+ spec->quirk = QUIRK_ZXR_DBPRO;
	9821	+ break;
	9822	+ default:
	9823	+ spec->quirk = QUIRK_SBZ;
	9824	+ break;
	9825	+ }
	9826	+}
	9827	+
7601	9828	static int patch_ca0132(struct hda_codec *codec)
7602	9829	{
7603	9830	struct ca0132_spec *spec;
..	..	@@ -7612,25 +9839,38 @@
7612	9839	codec->spec = spec;
7613	9840	spec->codec = codec;
7614	9841
7615		- codec->patch_ops = ca0132_patch_ops;
7616		- codec->pcm_format_first = 1;
7617		- codec->no_sticky_stream = 1;
7618		-
7619	9842	/* Detect codec quirk */
7620	9843	quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
7621	9844	if (quirk)
7622	9845	spec->quirk = quirk->value;
7623	9846	else
7624	9847	spec->quirk = QUIRK_NONE;
	9848	+ if (ca0132_quirk(spec) == QUIRK_SBZ)
	9849	+ sbz_detect_quirk(codec);
	9850	+
	9851	+ if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
	9852	+ codec->patch_ops = dbpro_patch_ops;
	9853	+ else
	9854	+ codec->patch_ops = ca0132_patch_ops;
	9855	+
	9856	+ codec->pcm_format_first = 1;
	9857	+ codec->no_sticky_stream = 1;
	9858	+
7625	9859
7626	9860	spec->dsp_state = DSP_DOWNLOAD_INIT;
7627	9861	spec->num_mixers = 1;
7628	9862
7629	9863	/* Set which mixers each quirk uses. */
7630		- switch (spec->quirk) {
	9864	+ switch (ca0132_quirk(spec)) {
7631	9865	case QUIRK_SBZ:
7632	9866	spec->mixers[0] = desktop_mixer;
7633	9867	snd_hda_codec_set_name(codec, "Sound Blaster Z");
	9868	+ break;
	9869	+ case QUIRK_ZXR:
	9870	+ spec->mixers[0] = desktop_mixer;
	9871	+ snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
	9872	+ break;
	9873	+ case QUIRK_ZXR_DBPRO:
7634	9874	break;
7635	9875	case QUIRK_R3D:
7636	9876	spec->mixers[0] = desktop_mixer;
..	..	@@ -7640,15 +9880,26 @@
7640	9880	spec->mixers[0] = r3di_mixer;
7641	9881	snd_hda_codec_set_name(codec, "Recon3Di");
7642	9882	break;
	9883	+ case QUIRK_AE5:
	9884	+ spec->mixers[0] = desktop_mixer;
	9885	+ snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
	9886	+ break;
	9887	+ case QUIRK_AE7:
	9888	+ spec->mixers[0] = desktop_mixer;
	9889	+ snd_hda_codec_set_name(codec, "Sound Blaster AE-7");
	9890	+ break;
7643	9891	default:
7644	9892	spec->mixers[0] = ca0132_mixer;
7645	9893	break;
7646	9894	}
7647	9895
7648	9896	/* Setup whether or not to use alt functions/controls/pci_mmio */
7649		- switch (spec->quirk) {
	9897	+ switch (ca0132_quirk(spec)) {
7650	9898	case QUIRK_SBZ:
7651	9899	case QUIRK_R3D:
	9900	+ case QUIRK_AE5:
	9901	+ case QUIRK_AE7:
	9902	+ case QUIRK_ZXR:
7652	9903	spec->use_alt_controls = true;
7653	9904	spec->use_alt_functions = true;
7654	9905	spec->use_pci_mmio = true;
..	..	@@ -7665,6 +9916,7 @@
7665	9916	break;
7666	9917	}
7667	9918
	9919	+#ifdef CONFIG_PCI
7668	9920	if (spec->use_pci_mmio) {
7669	9921	spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
7670	9922	if (spec->mem_base == NULL) {
..	..	@@ -7672,6 +9924,7 @@
7672	9924	spec->quirk = QUIRK_NONE;
7673	9925	}
7674	9926	}
	9927	+#endif
7675	9928
7676	9929	spec->base_init_verbs = ca0132_base_init_verbs;
7677	9930	spec->base_exit_verbs = ca0132_base_exit_verbs;
..	..	@@ -7700,7 +9953,7 @@
7700	9953	/*
7701	9954	* patch entries
7702	9955	*/
7703		-static struct hda_device_id snd_hda_id_ca0132[] = {
	9956	+static const struct hda_device_id snd_hda_id_ca0132[] = {
7704	9957	HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
7705	9958	{} /* terminator */
7706	9959	};