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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/include/uapi/linux/pci_regs.h
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@@ -1,7 +1,5 @@
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1
 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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2
 /*
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- *	pci_regs.h
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- *
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3
  *	PCI standard defines
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4
  *	Copyright 1994, Drew Eckhardt
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5
  *	Copyright 1997--1999 Martin Mares <mj@ucw.cz>
..
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@@ -15,7 +13,7 @@
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  *	PCI System Design Guide
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  *
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  *	For HyperTransport information, please consult the following manuals
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- *	from http://www.hypertransport.org
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+ *	from http://www.hypertransport.org :
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  *
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  *	The HyperTransport I/O Link Specification
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  */
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@@ -36,6 +34,7 @@
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  * of which the first 64 bytes are standardized as follows:
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  */
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 #define PCI_STD_HEADER_SIZEOF	64
37
+#define PCI_STD_NUM_BARS	6	/* Number of standard BARs */
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 #define PCI_VENDOR_ID		0x00	/* 16 bits */
40
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 #define PCI_DEVICE_ID		0x02	/* 16 bits */
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40
 #define PCI_COMMAND		0x04	/* 16 bits */
..
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@@ -52,6 +51,7 @@
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 #define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
53
52
 
54
53
 #define PCI_STATUS		0x06	/* 16 bits */
54
+#define  PCI_STATUS_IMM_READY	0x01	/* Immediate Readiness */
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 #define  PCI_STATUS_INTERRUPT	0x08	/* Interrupt status */
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56
 #define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
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 #define  PCI_STATUS_66MHZ	0x20	/* Support 66 MHz PCI 2.1 bus */
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@@ -76,6 +76,7 @@
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 #define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
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 #define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
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 #define PCI_HEADER_TYPE		0x0e	/* 8 bits */
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+#define  PCI_HEADER_TYPE_MASK		0x7f
79
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 #define  PCI_HEADER_TYPE_NORMAL		0
80
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 #define  PCI_HEADER_TYPE_BRIDGE		1
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 #define  PCI_HEADER_TYPE_CARDBUS	2
..
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@@ -246,7 +247,7 @@
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 #define  PCI_PM_CAP_PME_D0	0x0800	/* PME# from D0 */
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 #define  PCI_PM_CAP_PME_D1	0x1000	/* PME# from D1 */
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 #define  PCI_PM_CAP_PME_D2	0x2000	/* PME# from D2 */
249
-#define  PCI_PM_CAP_PME_D3	0x4000	/* PME# from D3 (hot) */
250
+#define  PCI_PM_CAP_PME_D3hot	0x4000	/* PME# from D3 (hot) */
250
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 #define  PCI_PM_CAP_PME_D3cold	0x8000	/* PME# from D3 (cold) */
251
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 #define  PCI_PM_CAP_PME_SHIFT	11	/* Start of the PME Mask in PMC */
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 #define PCI_PM_CTRL		4	/* PM control and status register */
..
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@@ -300,7 +301,7 @@
300
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 #define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
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 #define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
302
303
 
303
-/* Message Signalled Interrupts registers */
304
+/* Message Signalled Interrupt registers */
304
305
 
305
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 #define PCI_MSI_FLAGS		2	/* Message Control */
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 #define  PCI_MSI_FLAGS_ENABLE	0x0001	/* MSI feature enabled */
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@@ -318,7 +319,7 @@
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 #define PCI_MSI_MASK_64		16	/* Mask bits register for 64-bit devices */
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 #define PCI_MSI_PENDING_64	20	/* Pending intrs for 64-bit devices */
320
321
 
321
-/* MSI-X registers */
322
+/* MSI-X registers (in MSI-X capability) */
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 #define PCI_MSIX_FLAGS		2	/* Message Control */
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 #define  PCI_MSIX_FLAGS_QSIZE	0x07FF	/* Table size */
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 #define  PCI_MSIX_FLAGS_MASKALL	0x4000	/* Mask all vectors for this function */
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@@ -332,13 +333,13 @@
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 #define PCI_MSIX_FLAGS_BIRMASK	PCI_MSIX_PBA_BIR /* deprecated */
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 #define PCI_CAP_MSIX_SIZEOF	12	/* size of MSIX registers */
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335
 
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-/* MSI-X Table entry format */
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+/* MSI-X Table entry format (in memory mapped by a BAR) */
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 #define PCI_MSIX_ENTRY_SIZE		16
337
-#define  PCI_MSIX_ENTRY_LOWER_ADDR	0
338
-#define  PCI_MSIX_ENTRY_UPPER_ADDR	4
339
-#define  PCI_MSIX_ENTRY_DATA		8
340
-#define  PCI_MSIX_ENTRY_VECTOR_CTRL	12
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-#define   PCI_MSIX_ENTRY_CTRL_MASKBIT	1
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+#define PCI_MSIX_ENTRY_LOWER_ADDR	0  /* Message Address */
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+#define PCI_MSIX_ENTRY_UPPER_ADDR	4  /* Message Upper Address */
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+#define PCI_MSIX_ENTRY_DATA		8  /* Message Data */
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+#define PCI_MSIX_ENTRY_VECTOR_CTRL	12 /* Vector Control */
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+#define  PCI_MSIX_ENTRY_CTRL_MASKBIT	0x00000001
342
343
 
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 /* CompactPCI Hotswap Register */
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345
 
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@@ -371,6 +372,12 @@
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 #define PCI_EA_FIRST_ENT_BRIDGE	8	/* First EA Entry for Bridges */
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 #define  PCI_EA_ES		0x00000007 /* Entry Size */
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 #define  PCI_EA_BEI		0x000000f0 /* BAR Equivalent Indicator */
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+
376
+/* EA fixed Secondary and Subordinate bus numbers for Bridge */
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+#define PCI_EA_SEC_BUS_MASK	0xff
378
+#define PCI_EA_SUB_BUS_MASK	0xff00
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+#define PCI_EA_SUB_BUS_SHIFT	8
380
+
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 /* 0-5 map to BARs 0-5 respectively */
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 #define   PCI_EA_BEI_BAR0		0
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 #define   PCI_EA_BEI_BAR5		5
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@@ -464,19 +471,19 @@
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 /* PCI Express capability registers */
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472
 
466
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 #define PCI_EXP_FLAGS		2	/* Capabilities register */
467
-#define PCI_EXP_FLAGS_VERS	0x000f	/* Capability version */
468
-#define PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
469
-#define  PCI_EXP_TYPE_ENDPOINT	0x0	/* Express Endpoint */
470
-#define  PCI_EXP_TYPE_LEG_END	0x1	/* Legacy Endpoint */
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-#define  PCI_EXP_TYPE_ROOT_PORT 0x4	/* Root Port */
472
-#define  PCI_EXP_TYPE_UPSTREAM	0x5	/* Upstream Port */
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-#define  PCI_EXP_TYPE_DOWNSTREAM 0x6	/* Downstream Port */
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-#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7	/* PCIe to PCI/PCI-X Bridge */
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-#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8	/* PCI/PCI-X to PCIe Bridge */
476
-#define  PCI_EXP_TYPE_RC_END	0x9	/* Root Complex Integrated Endpoint */
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-#define  PCI_EXP_TYPE_RC_EC	0xa	/* Root Complex Event Collector */
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-#define PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
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-#define PCI_EXP_FLAGS_IRQ	0x3e00	/* Interrupt message number */
474
+#define  PCI_EXP_FLAGS_VERS	0x000f	/* Capability version */
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+#define  PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
476
+#define   PCI_EXP_TYPE_ENDPOINT	   0x0	/* Express Endpoint */
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+#define   PCI_EXP_TYPE_LEG_END	   0x1	/* Legacy Endpoint */
478
+#define   PCI_EXP_TYPE_ROOT_PORT   0x4	/* Root Port */
479
+#define   PCI_EXP_TYPE_UPSTREAM	   0x5	/* Upstream Port */
480
+#define   PCI_EXP_TYPE_DOWNSTREAM  0x6	/* Downstream Port */
481
+#define   PCI_EXP_TYPE_PCI_BRIDGE  0x7	/* PCIe to PCI/PCI-X Bridge */
482
+#define   PCI_EXP_TYPE_PCIE_BRIDGE 0x8	/* PCI/PCI-X to PCIe Bridge */
483
+#define   PCI_EXP_TYPE_RC_END	   0x9	/* Root Complex Integrated Endpoint */
484
+#define   PCI_EXP_TYPE_RC_EC	   0xa	/* Root Complex Event Collector */
485
+#define  PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
486
+#define  PCI_EXP_FLAGS_IRQ	0x3e00	/* Interrupt message number */
480
487
 #define PCI_EXP_DEVCAP		4	/* Device capabilities */
481
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 #define  PCI_EXP_DEVCAP_PAYLOAD	0x00000007 /* Max_Payload_Size */
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 #define  PCI_EXP_DEVCAP_PHANTOM	0x00000018 /* Phantom functions */
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@@ -529,8 +536,11 @@
529
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 #define  PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
530
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 #define  PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
531
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 #define  PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
539
+#define  PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */
532
540
 #define  PCI_EXP_LNKCAP_MLW	0x000003f0 /* Maximum Link Width */
533
541
 #define  PCI_EXP_LNKCAP_ASPMS	0x00000c00 /* ASPM Support */
542
+#define  PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */
543
+#define  PCI_EXP_LNKCAP_ASPM_L1  0x00000800 /* ASPM L1 Support */
534
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 #define  PCI_EXP_LNKCAP_L0SEL	0x00007000 /* L0s Exit Latency */
535
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 #define  PCI_EXP_LNKCAP_L1EL	0x00038000 /* L1 Exit Latency */
536
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 #define  PCI_EXP_LNKCAP_CLKPM	0x00040000 /* Clock Power Management */
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..
@@ -557,6 +567,7 @@
557
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 #define  PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
558
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 #define  PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
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 #define  PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */
570
+#define  PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */
560
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 #define  PCI_EXP_LNKSTA_NLW	0x03f0	/* Negotiated Link Width */
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 #define  PCI_EXP_LNKSTA_NLW_X1	0x0010	/* Current Link Width x1 */
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 #define  PCI_EXP_LNKSTA_NLW_X2	0x0020	/* Current Link Width x2 */
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@@ -590,6 +601,7 @@
590
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 #define  PCI_EXP_SLTCTL_CCIE	0x0010	/* Command Completed Interrupt Enable */
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 #define  PCI_EXP_SLTCTL_HPIE	0x0020	/* Hot-Plug Interrupt Enable */
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 #define  PCI_EXP_SLTCTL_AIC	0x00c0	/* Attention Indicator Control */
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+#define  PCI_EXP_SLTCTL_ATTN_IND_SHIFT 6      /* Attention Indicator shift */
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 #define  PCI_EXP_SLTCTL_ATTN_IND_ON    0x0040 /* Attention Indicator on */
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 #define  PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */
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 #define  PCI_EXP_SLTCTL_ATTN_IND_OFF   0x00c0 /* Attention Indicator off */
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@@ -602,6 +614,7 @@
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 #define  PCI_EXP_SLTCTL_PWR_OFF        0x0400 /* Power Off */
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 #define  PCI_EXP_SLTCTL_EIC	0x0800	/* Electromechanical Interlock Control */
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 #define  PCI_EXP_SLTCTL_DLLSCE	0x1000	/* Data Link Layer State Changed Enable */
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+#define  PCI_EXP_SLTCTL_IBPD_DISABLE	0x4000 /* In-band PD disable */
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 #define PCI_EXP_SLTSTA		26	/* Slot Status */
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619
 #define  PCI_EXP_SLTSTA_ABP	0x0001	/* Attention Button Pressed */
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 #define  PCI_EXP_SLTSTA_PFD	0x0002	/* Power Fault Detected */
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@@ -621,8 +634,8 @@
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 #define PCI_EXP_RTCAP		30	/* Root Capabilities */
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 #define  PCI_EXP_RTCAP_CRSVIS	0x0001	/* CRS Software Visibility capability */
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 #define PCI_EXP_RTSTA		32	/* Root Status */
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-#define PCI_EXP_RTSTA_PME	0x00010000 /* PME status */
625
-#define PCI_EXP_RTSTA_PENDING	0x00020000 /* PME pending */
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+#define  PCI_EXP_RTSTA_PME	0x00010000 /* PME status */
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+#define  PCI_EXP_RTSTA_PENDING	0x00020000 /* PME pending */
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 /*
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  * The Device Capabilities 2, Device Status 2, Device Control 2,
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  * Link Capabilities 2, Link Status 2, Link Control 2,
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@@ -642,13 +655,13 @@
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 #define  PCI_EXP_DEVCAP2_OBFF_MASK	0x000c0000 /* OBFF support mechanism */
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 #define  PCI_EXP_DEVCAP2_OBFF_MSG	0x00040000 /* New message signaling */
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 #define  PCI_EXP_DEVCAP2_OBFF_WAKE	0x00080000 /* Re-use WAKE# for OBFF */
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-#define PCI_EXP_DEVCAP2_EE_PREFIX	0x00200000 /* End-End TLP Prefix */
658
+#define  PCI_EXP_DEVCAP2_EE_PREFIX	0x00200000 /* End-End TLP Prefix */
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 #define PCI_EXP_DEVCTL2		40	/* Device Control 2 */
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 #define  PCI_EXP_DEVCTL2_COMP_TIMEOUT	0x000f	/* Completion Timeout Value */
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 #define  PCI_EXP_DEVCTL2_COMP_TMOUT_DIS	0x0010	/* Completion Timeout Disable */
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 #define  PCI_EXP_DEVCTL2_ARI		0x0020	/* Alternative Routing-ID */
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-#define PCI_EXP_DEVCTL2_ATOMIC_REQ	0x0040	/* Set Atomic requests */
651
-#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
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+#define  PCI_EXP_DEVCTL2_ATOMIC_REQ	0x0040	/* Set Atomic requests */
664
+#define  PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
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 #define  PCI_EXP_DEVCTL2_IDO_REQ_EN	0x0100	/* Allow IDO for requests */
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 #define  PCI_EXP_DEVCTL2_IDO_CMP_EN	0x0200	/* Allow IDO for completions */
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 #define  PCI_EXP_DEVCTL2_LTR_EN		0x0400	/* Enable LTR mechanism */
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@@ -662,17 +675,22 @@
662
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 #define  PCI_EXP_LNKCAP2_SLS_5_0GB	0x00000004 /* Supported Speed 5GT/s */
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 #define  PCI_EXP_LNKCAP2_SLS_8_0GB	0x00000008 /* Supported Speed 8GT/s */
664
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 #define  PCI_EXP_LNKCAP2_SLS_16_0GB	0x00000010 /* Supported Speed 16GT/s */
678
+#define  PCI_EXP_LNKCAP2_SLS_32_0GB	0x00000020 /* Supported Speed 32GT/s */
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 #define  PCI_EXP_LNKCAP2_CROSSLINK	0x00000100 /* Crosslink supported */
666
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 #define PCI_EXP_LNKCTL2		48	/* Link Control 2 */
667
-#define PCI_EXP_LNKCTL2_TLS		0x000f
668
-#define PCI_EXP_LNKCTL2_TLS_2_5GT	0x0001 /* Supported Speed 2.5GT/s */
669
-#define PCI_EXP_LNKCTL2_TLS_5_0GT	0x0002 /* Supported Speed 5GT/s */
670
-#define PCI_EXP_LNKCTL2_TLS_8_0GT	0x0003 /* Supported Speed 8GT/s */
671
-#define PCI_EXP_LNKCTL2_TLS_16_0GT	0x0004 /* Supported Speed 16GT/s */
672
-#define PCI_EXP_LNKCTL2_HASD		0x0020 /* HW Autonomous Speed Disable */
681
+#define  PCI_EXP_LNKCTL2_TLS		0x000f
682
+#define  PCI_EXP_LNKCTL2_TLS_2_5GT	0x0001 /* Supported Speed 2.5GT/s */
683
+#define  PCI_EXP_LNKCTL2_TLS_5_0GT	0x0002 /* Supported Speed 5GT/s */
684
+#define  PCI_EXP_LNKCTL2_TLS_8_0GT	0x0003 /* Supported Speed 8GT/s */
685
+#define  PCI_EXP_LNKCTL2_TLS_16_0GT	0x0004 /* Supported Speed 16GT/s */
686
+#define  PCI_EXP_LNKCTL2_TLS_32_0GT	0x0005 /* Supported Speed 32GT/s */
687
+#define  PCI_EXP_LNKCTL2_ENTER_COMP	0x0010 /* Enter Compliance */
688
+#define  PCI_EXP_LNKCTL2_TX_MARGIN	0x0380 /* Transmit Margin */
689
+#define  PCI_EXP_LNKCTL2_HASD		0x0020 /* HW Autonomous Speed Disable */
673
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 #define PCI_EXP_LNKSTA2		50	/* Link Status 2 */
674
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 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2	52	/* v2 endpoints with link end here */
675
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 #define PCI_EXP_SLTCAP2		52	/* Slot Capabilities 2 */
693
+#define  PCI_EXP_SLTCAP2_IBPD	0x00000001 /* In-band PD Disable Supported */
676
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 #define PCI_EXP_SLTCTL2		56	/* Slot Control 2 */
677
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 #define PCI_EXP_SLTSTA2		58	/* Slot Status 2 */
678
696
 
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@@ -711,7 +729,9 @@
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 #define PCI_EXT_CAP_ID_DPC	0x1D	/* Downstream Port Containment */
712
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 #define PCI_EXT_CAP_ID_L1SS	0x1E	/* L1 PM Substates */
713
731
 #define PCI_EXT_CAP_ID_PTM	0x1F	/* Precision Time Measurement */
714
-#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PTM
732
+#define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */
733
+#define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */
734
+#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PL_16GT
715
735
 
716
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 #define PCI_EXT_CAP_DSN_SIZEOF	12
717
737
 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
..
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@@ -758,18 +778,18 @@
758
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 #define  PCI_ERR_CAP_ECRC_CHKE	0x00000100	/* ECRC Check Enable */
759
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 #define PCI_ERR_HEADER_LOG	28	/* Header Log Register (16 bytes) */
760
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 #define PCI_ERR_ROOT_COMMAND	44	/* Root Error Command */
761
-#define PCI_ERR_ROOT_CMD_COR_EN		0x00000001 /* Correctable Err Reporting Enable */
762
-#define PCI_ERR_ROOT_CMD_NONFATAL_EN	0x00000002 /* Non-Fatal Err Reporting Enable */
763
-#define PCI_ERR_ROOT_CMD_FATAL_EN	0x00000004 /* Fatal Err Reporting Enable */
781
+#define  PCI_ERR_ROOT_CMD_COR_EN	0x00000001 /* Correctable Err Reporting Enable */
782
+#define  PCI_ERR_ROOT_CMD_NONFATAL_EN	0x00000002 /* Non-Fatal Err Reporting Enable */
783
+#define  PCI_ERR_ROOT_CMD_FATAL_EN	0x00000004 /* Fatal Err Reporting Enable */
764
784
 #define PCI_ERR_ROOT_STATUS	48
765
-#define PCI_ERR_ROOT_COR_RCV		0x00000001 /* ERR_COR Received */
766
-#define PCI_ERR_ROOT_MULTI_COR_RCV	0x00000002 /* Multiple ERR_COR */
767
-#define PCI_ERR_ROOT_UNCOR_RCV		0x00000004 /* ERR_FATAL/NONFATAL */
768
-#define PCI_ERR_ROOT_MULTI_UNCOR_RCV	0x00000008 /* Multiple FATAL/NONFATAL */
769
-#define PCI_ERR_ROOT_FIRST_FATAL	0x00000010 /* First UNC is Fatal */
770
-#define PCI_ERR_ROOT_NONFATAL_RCV	0x00000020 /* Non-Fatal Received */
771
-#define PCI_ERR_ROOT_FATAL_RCV		0x00000040 /* Fatal Received */
772
-#define PCI_ERR_ROOT_AER_IRQ		0xf8000000 /* Advanced Error Interrupt Message Number */
785
+#define  PCI_ERR_ROOT_COR_RCV		0x00000001 /* ERR_COR Received */
786
+#define  PCI_ERR_ROOT_MULTI_COR_RCV	0x00000002 /* Multiple ERR_COR */
787
+#define  PCI_ERR_ROOT_UNCOR_RCV		0x00000004 /* ERR_FATAL/NONFATAL */
788
+#define  PCI_ERR_ROOT_MULTI_UNCOR_RCV	0x00000008 /* Multiple FATAL/NONFATAL */
789
+#define  PCI_ERR_ROOT_FIRST_FATAL	0x00000010 /* First UNC is Fatal */
790
+#define  PCI_ERR_ROOT_NONFATAL_RCV	0x00000020 /* Non-Fatal Received */
791
+#define  PCI_ERR_ROOT_FATAL_RCV		0x00000040 /* Fatal Received */
792
+#define  PCI_ERR_ROOT_AER_IRQ		0xf8000000 /* Advanced Error Interrupt Message Number */
773
793
 #define PCI_ERR_ROOT_ERR_SRC	52	/* Error Source Identification */
774
794
 
775
795
 /* Virtual Channel */
..
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@@ -816,6 +836,13 @@
816
836
 #define PCI_PWR_CAP		12	/* Capability */
817
837
 #define  PCI_PWR_CAP_BUDGET(x)	((x) & 1)	/* Included in system budget */
818
838
 #define PCI_EXT_CAP_PWR_SIZEOF	16
839
+
840
+/* Root Complex Event Collector Endpoint Association  */
841
+#define PCI_RCEC_RCIEP_BITMAP	4	/* Associated Bitmap for RCiEPs */
842
+#define PCI_RCEC_BUSN		8	/* RCEC Associated Bus Numbers */
843
+#define  PCI_RCEC_BUSN_REG_VER	0x02	/* Least version with BUSN present */
844
+#define  PCI_RCEC_BUSN_NEXT(x)	(((x) >> 8) & 0xff)
845
+#define  PCI_RCEC_BUSN_LAST(x)	(((x) >> 16) & 0xff)
819
846
 
820
847
 /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */
821
848
 #define PCI_VNDR_HEADER		4	/* Vendor-Specific Header */
..
..
@@ -872,6 +899,7 @@
872
899
 #define PCI_ATS_CAP		0x04	/* ATS Capability Register */
873
900
 #define  PCI_ATS_CAP_QDEP(x)	((x) & 0x1f)	/* Invalidate Queue Depth */
874
901
 #define  PCI_ATS_MAX_QDEP	32	/* Max Invalidate Queue Depth */
902
+#define  PCI_ATS_CAP_PAGE_ALIGNED	0x0020 /* Page Aligned Request */
875
903
 #define PCI_ATS_CTRL		0x06	/* ATS Control Register */
876
904
 #define  PCI_ATS_CTRL_ENABLE	0x8000	/* ATS Enable */
877
905
 #define  PCI_ATS_CTRL_STU(x)	((x) & 0x1f)	/* Smallest Translation Unit */
..
..
@@ -880,12 +908,13 @@
880
908
 
881
909
 /* Page Request Interface */
882
910
 #define PCI_PRI_CTRL		0x04	/* PRI control register */
883
-#define  PCI_PRI_CTRL_ENABLE	0x01	/* Enable */
884
-#define  PCI_PRI_CTRL_RESET	0x02	/* Reset */
911
+#define  PCI_PRI_CTRL_ENABLE	0x0001	/* Enable */
912
+#define  PCI_PRI_CTRL_RESET	0x0002	/* Reset */
885
913
 #define PCI_PRI_STATUS		0x06	/* PRI status register */
886
-#define  PCI_PRI_STATUS_RF	0x001	/* Response Failure */
887
-#define  PCI_PRI_STATUS_UPRGI	0x002	/* Unexpected PRG index */
888
-#define  PCI_PRI_STATUS_STOPPED	0x100	/* PRI Stopped */
914
+#define  PCI_PRI_STATUS_RF	0x0001	/* Response Failure */
915
+#define  PCI_PRI_STATUS_UPRGI	0x0002	/* Unexpected PRG index */
916
+#define  PCI_PRI_STATUS_STOPPED	0x0100	/* PRI Stopped */
917
+#define  PCI_PRI_STATUS_PASID	0x8000	/* PRG Response PASID Required */
889
918
 #define PCI_PRI_MAX_REQ		0x08	/* PRI max reqs supported */
890
919
 #define PCI_PRI_ALLOC_REQ	0x0c	/* PRI max reqs allowed */
891
920
 #define PCI_EXT_CAP_PRI_SIZEOF	16
..
..
@@ -902,16 +931,16 @@
902
931
 
903
932
 /* Single Root I/O Virtualization */
904
933
 #define PCI_SRIOV_CAP		0x04	/* SR-IOV Capabilities */
905
-#define  PCI_SRIOV_CAP_VFM	0x01	/* VF Migration Capable */
934
+#define  PCI_SRIOV_CAP_VFM	0x00000001  /* VF Migration Capable */
906
935
 #define  PCI_SRIOV_CAP_INTR(x)	((x) >> 21) /* Interrupt Message Number */
907
936
 #define PCI_SRIOV_CTRL		0x08	/* SR-IOV Control */
908
-#define  PCI_SRIOV_CTRL_VFE	0x01	/* VF Enable */
909
-#define  PCI_SRIOV_CTRL_VFM	0x02	/* VF Migration Enable */
910
-#define  PCI_SRIOV_CTRL_INTR	0x04	/* VF Migration Interrupt Enable */
911
-#define  PCI_SRIOV_CTRL_MSE	0x08	/* VF Memory Space Enable */
912
-#define  PCI_SRIOV_CTRL_ARI	0x10	/* ARI Capable Hierarchy */
937
+#define  PCI_SRIOV_CTRL_VFE	0x0001	/* VF Enable */
938
+#define  PCI_SRIOV_CTRL_VFM	0x0002	/* VF Migration Enable */
939
+#define  PCI_SRIOV_CTRL_INTR	0x0004	/* VF Migration Interrupt Enable */
940
+#define  PCI_SRIOV_CTRL_MSE	0x0008	/* VF Memory Space Enable */
941
+#define  PCI_SRIOV_CTRL_ARI	0x0010	/* ARI Capable Hierarchy */
913
942
 #define PCI_SRIOV_STATUS	0x0a	/* SR-IOV Status */
914
-#define  PCI_SRIOV_STATUS_VFM	0x01	/* VF Migration Status */
943
+#define  PCI_SRIOV_STATUS_VFM	0x0001	/* VF Migration Status */
915
944
 #define PCI_SRIOV_INITIAL_VF	0x0c	/* Initial VFs */
916
945
 #define PCI_SRIOV_TOTAL_VF	0x0e	/* Total VFs */
917
946
 #define PCI_SRIOV_NUM_VF	0x10	/* Number of VFs */
..
..
@@ -941,13 +970,13 @@
941
970
 
942
971
 /* Access Control Service */
943
972
 #define PCI_ACS_CAP		0x04	/* ACS Capability Register */
944
-#define  PCI_ACS_SV		0x01	/* Source Validation */
945
-#define  PCI_ACS_TB		0x02	/* Translation Blocking */
946
-#define  PCI_ACS_RR		0x04	/* P2P Request Redirect */
947
-#define  PCI_ACS_CR		0x08	/* P2P Completion Redirect */
948
-#define  PCI_ACS_UF		0x10	/* Upstream Forwarding */
949
-#define  PCI_ACS_EC		0x20	/* P2P Egress Control */
950
-#define  PCI_ACS_DT		0x40	/* Direct Translated P2P */
973
+#define  PCI_ACS_SV		0x0001	/* Source Validation */
974
+#define  PCI_ACS_TB		0x0002	/* Translation Blocking */
975
+#define  PCI_ACS_RR		0x0004	/* P2P Request Redirect */
976
+#define  PCI_ACS_CR		0x0008	/* P2P Completion Redirect */
977
+#define  PCI_ACS_UF		0x0010	/* Upstream Forwarding */
978
+#define  PCI_ACS_EC		0x0020	/* P2P Egress Control */
979
+#define  PCI_ACS_DT		0x0040	/* Direct Translated P2P */
951
980
 #define PCI_ACS_EGRESS_BITS	0x05	/* ACS Egress Control Vector Size */
952
981
 #define PCI_ACS_CTRL		0x06	/* ACS Control Register */
953
982
 #define PCI_ACS_EGRESS_CTL_V	0x08	/* ACS Egress Control Vector */
..
..
@@ -997,9 +1026,9 @@
997
1026
 #define  PCI_EXP_DPC_CAP_DL_ACTIVE	0x1000	/* ERR_COR signal on DL_Active supported */
998
1027
 
999
1028
 #define PCI_EXP_DPC_CTL			6	/* DPC control */
1000
-#define  PCI_EXP_DPC_CTL_EN_FATAL 	0x0001	/* Enable trigger on ERR_FATAL message */
1001
-#define  PCI_EXP_DPC_CTL_EN_NONFATAL 	0x0002	/* Enable trigger on ERR_NONFATAL message */
1002
-#define  PCI_EXP_DPC_CTL_INT_EN 	0x0008	/* DPC Interrupt Enable */
1029
+#define  PCI_EXP_DPC_CTL_EN_FATAL	0x0001	/* Enable trigger on ERR_FATAL message */
1030
+#define  PCI_EXP_DPC_CTL_EN_NONFATAL	0x0002	/* Enable trigger on ERR_NONFATAL message */
1031
+#define  PCI_EXP_DPC_CTL_INT_EN		0x0008	/* DPC Interrupt Enable */
1003
1032
 
1004
1033
 #define PCI_EXP_DPC_STATUS		8	/* DPC Status */
1005
1034
 #define  PCI_EXP_DPC_STATUS_TRIGGER	    0x0001 /* Trigger Status */
..
..
@@ -1043,10 +1072,21 @@
1043
1072
 #define  PCI_L1SS_CTL1_PCIPM_L1_1	0x00000002  /* PCI-PM L1.1 Enable */
1044
1073
 #define  PCI_L1SS_CTL1_ASPM_L1_2	0x00000004  /* ASPM L1.2 Enable */
1045
1074
 #define  PCI_L1SS_CTL1_ASPM_L1_1	0x00000008  /* ASPM L1.1 Enable */
1075
+#define  PCI_L1SS_CTL1_L1_2_MASK	0x00000005
1046
1076
 #define  PCI_L1SS_CTL1_L1SS_MASK	0x0000000f
1047
1077
 #define  PCI_L1SS_CTL1_CM_RESTORE_TIME	0x0000ff00  /* Common_Mode_Restore_Time */
1048
1078
 #define  PCI_L1SS_CTL1_LTR_L12_TH_VALUE	0x03ff0000  /* LTR_L1.2_THRESHOLD_Value */
1049
1079
 #define  PCI_L1SS_CTL1_LTR_L12_TH_SCALE	0xe0000000  /* LTR_L1.2_THRESHOLD_Scale */
1050
1080
 #define PCI_L1SS_CTL2		0x0c	/* Control 2 Register */
1051
1081
 
1082
+/* Data Link Feature */
1083
+#define PCI_DLF_CAP		0x04	/* Capabilities Register */
1084
+#define  PCI_DLF_EXCHANGE_ENABLE	0x80000000  /* Data Link Feature Exchange Enable */
1085
+
1086
+/* Physical Layer 16.0 GT/s */
1087
+#define PCI_PL_16GT_LE_CTRL	0x20	/* Lane Equalization Control Register */
1088
+#define  PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK		0x0000000F
1089
+#define  PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK		0x000000F0
1090
+#define  PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT	4
1091
+
1052
1092
 #endif /* LINUX_PCI_REGS_H */