~hc/RK356X_SDK_RELEASE.git

..	..	@@ -55,12 +55,34 @@
55	55	* cause the related events to not be seen.
56	56	*
57	57	* I915_RESET_UEVENT - Event is generated just before an attempt to reset the
58		- * the GPU. The value supplied with the event is always 1. NOTE: Disable
	58	+ * GPU. The value supplied with the event is always 1. NOTE: Disable
59	59	* reset via module parameter will cause this event to not be seen.
60	60	*/
61	61	#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
62	62	#define I915_ERROR_UEVENT "ERROR"
63	63	#define I915_RESET_UEVENT "RESET"
	64	+
	65	+/*
	66	+ * i915_user_extension: Base class for defining a chain of extensions
	67	+ *
	68	+ * Many interfaces need to grow over time. In most cases we can simply
	69	+ * extend the struct and have userspace pass in more data. Another option,
	70	+ * as demonstrated by Vulkan's approach to providing extensions for forward
	71	+ * and backward compatibility, is to use a list of optional structs to
	72	+ * provide those extra details.
	73	+ *
	74	+ * The key advantage to using an extension chain is that it allows us to
	75	+ * redefine the interface more easily than an ever growing struct of
	76	+ * increasing complexity, and for large parts of that interface to be
	77	+ * entirely optional. The downside is more pointer chasing; chasing across
	78	+ * the __user boundary with pointers encapsulated inside u64.
	79	+ */
	80	+struct i915_user_extension {
	81	+ __u64 next_extension;
	82	+ __u32 name;
	83	+ __u32 flags; /* All undefined bits must be zero. */
	84	+ __u32 rsvd[4]; /* Reserved for future use; must be zero. */
	85	+};
64	86
65	87	/*
66	88	* MOCS indexes used for GPU surfaces, defining the cacheability of the
..	..	@@ -99,7 +121,23 @@
99	121	I915_ENGINE_CLASS_VIDEO = 2,
100	122	I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
101	123
	124	+ /* should be kept compact */
	125	+
102	126	I915_ENGINE_CLASS_INVALID = -1
	127	+};
	128	+
	129	+/*
	130	+ * There may be more than one engine fulfilling any role within the system.
	131	+ * Each engine of a class is given a unique instance number and therefore
	132	+ * any engine can be specified by its class:instance tuplet. APIs that allow
	133	+ * access to any engine in the system will use struct i915_engine_class_instance
	134	+ * for this identification.
	135	+ */
	136	+struct i915_engine_class_instance {
	137	+ __u16 engine_class; /* see enum drm_i915_gem_engine_class */
	138	+ __u16 engine_instance;
	139	+#define I915_ENGINE_CLASS_INVALID_NONE -1
	140	+#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
103	141	};
104	142
105	143	/**
..	..	@@ -319,6 +357,9 @@
319	357	#define DRM_I915_PERF_ADD_CONFIG 0x37
320	358	#define DRM_I915_PERF_REMOVE_CONFIG 0x38
321	359	#define DRM_I915_QUERY 0x39
	360	+#define DRM_I915_GEM_VM_CREATE 0x3a
	361	+#define DRM_I915_GEM_VM_DESTROY 0x3b
	362	+/* Must be kept compact -- no holes */
322	363
323	364	#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
324	365	#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
..	..	@@ -354,6 +395,7 @@
354	395	#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
355	396	#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
356	397	#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
	398	+#define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset)
357	399	#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
358	400	#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
359	401	#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
..	..	@@ -367,6 +409,7 @@
367	409	#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
368	410	#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
369	411	#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
	412	+#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
370	413	#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
371	414	#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
372	415	#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
..	..	@@ -377,6 +420,8 @@
377	420	#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
378	421	#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
379	422	#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
	423	+#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
	424	+#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
380	425
381	426	/* Allow drivers to submit batchbuffers directly to hardware, relying
382	427	* on the security mechanisms provided by hardware.
..	..	@@ -411,6 +456,14 @@
411	456	typedef struct drm_i915_irq_wait {
412	457	int irq_seq;
413	458	} drm_i915_irq_wait_t;
	459	+
	460	+/*
	461	+ * Different modes of per-process Graphics Translation Table,
	462	+ * see I915_PARAM_HAS_ALIASING_PPGTT
	463	+ */
	464	+#define I915_GEM_PPGTT_NONE 0
	465	+#define I915_GEM_PPGTT_ALIASING 1
	466	+#define I915_GEM_PPGTT_FULL 2
414	467
415	468	/* Ioctl to query kernel params:
416	469	*/
..	..	@@ -468,6 +521,8 @@
468	521	#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
469	522	#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
470	523	#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
	524	+#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
	525	+#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
471	526
472	527	#define I915_PARAM_HUC_STATUS 42
473	528
..	..	@@ -529,6 +584,49 @@
529	584	*/
530	585	#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
531	586
	587	+/*
	588	+ * Once upon a time we supposed that writes through the GGTT would be
	589	+ * immediately in physical memory (once flushed out of the CPU path). However,
	590	+ * on a few different processors and chipsets, this is not necessarily the case
	591	+ * as the writes appear to be buffered internally. Thus a read of the backing
	592	+ * storage (physical memory) via a different path (with different physical tags
	593	+ * to the indirect write via the GGTT) will see stale values from before
	594	+ * the GGTT write. Inside the kernel, we can for the most part keep track of
	595	+ * the different read/write domains in use (e.g. set-domain), but the assumption
	596	+ * of coherency is baked into the ABI, hence reporting its true state in this
	597	+ * parameter.
	598	+ *
	599	+ * Reports true when writes via mmap_gtt are immediately visible following an
	600	+ * lfence to flush the WCB.
	601	+ *
	602	+ * Reports false when writes via mmap_gtt are indeterminately delayed in an in
	603	+ * internal buffer and are _not_ immediately visible to third parties accessing
	604	+ * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
	605	+ * communications channel when reporting false is strongly disadvised.
	606	+ */
	607	+#define I915_PARAM_MMAP_GTT_COHERENT 52
	608	+
	609	+/*
	610	+ * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
	611	+ * execution through use of explicit fence support.
	612	+ * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
	613	+ */
	614	+#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
	615	+
	616	+/*
	617	+ * Revision of the i915-perf uAPI. The value returned helps determine what
	618	+ * i915-perf features are available. See drm_i915_perf_property_id.
	619	+ */
	620	+#define I915_PARAM_PERF_REVISION 54
	621	+
	622	+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
	623	+ * timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See
	624	+ * I915_EXEC_USE_EXTENSIONS.
	625	+ */
	626	+#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
	627	+
	628	+/* Must be kept compact -- no holes and well documented */
	629	+
532	630	typedef struct drm_i915_getparam {
533	631	__s32 param;
534	632	/*
..	..	@@ -544,6 +642,7 @@
544	642	#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
545	643	#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
546	644	#define I915_SETPARAM_NUM_USED_FENCES 4
	645	+/* Must be kept compact -- no holes */
547	646
548	647	typedef struct drm_i915_setparam {
549	648	int param;
..	..	@@ -699,6 +798,37 @@
699	798	* This is a fixed-size type for 32/64 compatibility.
700	799	*/
701	800	__u64 offset;
	801	+};
	802	+
	803	+struct drm_i915_gem_mmap_offset {
	804	+ /** Handle for the object being mapped. */
	805	+ __u32 handle;
	806	+ __u32 pad;
	807	+ /**
	808	+ * Fake offset to use for subsequent mmap call
	809	+ *
	810	+ * This is a fixed-size type for 32/64 compatibility.
	811	+ */
	812	+ __u64 offset;
	813	+
	814	+ /**
	815	+ * Flags for extended behaviour.
	816	+ *
	817	+ * It is mandatory that one of the MMAP_OFFSET types
	818	+ * (GTT, WC, WB, UC, etc) should be included.
	819	+ */
	820	+ __u64 flags;
	821	+#define I915_MMAP_OFFSET_GTT 0
	822	+#define I915_MMAP_OFFSET_WC 1
	823	+#define I915_MMAP_OFFSET_WB 2
	824	+#define I915_MMAP_OFFSET_UC 3
	825	+
	826	+ /*
	827	+ * Zero-terminated chain of extensions.
	828	+ *
	829	+ * No current extensions defined; mbz.
	830	+ */
	831	+ __u64 extensions;
702	832	};
703	833
704	834	struct drm_i915_gem_set_domain {
..	..	@@ -922,6 +1052,38 @@
922	1052	__u32 flags;
923	1053	};
924	1054
	1055	+/**
	1056	+ * See drm_i915_gem_execbuffer_ext_timeline_fences.
	1057	+ */
	1058	+#define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
	1059	+
	1060	+/**
	1061	+ * This structure describes an array of drm_syncobj and associated points for
	1062	+ * timeline variants of drm_syncobj. It is invalid to append this structure to
	1063	+ * the execbuf if I915_EXEC_FENCE_ARRAY is set.
	1064	+ */
	1065	+struct drm_i915_gem_execbuffer_ext_timeline_fences {
	1066	+ struct i915_user_extension base;
	1067	+
	1068	+ /**
	1069	+ * Number of element in the handles_ptr & value_ptr arrays.
	1070	+ */
	1071	+ __u64 fence_count;
	1072	+
	1073	+ /**
	1074	+ * Pointer to an array of struct drm_i915_gem_exec_fence of length
	1075	+ * fence_count.
	1076	+ */
	1077	+ __u64 handles_ptr;
	1078	+
	1079	+ /**
	1080	+ * Pointer to an array of u64 values of length fence_count. Values
	1081	+ * must be 0 for a binary drm_syncobj. A Value of 0 for a timeline
	1082	+ * drm_syncobj is invalid as it turns a drm_syncobj into a binary one.
	1083	+ */
	1084	+ __u64 values_ptr;
	1085	+};
	1086	+
925	1087	struct drm_i915_gem_execbuffer2 {
926	1088	/**
927	1089	* List of gem_exec_object2 structs
..	..	@@ -938,8 +1100,14 @@
938	1100	__u32 num_cliprects;
939	1101	/**
940	1102	* This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
941		- * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a
942		- * struct drm_i915_gem_exec_fence *fences.
	1103	+ * & I915_EXEC_USE_EXTENSIONS are not set.
	1104	+ *
	1105	+ * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array
	1106	+ * of struct drm_i915_gem_exec_fence and num_cliprects is the length
	1107	+ * of the array.
	1108	+ *
	1109	+ * If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a
	1110	+ * single struct i915_user_extension and num_cliprects is 0.
943	1111	*/
944	1112	__u64 cliprects_ptr;
945	1113	#define I915_EXEC_RING_MASK (0x3f)
..	..	@@ -1048,7 +1216,25 @@
1048	1216	*/
1049	1217	#define I915_EXEC_FENCE_ARRAY (1<<19)
1050	1218
1051		-#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
	1219	+/*
	1220	+ * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
	1221	+ * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
	1222	+ * the batch.
	1223	+ *
	1224	+ * Returns -EINVAL if the sync_file fd cannot be found.
	1225	+ */
	1226	+#define I915_EXEC_FENCE_SUBMIT (1 << 20)
	1227	+
	1228	+/*
	1229	+ * Setting I915_EXEC_USE_EXTENSIONS implies that
	1230	+ * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked
	1231	+ * list of i915_user_extension. Each i915_user_extension node is the base of a
	1232	+ * larger structure. The list of supported structures are listed in the
	1233	+ * drm_i915_gem_execbuffer_ext enum.
	1234	+ */
	1235	+#define I915_EXEC_USE_EXTENSIONS (1 << 21)
	1236	+
	1237	+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1))
1052	1238
1053	1239	#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
1054	1240	#define i915_execbuffer2_set_context_id(eb2, context) \
..	..	@@ -1090,32 +1276,34 @@
1090	1276	* as busy may become idle before the ioctl is completed.
1091	1277	*
1092	1278	* Furthermore, if the object is busy, which engine is busy is only
1093		- * provided as a guide. There are race conditions which prevent the
1094		- * report of which engines are busy from being always accurate.
1095		- * However, the converse is not true. If the object is idle, the
1096		- * result of the ioctl, that all engines are idle, is accurate.
	1279	+ * provided as a guide and only indirectly by reporting its class
	1280	+ * (there may be more than one engine in each class). There are race
	1281	+ * conditions which prevent the report of which engines are busy from
	1282	+ * being always accurate. However, the converse is not true. If the
	1283	+ * object is idle, the result of the ioctl, that all engines are idle,
	1284	+ * is accurate.
1097	1285	*
1098	1286	* The returned dword is split into two fields to indicate both
1099		- * the engines on which the object is being read, and the
1100		- * engine on which it is currently being written (if any).
	1287	+ * the engine classess on which the object is being read, and the
	1288	+ * engine class on which it is currently being written (if any).
1101	1289	*
1102	1290	* The low word (bits 0:15) indicate if the object is being written
1103	1291	* to by any engine (there can only be one, as the GEM implicit
1104	1292	* synchronisation rules force writes to be serialised). Only the
1105		- * engine for the last write is reported.
	1293	+ * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
	1294	+ * 1 not 0 etc) for the last write is reported.
1106	1295	*
1107		- * The high word (bits 16:31) are a bitmask of which engines are
1108		- * currently reading from the object. Multiple engines may be
	1296	+ * The high word (bits 16:31) are a bitmask of which engines classes
	1297	+ * are currently reading from the object. Multiple engines may be
1109	1298	* reading from the object simultaneously.
1110	1299	*
1111		- * The value of each engine is the same as specified in the
1112		- * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
1113		- * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
1114		- * the I915_EXEC_RENDER engine for execution, and so it is never
	1300	+ * The value of each engine class is the same as specified in the
	1301	+ * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
	1302	+ * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
1115	1303	* reported as active itself. Some hardware may have parallel
1116	1304	* execution engines, e.g. multiple media engines, which are
1117		- * mapped to the same identifier in the EXECBUFFER2 ioctl and
1118		- * so are not separately reported for busyness.
	1305	+ * mapped to the same class identifier and so are not separately
	1306	+ * reported for busyness.
1119	1307	*
1120	1308	* Caveat emptor:
1121	1309	* Only the boolean result of this query is reliable; that is whether
..	..	@@ -1382,14 +1570,332 @@
1382	1570	};
1383	1571
1384	1572	struct drm_i915_gem_context_create {
1385		- /* output: id of new context*/
1386		- __u32 ctx_id;
	1573	+ __u32 ctx_id; /* output: id of new context*/
1387	1574	__u32 pad;
	1575	+};
	1576	+
	1577	+struct drm_i915_gem_context_create_ext {
	1578	+ __u32 ctx_id; /* output: id of new context*/
	1579	+ __u32 flags;
	1580	+#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
	1581	+#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
	1582	+#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
	1583	+ (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
	1584	+ __u64 extensions;
	1585	+};
	1586	+
	1587	+struct drm_i915_gem_context_param {
	1588	+ __u32 ctx_id;
	1589	+ __u32 size;
	1590	+ __u64 param;
	1591	+#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
	1592	+#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
	1593	+#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
	1594	+#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
	1595	+#define I915_CONTEXT_PARAM_BANNABLE 0x5
	1596	+#define I915_CONTEXT_PARAM_PRIORITY 0x6
	1597	+#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
	1598	+#define I915_CONTEXT_DEFAULT_PRIORITY 0
	1599	+#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
	1600	+ /*
	1601	+ * When using the following param, value should be a pointer to
	1602	+ * drm_i915_gem_context_param_sseu.
	1603	+ */
	1604	+#define I915_CONTEXT_PARAM_SSEU 0x7
	1605	+
	1606	+/*
	1607	+ * Not all clients may want to attempt automatic recover of a context after
	1608	+ * a hang (for example, some clients may only submit very small incremental
	1609	+ * batches relying on known logical state of previous batches which will never
	1610	+ * recover correctly and each attempt will hang), and so would prefer that
	1611	+ * the context is forever banned instead.
	1612	+ *
	1613	+ * If set to false (0), after a reset, subsequent (and in flight) rendering
	1614	+ * from this context is discarded, and the client will need to create a new
	1615	+ * context to use instead.
	1616	+ *
	1617	+ * If set to true (1), the kernel will automatically attempt to recover the
	1618	+ * context by skipping the hanging batch and executing the next batch starting
	1619	+ * from the default context state (discarding the incomplete logical context
	1620	+ * state lost due to the reset).
	1621	+ *
	1622	+ * On creation, all new contexts are marked as recoverable.
	1623	+ */
	1624	+#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
	1625	+
	1626	+ /*
	1627	+ * The id of the associated virtual memory address space (ppGTT) of
	1628	+ * this context. Can be retrieved and passed to another context
	1629	+ * (on the same fd) for both to use the same ppGTT and so share
	1630	+ * address layouts, and avoid reloading the page tables on context
	1631	+ * switches between themselves.
	1632	+ *
	1633	+ * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
	1634	+ */
	1635	+#define I915_CONTEXT_PARAM_VM 0x9
	1636	+
	1637	+/*
	1638	+ * I915_CONTEXT_PARAM_ENGINES:
	1639	+ *
	1640	+ * Bind this context to operate on this subset of available engines. Henceforth,
	1641	+ * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
	1642	+ * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
	1643	+ * and upwards. Slots 0...N are filled in using the specified (class, instance).
	1644	+ * Use
	1645	+ * engine_class: I915_ENGINE_CLASS_INVALID,
	1646	+ * engine_instance: I915_ENGINE_CLASS_INVALID_NONE
	1647	+ * to specify a gap in the array that can be filled in later, e.g. by a
	1648	+ * virtual engine used for load balancing.
	1649	+ *
	1650	+ * Setting the number of engines bound to the context to 0, by passing a zero
	1651	+ * sized argument, will revert back to default settings.
	1652	+ *
	1653	+ * See struct i915_context_param_engines.
	1654	+ *
	1655	+ * Extensions:
	1656	+ * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
	1657	+ * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
	1658	+ */
	1659	+#define I915_CONTEXT_PARAM_ENGINES 0xa
	1660	+
	1661	+/*
	1662	+ * I915_CONTEXT_PARAM_PERSISTENCE:
	1663	+ *
	1664	+ * Allow the context and active rendering to survive the process until
	1665	+ * completion. Persistence allows fire-and-forget clients to queue up a
	1666	+ * bunch of work, hand the output over to a display server and then quit.
	1667	+ * If the context is marked as not persistent, upon closing (either via
	1668	+ * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure
	1669	+ * or process termination), the context and any outstanding requests will be
	1670	+ * cancelled (and exported fences for cancelled requests marked as -EIO).
	1671	+ *
	1672	+ * By default, new contexts allow persistence.
	1673	+ */
	1674	+#define I915_CONTEXT_PARAM_PERSISTENCE 0xb
	1675	+
	1676	+/*
	1677	+ * I915_CONTEXT_PARAM_RINGSIZE:
	1678	+ *
	1679	+ * Sets the size of the CS ringbuffer to use for logical ring contexts. This
	1680	+ * applies a limit of how many batches can be queued to HW before the caller
	1681	+ * is blocked due to lack of space for more commands.
	1682	+ *
	1683	+ * Only reliably possible to be set prior to first use, i.e. during
	1684	+ * construction. At any later point, the current execution must be flushed as
	1685	+ * the ring can only be changed while the context is idle. Note, the ringsize
	1686	+ * can be specified as a constructor property, see
	1687	+ * I915_CONTEXT_CREATE_EXT_SETPARAM, but can also be set later if required.
	1688	+ *
	1689	+ * Only applies to the current set of engine and lost when those engines
	1690	+ * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
	1691	+ *
	1692	+ * Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
	1693	+ * Default is 16 KiB.
	1694	+ */
	1695	+#define I915_CONTEXT_PARAM_RINGSIZE 0xc
	1696	+/* Must be kept compact -- no holes and well documented */
	1697	+
	1698	+ __u64 value;
	1699	+};
	1700	+
	1701	+/**
	1702	+ * Context SSEU programming
	1703	+ *
	1704	+ * It may be necessary for either functional or performance reason to configure
	1705	+ * a context to run with a reduced number of SSEU (where SSEU stands for Slice/
	1706	+ * Sub-slice/EU).
	1707	+ *
	1708	+ * This is done by configuring SSEU configuration using the below
	1709	+ * @struct drm_i915_gem_context_param_sseu for every supported engine which
	1710	+ * userspace intends to use.
	1711	+ *
	1712	+ * Not all GPUs or engines support this functionality in which case an error
	1713	+ * code -ENODEV will be returned.
	1714	+ *
	1715	+ * Also, flexibility of possible SSEU configuration permutations varies between
	1716	+ * GPU generations and software imposed limitations. Requesting such a
	1717	+ * combination will return an error code of -EINVAL.
	1718	+ *
	1719	+ * NOTE: When perf/OA is active the context's SSEU configuration is ignored in
	1720	+ * favour of a single global setting.
	1721	+ */
	1722	+struct drm_i915_gem_context_param_sseu {
	1723	+ /*
	1724	+ * Engine class & instance to be configured or queried.
	1725	+ */
	1726	+ struct i915_engine_class_instance engine;
	1727	+
	1728	+ /*
	1729	+ * Unknown flags must be cleared to zero.
	1730	+ */
	1731	+ __u32 flags;
	1732	+#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
	1733	+
	1734	+ /*
	1735	+ * Mask of slices to enable for the context. Valid values are a subset
	1736	+ * of the bitmask value returned for I915_PARAM_SLICE_MASK.
	1737	+ */
	1738	+ __u64 slice_mask;
	1739	+
	1740	+ /*
	1741	+ * Mask of subslices to enable for the context. Valid values are a
	1742	+ * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
	1743	+ */
	1744	+ __u64 subslice_mask;
	1745	+
	1746	+ /*
	1747	+ * Minimum/Maximum number of EUs to enable per subslice for the
	1748	+ * context. min_eus_per_subslice must be inferior or equal to
	1749	+ * max_eus_per_subslice.
	1750	+ */
	1751	+ __u16 min_eus_per_subslice;
	1752	+ __u16 max_eus_per_subslice;
	1753	+
	1754	+ /*
	1755	+ * Unused for now. Must be cleared to zero.
	1756	+ */
	1757	+ __u32 rsvd;
	1758	+};
	1759	+
	1760	+/*
	1761	+ * i915_context_engines_load_balance:
	1762	+ *
	1763	+ * Enable load balancing across this set of engines.
	1764	+ *
	1765	+ * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
	1766	+ * used will proxy the execbuffer request onto one of the set of engines
	1767	+ * in such a way as to distribute the load evenly across the set.
	1768	+ *
	1769	+ * The set of engines must be compatible (e.g. the same HW class) as they
	1770	+ * will share the same logical GPU context and ring.
	1771	+ *
	1772	+ * To intermix rendering with the virtual engine and direct rendering onto
	1773	+ * the backing engines (bypassing the load balancing proxy), the context must
	1774	+ * be defined to use a single timeline for all engines.
	1775	+ */
	1776	+struct i915_context_engines_load_balance {
	1777	+ struct i915_user_extension base;
	1778	+
	1779	+ __u16 engine_index;
	1780	+ __u16 num_siblings;
	1781	+ __u32 flags; /* all undefined flags must be zero */
	1782	+
	1783	+ __u64 mbz64; /* reserved for future use; must be zero */
	1784	+
	1785	+ struct i915_engine_class_instance engines[0];
	1786	+} __attribute__((packed));
	1787	+
	1788	+#define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
	1789	+ struct i915_user_extension base; \
	1790	+ __u16 engine_index; \
	1791	+ __u16 num_siblings; \
	1792	+ __u32 flags; \
	1793	+ __u64 mbz64; \
	1794	+ struct i915_engine_class_instance engines[N__]; \
	1795	+} __attribute__((packed)) name__
	1796	+
	1797	+/*
	1798	+ * i915_context_engines_bond:
	1799	+ *
	1800	+ * Constructed bonded pairs for execution within a virtual engine.
	1801	+ *
	1802	+ * All engines are equal, but some are more equal than others. Given
	1803	+ * the distribution of resources in the HW, it may be preferable to run
	1804	+ * a request on a given subset of engines in parallel to a request on a
	1805	+ * specific engine. We enable this selection of engines within a virtual
	1806	+ * engine by specifying bonding pairs, for any given master engine we will
	1807	+ * only execute on one of the corresponding siblings within the virtual engine.
	1808	+ *
	1809	+ * To execute a request in parallel on the master engine and a sibling requires
	1810	+ * coordination with a I915_EXEC_FENCE_SUBMIT.
	1811	+ */
	1812	+struct i915_context_engines_bond {
	1813	+ struct i915_user_extension base;
	1814	+
	1815	+ struct i915_engine_class_instance master;
	1816	+
	1817	+ __u16 virtual_index; /* index of virtual engine in ctx->engines[] */
	1818	+ __u16 num_bonds;
	1819	+
	1820	+ __u64 flags; /* all undefined flags must be zero */
	1821	+ __u64 mbz64[4]; /* reserved for future use; must be zero */
	1822	+
	1823	+ struct i915_engine_class_instance engines[0];
	1824	+} __attribute__((packed));
	1825	+
	1826	+#define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
	1827	+ struct i915_user_extension base; \
	1828	+ struct i915_engine_class_instance master; \
	1829	+ __u16 virtual_index; \
	1830	+ __u16 num_bonds; \
	1831	+ __u64 flags; \
	1832	+ __u64 mbz64[4]; \
	1833	+ struct i915_engine_class_instance engines[N__]; \
	1834	+} __attribute__((packed)) name__
	1835	+
	1836	+struct i915_context_param_engines {
	1837	+ __u64 extensions; /* linked chain of extension blocks, 0 terminates */
	1838	+#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
	1839	+#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
	1840	+ struct i915_engine_class_instance engines[0];
	1841	+} __attribute__((packed));
	1842	+
	1843	+#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
	1844	+ __u64 extensions; \
	1845	+ struct i915_engine_class_instance engines[N__]; \
	1846	+} __attribute__((packed)) name__
	1847	+
	1848	+struct drm_i915_gem_context_create_ext_setparam {
	1849	+#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
	1850	+ struct i915_user_extension base;
	1851	+ struct drm_i915_gem_context_param param;
	1852	+};
	1853	+
	1854	+struct drm_i915_gem_context_create_ext_clone {
	1855	+#define I915_CONTEXT_CREATE_EXT_CLONE 1
	1856	+ struct i915_user_extension base;
	1857	+ __u32 clone_id;
	1858	+ __u32 flags;
	1859	+#define I915_CONTEXT_CLONE_ENGINES (1u << 0)
	1860	+#define I915_CONTEXT_CLONE_FLAGS (1u << 1)
	1861	+#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
	1862	+#define I915_CONTEXT_CLONE_SSEU (1u << 3)
	1863	+#define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
	1864	+#define I915_CONTEXT_CLONE_VM (1u << 5)
	1865	+#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
	1866	+ __u64 rsvd;
1388	1867	};
1389	1868
1390	1869	struct drm_i915_gem_context_destroy {
1391	1870	__u32 ctx_id;
1392	1871	__u32 pad;
	1872	+};
	1873	+
	1874	+/*
	1875	+ * DRM_I915_GEM_VM_CREATE -
	1876	+ *
	1877	+ * Create a new virtual memory address space (ppGTT) for use within a context
	1878	+ * on the same file. Extensions can be provided to configure exactly how the
	1879	+ * address space is setup upon creation.
	1880	+ *
	1881	+ * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
	1882	+ * returned in the outparam @id.
	1883	+ *
	1884	+ * No flags are defined, with all bits reserved and must be zero.
	1885	+ *
	1886	+ * An extension chain maybe provided, starting with @extensions, and terminated
	1887	+ * by the @next_extension being 0. Currently, no extensions are defined.
	1888	+ *
	1889	+ * DRM_I915_GEM_VM_DESTROY -
	1890	+ *
	1891	+ * Destroys a previously created VM id, specified in @id.
	1892	+ *
	1893	+ * No extensions or flags are allowed currently, and so must be zero.
	1894	+ */
	1895	+struct drm_i915_gem_vm_control {
	1896	+ __u64 extensions;
	1897	+ __u32 flags;
	1898	+ __u32 vm_id;
1393	1899	};
1394	1900
1395	1901	struct drm_i915_reg_read {
..	..	@@ -1404,6 +1910,7 @@
1404	1910
1405	1911	__u64 val; /* Return value */
1406	1912	};
	1913	+
1407	1914	/* Known registers:
1408	1915	*
1409	1916	* Render engine timestamp - 0x2358 + 64bit - gen7+
..	..	@@ -1443,22 +1950,6 @@
1443	1950	__u32 handle;
1444	1951	};
1445	1952
1446		-struct drm_i915_gem_context_param {
1447		- __u32 ctx_id;
1448		- __u32 size;
1449		- __u64 param;
1450		-#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1451		-#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1452		-#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1453		-#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1454		-#define I915_CONTEXT_PARAM_BANNABLE 0x5
1455		-#define I915_CONTEXT_PARAM_PRIORITY 0x6
1456		-#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
1457		-#define I915_CONTEXT_DEFAULT_PRIORITY 0
1458		-#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
1459		- __u64 value;
1460		-};
1461		-
1462	1953	enum drm_i915_oa_format {
1463	1954	I915_OA_FORMAT_A13 = 1, /* HSW only */
1464	1955	I915_OA_FORMAT_A29, /* HSW only */
..	..	@@ -1481,23 +1972,31 @@
1481	1972	* Open the stream for a specific context handle (as used with
1482	1973	* execbuffer2). A stream opened for a specific context this way
1483	1974	* won't typically require root privileges.
	1975	+ *
	1976	+ * This property is available in perf revision 1.
1484	1977	*/
1485	1978	DRM_I915_PERF_PROP_CTX_HANDLE = 1,
1486	1979
1487	1980	/**
1488	1981	* A value of 1 requests the inclusion of raw OA unit reports as
1489	1982	* part of stream samples.
	1983	+ *
	1984	+ * This property is available in perf revision 1.
1490	1985	*/
1491	1986	DRM_I915_PERF_PROP_SAMPLE_OA,
1492	1987
1493	1988	/**
1494	1989	* The value specifies which set of OA unit metrics should be
1495		- * be configured, defining the contents of any OA unit reports.
	1990	+ * configured, defining the contents of any OA unit reports.
	1991	+ *
	1992	+ * This property is available in perf revision 1.
1496	1993	*/
1497	1994	DRM_I915_PERF_PROP_OA_METRICS_SET,
1498	1995
1499	1996	/**
1500	1997	* The value specifies the size and layout of OA unit reports.
	1998	+ *
	1999	+ * This property is available in perf revision 1.
1501	2000	*/
1502	2001	DRM_I915_PERF_PROP_OA_FORMAT,
1503	2002
..	..	@@ -1507,8 +2006,45 @@
1507	2006	* from this exponent as follows:
1508	2007	*
1509	2008	* 80ns * 2^(period_exponent + 1)
	2009	+ *
	2010	+ * This property is available in perf revision 1.
1510	2011	*/
1511	2012	DRM_I915_PERF_PROP_OA_EXPONENT,
	2013	+
	2014	+ /**
	2015	+ * Specifying this property is only valid when specify a context to
	2016	+ * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property
	2017	+ * will hold preemption of the particular context we want to gather
	2018	+ * performance data about. The execbuf2 submissions must include a
	2019	+ * drm_i915_gem_execbuffer_ext_perf parameter for this to apply.
	2020	+ *
	2021	+ * This property is available in perf revision 3.
	2022	+ */
	2023	+ DRM_I915_PERF_PROP_HOLD_PREEMPTION,
	2024	+
	2025	+ /**
	2026	+ * Specifying this pins all contexts to the specified SSEU power
	2027	+ * configuration for the duration of the recording.
	2028	+ *
	2029	+ * This parameter's value is a pointer to a struct
	2030	+ * drm_i915_gem_context_param_sseu.
	2031	+ *
	2032	+ * This property is available in perf revision 4.
	2033	+ */
	2034	+ DRM_I915_PERF_PROP_GLOBAL_SSEU,
	2035	+
	2036	+ /**
	2037	+ * This optional parameter specifies the timer interval in nanoseconds
	2038	+ * at which the i915 driver will check the OA buffer for available data.
	2039	+ * Minimum allowed value is 100 microseconds. A default value is used by
	2040	+ * the driver if this parameter is not specified. Note that larger timer
	2041	+ * values will reduce cpu consumption during OA perf captures. However,
	2042	+ * excessively large values would potentially result in OA buffer
	2043	+ * overwrites as captures reach end of the OA buffer.
	2044	+ *
	2045	+ * This property is available in perf revision 5.
	2046	+ */
	2047	+ DRM_I915_PERF_PROP_POLL_OA_PERIOD,
1512	2048
1513	2049	DRM_I915_PERF_PROP_MAX /* non-ABI */
1514	2050	};
..	..	@@ -1538,6 +2074,8 @@
1538	2074	* to close and re-open a stream with the same configuration.
1539	2075	*
1540	2076	* It's undefined whether any pending data for the stream will be lost.
	2077	+ *
	2078	+ * This ioctl is available in perf revision 1.
1541	2079	*/
1542	2080	#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
1543	2081
..	..	@@ -1545,8 +2083,23 @@
1545	2083	* Disable data capture for a stream.
1546	2084	*
1547	2085	* It is an error to try and read a stream that is disabled.
	2086	+ *
	2087	+ * This ioctl is available in perf revision 1.
1548	2088	*/
1549	2089	#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
	2090	+
	2091	+/**
	2092	+ * Change metrics_set captured by a stream.
	2093	+ *
	2094	+ * If the stream is bound to a specific context, the configuration change
	2095	+ * will performed inline with that context such that it takes effect before
	2096	+ * the next execbuf submission.
	2097	+ *
	2098	+ * Returns the previously bound metrics set id, or a negative error code.
	2099	+ *
	2100	+ * This ioctl is available in perf revision 2.
	2101	+ */
	2102	+#define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
1550	2103
1551	2104	/**
1552	2105	* Common to all i915 perf records
..	..	@@ -1620,6 +2173,9 @@
1620	2173	struct drm_i915_query_item {
1621	2174	__u64 query_id;
1622	2175	#define DRM_I915_QUERY_TOPOLOGY_INFO 1
	2176	+#define DRM_I915_QUERY_ENGINE_INFO 2
	2177	+#define DRM_I915_QUERY_PERF_CONFIG 3
	2178	+/* Must be kept compact -- no holes and well documented */
1623	2179
1624	2180	/*
1625	2181	* When set to zero by userspace, this is filled with the size of the
..	..	@@ -1630,9 +2186,18 @@
1630	2186	__s32 length;
1631	2187
1632	2188	/*
1633		- * Unused for now. Must be cleared to zero.
	2189	+ * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
	2190	+ *
	2191	+ * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
	2192	+ * following :
	2193	+ * - DRM_I915_QUERY_PERF_CONFIG_LIST
	2194	+ * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
	2195	+ * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
1634	2196	*/
1635	2197	__u32 flags;
	2198	+#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
	2199	+#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
	2200	+#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
1636	2201
1637	2202	/*
1638	2203	* Data will be written at the location pointed by data_ptr when the
..	..	@@ -1668,8 +2233,10 @@
1668	2233	* (data[X / 8] >> (X % 8)) & 1
1669	2234	*
1670	2235	* - the subslice mask for each slice with one bit per subslice telling
1671		- * whether a subslice is available. The availability of subslice Y in slice
1672		- * X can be queried with the following formula :
	2236	+ * whether a subslice is available. Gen12 has dual-subslices, which are
	2237	+ * similar to two gen11 subslices. For gen12, this array represents dual-
	2238	+ * subslices. The availability of subslice Y in slice X can be queried
	2239	+ * with the following formula :
1673	2240	*
1674	2241	* (data[subslice_offset +
1675	2242	* X * subslice_stride +
..	..	@@ -1717,6 +2284,97 @@
1717	2284	__u8 data[];
1718	2285	};
1719	2286
	2287	+/**
	2288	+ * struct drm_i915_engine_info
	2289	+ *
	2290	+ * Describes one engine and it's capabilities as known to the driver.
	2291	+ */
	2292	+struct drm_i915_engine_info {
	2293	+ /** Engine class and instance. */
	2294	+ struct i915_engine_class_instance engine;
	2295	+
	2296	+ /** Reserved field. */
	2297	+ __u32 rsvd0;
	2298	+
	2299	+ /** Engine flags. */
	2300	+ __u64 flags;
	2301	+
	2302	+ /** Capabilities of this engine. */
	2303	+ __u64 capabilities;
	2304	+#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
	2305	+#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
	2306	+
	2307	+ /** Reserved fields. */
	2308	+ __u64 rsvd1[4];
	2309	+};
	2310	+
	2311	+/**
	2312	+ * struct drm_i915_query_engine_info
	2313	+ *
	2314	+ * Engine info query enumerates all engines known to the driver by filling in
	2315	+ * an array of struct drm_i915_engine_info structures.
	2316	+ */
	2317	+struct drm_i915_query_engine_info {
	2318	+ /** Number of struct drm_i915_engine_info structs following. */
	2319	+ __u32 num_engines;
	2320	+
	2321	+ /** MBZ */
	2322	+ __u32 rsvd[3];
	2323	+
	2324	+ /** Marker for drm_i915_engine_info structures. */
	2325	+ struct drm_i915_engine_info engines[];
	2326	+};
	2327	+
	2328	+/*
	2329	+ * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
	2330	+ */
	2331	+struct drm_i915_query_perf_config {
	2332	+ union {
	2333	+ /*
	2334	+ * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
	2335	+ * this fields to the number of configurations available.
	2336	+ */
	2337	+ __u64 n_configs;
	2338	+
	2339	+ /*
	2340	+ * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
	2341	+ * i915 will use the value in this field as configuration
	2342	+ * identifier to decide what data to write into config_ptr.
	2343	+ */
	2344	+ __u64 config;
	2345	+
	2346	+ /*
	2347	+ * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
	2348	+ * i915 will use the value in this field as configuration
	2349	+ * identifier to decide what data to write into config_ptr.
	2350	+ *
	2351	+ * String formatted like "%08x-%04x-%04x-%04x-%012x"
	2352	+ */
	2353	+ char uuid[36];
	2354	+ };
	2355	+
	2356	+ /*
	2357	+ * Unused for now. Must be cleared to zero.
	2358	+ */
	2359	+ __u32 flags;
	2360	+
	2361	+ /*
	2362	+ * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
	2363	+ * write an array of __u64 of configuration identifiers.
	2364	+ *
	2365	+ * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
	2366	+ * write a struct drm_i915_perf_oa_config. If the following fields of
	2367	+ * drm_i915_perf_oa_config are set not set to 0, i915 will write into
	2368	+ * the associated pointers the values of submitted when the
	2369	+ * configuration was created :
	2370	+ *
	2371	+ * - n_mux_regs
	2372	+ * - n_boolean_regs
	2373	+ * - n_flex_regs
	2374	+ */
	2375	+ __u8 data[];
	2376	+};
	2377	+
1720	2378	#if defined(__cplusplus)
1721	2379	}
1722	2380	#endif