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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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1 | 2 | /* |
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2 | | - * 10G controller driver for Samsung EXYNOS SoCs |
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| 3 | + * 10G controller driver for Samsung Exynos SoCs |
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3 | 4 | * |
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4 | 5 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. |
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5 | 6 | * http://www.samsung.com |
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6 | 7 | * |
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7 | 8 | * Author: Siva Reddy Kallam <siva.kallam@samsung.com> |
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8 | | - * |
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9 | | - * This program is free software; you can redistribute it and/or modify |
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10 | | - * it under the terms of the GNU General Public License version 2 as |
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11 | | - * published by the Free Software Foundation. |
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12 | 9 | */ |
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13 | 10 | #ifndef __SXGBE_PLATFORM_H__ |
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14 | 11 | #define __SXGBE_PLATFORM_H__ |
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| 12 | + |
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| 13 | +#include <linux/phy.h> |
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15 | 14 | |
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16 | 15 | /* MDC Clock Selection define*/ |
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17 | 16 | #define SXGBE_CSR_100_150M 0x0 /* MDC = clk_scr_i/62 */ |
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.. | .. |
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41 | 40 | char *phy_bus_name; |
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42 | 41 | int bus_id; |
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43 | 42 | int phy_addr; |
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44 | | - int interface; |
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| 43 | + phy_interface_t interface; |
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45 | 44 | struct sxgbe_mdio_bus_data *mdio_bus_data; |
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46 | 45 | struct sxgbe_dma_cfg *dma_cfg; |
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47 | 46 | int clk_csr; |
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