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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/include/linux/switchtec.h
....@@ -1,16 +1,7 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Microsemi Switchtec PCIe Driver
34  * Copyright (c) 2017, Microsemi Corporation
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms and conditions of the GNU General Public License,
7
- * version 2, as published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
145  */
156 
167 #ifndef _SWITCHTEC_H
....@@ -20,7 +11,7 @@
2011 #include <linux/cdev.h>
2112 
2213 #define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
23
-#define SWITCHTEC_MAX_PFF_CSR 48
14
+#define SWITCHTEC_MAX_PFF_CSR 255
2415 
2516 #define SWITCHTEC_EVENT_OCCURRED BIT(0)
2617 #define SWITCHTEC_EVENT_CLEAR    BIT(0)
....@@ -28,6 +19,12 @@
2819 #define SWITCHTEC_EVENT_EN_CLI   BIT(2)
2920 #define SWITCHTEC_EVENT_EN_IRQ   BIT(3)
3021 #define SWITCHTEC_EVENT_FATAL    BIT(4)
22
+
23
+#define SWITCHTEC_DMA_MRPC_EN	BIT(0)
24
+
25
+#define MRPC_GAS_READ		0x29
26
+#define MRPC_GAS_WRITE		0x87
27
+#define MRPC_CMD_ID(x)		((x) & 0xffff)
3128 
3229 enum {
3330 	SWITCHTEC_GAS_MRPC_OFFSET       = 0x0000,
....@@ -40,12 +37,21 @@
4037 	SWITCHTEC_GAS_PFF_CSR_OFFSET    = 0x134000,
4138 };
4239 
40
+enum switchtec_gen {
41
+	SWITCHTEC_GEN3,
42
+	SWITCHTEC_GEN4,
43
+};
44
+
4345 struct mrpc_regs {
4446 	u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
4547 	u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
4648 	u32 cmd;
4749 	u32 status;
4850 	u32 ret_value;
51
+	u32 dma_en;
52
+	u64 dma_addr;
53
+	u32 dma_vector;
54
+	u32 dma_ver;
4955 } __packed;
5056 
5157 enum mrpc_status {
....@@ -102,16 +108,37 @@
102108 } __packed;
103109 
104110 enum {
105
-	SWITCHTEC_CFG0_RUNNING = 0x04,
106
-	SWITCHTEC_CFG1_RUNNING = 0x05,
107
-	SWITCHTEC_IMG0_RUNNING = 0x03,
108
-	SWITCHTEC_IMG1_RUNNING = 0x07,
111
+	SWITCHTEC_GEN3_CFG0_RUNNING = 0x04,
112
+	SWITCHTEC_GEN3_CFG1_RUNNING = 0x05,
113
+	SWITCHTEC_GEN3_IMG0_RUNNING = 0x03,
114
+	SWITCHTEC_GEN3_IMG1_RUNNING = 0x07,
109115 };
110116 
111
-struct sys_info_regs {
112
-	u32 device_id;
113
-	u32 device_version;
114
-	u32 firmware_version;
117
+enum {
118
+	SWITCHTEC_GEN4_MAP0_RUNNING = 0x00,
119
+	SWITCHTEC_GEN4_MAP1_RUNNING = 0x01,
120
+	SWITCHTEC_GEN4_KEY0_RUNNING = 0x02,
121
+	SWITCHTEC_GEN4_KEY1_RUNNING = 0x03,
122
+	SWITCHTEC_GEN4_BL2_0_RUNNING = 0x04,
123
+	SWITCHTEC_GEN4_BL2_1_RUNNING = 0x05,
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+	SWITCHTEC_GEN4_CFG0_RUNNING = 0x06,
125
+	SWITCHTEC_GEN4_CFG1_RUNNING = 0x07,
126
+	SWITCHTEC_GEN4_IMG0_RUNNING = 0x08,
127
+	SWITCHTEC_GEN4_IMG1_RUNNING = 0x09,
128
+};
129
+
130
+enum {
131
+	SWITCHTEC_GEN4_KEY0_ACTIVE = 0,
132
+	SWITCHTEC_GEN4_KEY1_ACTIVE = 1,
133
+	SWITCHTEC_GEN4_BL2_0_ACTIVE = 0,
134
+	SWITCHTEC_GEN4_BL2_1_ACTIVE = 1,
135
+	SWITCHTEC_GEN4_CFG0_ACTIVE = 0,
136
+	SWITCHTEC_GEN4_CFG1_ACTIVE = 1,
137
+	SWITCHTEC_GEN4_IMG0_ACTIVE = 0,
138
+	SWITCHTEC_GEN4_IMG1_ACTIVE = 1,
139
+};
140
+
141
+struct sys_info_regs_gen3 {
115142 	u32 reserved1;
116143 	u32 vendor_table_revision;
117144 	u32 table_format_version;
....@@ -128,31 +155,117 @@
128155 	u8 component_revision;
129156 } __packed;
130157 
131
-struct flash_info_regs {
158
+struct sys_info_regs_gen4 {
159
+	u16 gas_layout_ver;
160
+	u8 evlist_ver;
161
+	u8 reserved1;
162
+	u16 mgmt_cmd_set_ver;
163
+	u16 fabric_cmd_set_ver;
164
+	u32 reserved2[2];
165
+	u8 mrpc_uart_ver;
166
+	u8 mrpc_twi_ver;
167
+	u8 mrpc_eth_ver;
168
+	u8 mrpc_inband_ver;
169
+	u32 reserved3[7];
170
+	u32 fw_update_tmo;
171
+	u32 xml_version_cfg;
172
+	u32 xml_version_img;
173
+	u32 partition_id;
174
+	u16 bl2_running;
175
+	u16 cfg_running;
176
+	u16 img_running;
177
+	u16 key_running;
178
+	u32 reserved4[43];
179
+	u32 vendor_seeprom_twi;
180
+	u32 vendor_table_revision;
181
+	u32 vendor_specific_info[2];
182
+	u16 p2p_vendor_id;
183
+	u16 p2p_device_id;
184
+	u8 p2p_revision_id;
185
+	u8 reserved5[3];
186
+	u32 p2p_class_id;
187
+	u16 subsystem_vendor_id;
188
+	u16 subsystem_id;
189
+	u32 p2p_serial_number[2];
190
+	u8 mac_addr[6];
191
+	u8 reserved6[2];
192
+	u32 reserved7[3];
193
+	char vendor_id[8];
194
+	char product_id[24];
195
+	char  product_revision[2];
196
+	u16 reserved8;
197
+} __packed;
198
+
199
+struct sys_info_regs {
200
+	u32 device_id;
201
+	u32 device_version;
202
+	u32 firmware_version;
203
+	union {
204
+		struct sys_info_regs_gen3 gen3;
205
+		struct sys_info_regs_gen4 gen4;
206
+	};
207
+} __packed;
208
+
209
+struct partition_info {
210
+	u32 address;
211
+	u32 length;
212
+};
213
+
214
+struct flash_info_regs_gen3 {
132215 	u32 flash_part_map_upd_idx;
133216 
134
-	struct active_partition_info {
217
+	struct active_partition_info_gen3 {
135218 		u32 address;
136219 		u32 build_version;
137220 		u32 build_string;
138221 	} active_img;
139222 
140
-	struct active_partition_info active_cfg;
141
-	struct active_partition_info inactive_img;
142
-	struct active_partition_info inactive_cfg;
223
+	struct active_partition_info_gen3 active_cfg;
224
+	struct active_partition_info_gen3 inactive_img;
225
+	struct active_partition_info_gen3 inactive_cfg;
143226 
144227 	u32 flash_length;
145228 
146
-	struct partition_info {
147
-		u32 address;
148
-		u32 length;
149
-	} cfg0;
150
-
229
+	struct partition_info cfg0;
151230 	struct partition_info cfg1;
152231 	struct partition_info img0;
153232 	struct partition_info img1;
154233 	struct partition_info nvlog;
155234 	struct partition_info vendor[8];
235
+};
236
+
237
+struct flash_info_regs_gen4 {
238
+	u32 flash_address;
239
+	u32 flash_length;
240
+
241
+	struct active_partition_info_gen4 {
242
+		unsigned char bl2;
243
+		unsigned char cfg;
244
+		unsigned char img;
245
+		unsigned char key;
246
+	} active_flag;
247
+
248
+	u32 reserved[3];
249
+
250
+	struct partition_info map0;
251
+	struct partition_info map1;
252
+	struct partition_info key0;
253
+	struct partition_info key1;
254
+	struct partition_info bl2_0;
255
+	struct partition_info bl2_1;
256
+	struct partition_info cfg0;
257
+	struct partition_info cfg1;
258
+	struct partition_info img0;
259
+	struct partition_info img1;
260
+	struct partition_info nvlog;
261
+	struct partition_info vendor[8];
262
+};
263
+
264
+struct flash_info_regs {
265
+	union {
266
+		struct flash_info_regs_gen3 gen3;
267
+		struct flash_info_regs_gen4 gen4;
268
+	};
156269 };
157270 
158271 enum {
....@@ -200,7 +313,9 @@
200313 	u32 mrpc_comp_async_data[5];
201314 	u32 dyn_binding_hdr;
202315 	u32 dyn_binding_data[5];
203
-	u32 reserved4[159];
316
+	u32 intercomm_notify_hdr;
317
+	u32 intercomm_notify_data[5];
318
+	u32 reserved4[153];
204319 } __packed;
205320 
206321 enum {
....@@ -243,7 +358,11 @@
243358 		u32 win_size;
244359 		u64 xlate_addr;
245360 	} bar_entry[6];
246
-	u32 reserved2[216];
361
+	struct {
362
+		u32 win_size;
363
+		u32 reserved[3];
364
+	} bar_ext_entry[6];
365
+	u32 reserved2[192];
247366 	u32 req_id_table[512];
248367 	u32 reserved3[256];
249368 	u64 lut_entry[512];
....@@ -320,7 +439,8 @@
320439 	u32 dpc_data[5];
321440 	u32 cts_hdr;
322441 	u32 cts_data[5];
323
-	u32 reserved3[6];
442
+	u32 uec_hdr;
443
+	u32 uec_data[5];
324444 	u32 hotplug_hdr;
325445 	u32 hotplug_data[5];
326446 	u32 ier_hdr;
....@@ -342,10 +462,20 @@
342462 
343463 struct switchtec_ntb;
344464 
465
+struct dma_mrpc_output {
466
+	u32 status;
467
+	u32 cmd_id;
468
+	u32 rtn_code;
469
+	u32 output_size;
470
+	u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
471
+};
472
+
345473 struct switchtec_dev {
346474 	struct pci_dev *pdev;
347475 	struct device dev;
348476 	struct cdev cdev;
477
+
478
+	enum switchtec_gen gen;
349479 
350480 	int partition;
351481 	int partition_count;
....@@ -381,6 +511,9 @@
381511 	u8 link_event_count[SWITCHTEC_MAX_PFF_CSR];
382512 
383513 	struct switchtec_ntb *sndev;
514
+
515
+	struct dma_mrpc_output *dma_mrpc;
516
+	dma_addr_t dma_mrpc_dma_addr;
384517 };
385518 
386519 static inline struct switchtec_dev *to_stdev(struct device *dev)