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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/include/linux/qcom_scm.h
..
..
@@ -1,18 +1,11 @@
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-/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+/* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
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  * Copyright (C) 2015 Linaro Ltd.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #ifndef __QCOM_SCM_H
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 #define __QCOM_SCM_H
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7
 
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+#include <linux/err.h>
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 #include <linux/types.h>
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 #include <linux/cpumask.h>
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11
 
..
..
@@ -31,8 +24,37 @@
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 	int perm;
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 };
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26
 
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+enum qcom_scm_ocmem_client {
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+	QCOM_SCM_OCMEM_UNUSED_ID = 0x0,
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+	QCOM_SCM_OCMEM_GRAPHICS_ID,
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+	QCOM_SCM_OCMEM_VIDEO_ID,
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+	QCOM_SCM_OCMEM_LP_AUDIO_ID,
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+	QCOM_SCM_OCMEM_SENSORS_ID,
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+	QCOM_SCM_OCMEM_OTHER_OS_ID,
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+	QCOM_SCM_OCMEM_DEBUG_ID,
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+};
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+
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+enum qcom_scm_sec_dev_id {
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+	QCOM_SCM_MDSS_DEV_ID    = 1,
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+	QCOM_SCM_OCMEM_DEV_ID   = 5,
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+	QCOM_SCM_PCIE0_DEV_ID   = 11,
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+	QCOM_SCM_PCIE1_DEV_ID   = 12,
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+	QCOM_SCM_GFX_DEV_ID     = 18,
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+	QCOM_SCM_UFS_DEV_ID     = 19,
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+	QCOM_SCM_ICE_DEV_ID     = 20,
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+};
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+
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+enum qcom_scm_ice_cipher {
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+	QCOM_SCM_ICE_CIPHER_AES_128_XTS = 0,
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+	QCOM_SCM_ICE_CIPHER_AES_128_CBC = 1,
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+	QCOM_SCM_ICE_CIPHER_AES_256_XTS = 3,
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+	QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4,
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+};
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+
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 #define QCOM_SCM_VMID_HLOS       0x3
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 #define QCOM_SCM_VMID_MSS_MSA    0xF
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+#define QCOM_SCM_VMID_WLAN       0x18
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+#define QCOM_SCM_VMID_WLAN_CE    0x19
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 #define QCOM_SCM_PERM_READ       0x4
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 #define QCOM_SCM_PERM_WRITE      0x2
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 #define QCOM_SCM_PERM_EXEC       0x1
..
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@@ -40,68 +62,113 @@
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 #define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
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63
 
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 #if IS_ENABLED(CONFIG_QCOM_SCM)
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+extern bool qcom_scm_is_available(void);
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+
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 extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
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 extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
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-extern bool qcom_scm_is_available(void);
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-extern bool qcom_scm_hdcp_available(void);
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-extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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-			     u32 *resp);
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-extern bool qcom_scm_pas_supported(u32 peripheral);
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+extern void qcom_scm_cpu_power_down(u32 flags);
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+extern int qcom_scm_set_remote_state(u32 state, u32 id);
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+
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 extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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 				   size_t size);
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 extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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 				  phys_addr_t size);
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 extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
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 extern int qcom_scm_pas_shutdown(u32 peripheral);
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-extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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-			       unsigned int *src, struct qcom_scm_vmperm *newvm,
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-			       int dest_cnt);
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-extern void qcom_scm_cpu_power_down(u32 flags);
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-extern u32 qcom_scm_get_version(void);
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-extern int qcom_scm_set_remote_state(u32 state, u32 id);
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+extern bool qcom_scm_pas_supported(u32 peripheral);
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+
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+extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
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+extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
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+
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+extern bool qcom_scm_restore_sec_cfg_available(void);
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 extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
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 extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
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 extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
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-extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
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-extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
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+extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
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+					  u32 cp_nonpixel_start,
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+					  u32 cp_nonpixel_size);
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+extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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+			       unsigned int *src,
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+			       const struct qcom_scm_vmperm *newvm,
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+			       unsigned int dest_cnt);
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+
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+extern bool qcom_scm_ocmem_lock_available(void);
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+extern int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
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+			       u32 size, u32 mode);
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+extern int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset,
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+				 u32 size);
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+
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+extern bool qcom_scm_ice_available(void);
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+extern int qcom_scm_ice_invalidate_key(u32 index);
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+extern int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
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+				enum qcom_scm_ice_cipher cipher,
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+				u32 data_unit_size);
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+
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+extern bool qcom_scm_hdcp_available(void);
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+extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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+			     u32 *resp);
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+
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+extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
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 #else
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113
 
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 #include <linux/errno.h>
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115
 
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-static inline
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-int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
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-{
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-	return -ENODEV;
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-}
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-static inline
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-int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
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-{
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-	return -ENODEV;
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-}
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 static inline bool qcom_scm_is_available(void) { return false; }
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+
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+static inline int qcom_scm_set_cold_boot_addr(void *entry,
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+		const cpumask_t *cpus) { return -ENODEV; }
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+static inline int qcom_scm_set_warm_boot_addr(void *entry,
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+		const cpumask_t *cpus) { return -ENODEV; }
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+static inline void qcom_scm_cpu_power_down(u32 flags) {}
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+static inline u32 qcom_scm_set_remote_state(u32 state,u32 id)
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+		{ return -ENODEV; }
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+
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+static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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+		size_t size) { return -ENODEV; }
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+static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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+		phys_addr_t size) { return -ENODEV; }
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+static inline int qcom_scm_pas_auth_and_reset(u32 peripheral)
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+		{ return -ENODEV; }
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+static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
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+static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
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+
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+static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
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+		{ return -ENODEV; }
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+static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
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+		{ return -ENODEV; }
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+
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+static inline bool qcom_scm_restore_sec_cfg_available(void) { return false; }
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+static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
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+		{ return -ENODEV; }
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+static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
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+		{ return -ENODEV; }
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+static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
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+		{ return -ENODEV; }
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+extern inline int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
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+						 u32 cp_nonpixel_start,
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+						 u32 cp_nonpixel_size)
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+		{ return -ENODEV; }
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+static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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+		unsigned int *src, const struct qcom_scm_vmperm *newvm,
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+		unsigned int dest_cnt) { return -ENODEV; }
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+
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+static inline bool qcom_scm_ocmem_lock_available(void) { return false; }
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+static inline int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset,
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+		u32 size, u32 mode) { return -ENODEV; }
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+static inline int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id,
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+		u32 offset, u32 size) { return -ENODEV; }
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+
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+static inline bool qcom_scm_ice_available(void) { return false; }
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+static inline int qcom_scm_ice_invalidate_key(u32 index) { return -ENODEV; }
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+static inline int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
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+				       enum qcom_scm_ice_cipher cipher,
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+				       u32 data_unit_size) { return -ENODEV; }
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+
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 static inline bool qcom_scm_hdcp_available(void) { return false; }
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 static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
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-				    u32 *resp) { return -ENODEV; }
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-static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
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-static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
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-					  size_t size) { return -ENODEV; }
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-static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
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-					 phys_addr_t size) { return -ENODEV; }
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-static inline int
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-qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
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-static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
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-static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
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-				      unsigned int *src,
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-				      struct qcom_scm_vmperm *newvm,
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-				      int dest_cnt) { return -ENODEV; }
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-static inline void qcom_scm_cpu_power_down(u32 flags) {}
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-static inline u32 qcom_scm_get_version(void) { return 0; }
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-static inline u32
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-qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
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-static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
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-static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
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-static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
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-static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
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-static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
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+		u32 *resp) { return -ENODEV; }
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+
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+static inline int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
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+		{ return -ENODEV; }
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 #endif
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 #endif