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60 | 60 | #define MLX5_I2C_ADDR_LOW 0x50 |
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61 | 61 | #define MLX5_I2C_ADDR_HIGH 0x51 |
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62 | 62 | #define MLX5_EEPROM_PAGE_LENGTH 256 |
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| 63 | +#define MLX5_EEPROM_HIGH_PAGE_LENGTH 128 |
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63 | 64 | |
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64 | 65 | enum mlx5e_link_mode { |
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65 | 66 | MLX5E_1000BASE_CX_SGMII = 0, |
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92 | 93 | MLX5E_LINK_MODES_NUMBER, |
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93 | 94 | }; |
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94 | 95 | |
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| 96 | +enum mlx5e_ext_link_mode { |
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| 97 | + MLX5E_SGMII_100M = 0, |
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| 98 | + MLX5E_1000BASE_X_SGMII = 1, |
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| 99 | + MLX5E_5GBASE_R = 3, |
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| 100 | + MLX5E_10GBASE_XFI_XAUI_1 = 4, |
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| 101 | + MLX5E_40GBASE_XLAUI_4_XLPPI_4 = 5, |
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| 102 | + MLX5E_25GAUI_1_25GBASE_CR_KR = 6, |
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| 103 | + MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 7, |
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| 104 | + MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8, |
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| 105 | + MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9, |
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| 106 | + MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10, |
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| 107 | + MLX5E_100GAUI_1_100GBASE_CR_KR = 11, |
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| 108 | + MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12, |
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| 109 | + MLX5E_200GAUI_2_200GBASE_CR2_KR2 = 13, |
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| 110 | + MLX5E_400GAUI_8 = 15, |
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| 111 | + MLX5E_400GAUI_4_400GBASE_CR4_KR4 = 16, |
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| 112 | + MLX5E_EXT_LINK_MODES_NUMBER, |
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| 113 | +}; |
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| 114 | + |
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95 | 115 | enum mlx5e_connector_type { |
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96 | 116 | MLX5E_PORT_UNKNOWN = 0, |
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97 | 117 | MLX5E_PORT_NONE = 1, |
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105 | 125 | MLX5E_CONNECTOR_TYPE_NUMBER, |
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106 | 126 | }; |
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107 | 127 | |
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108 | | -#define MLX5E_PROT_MASK(link_mode) (1 << link_mode) |
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| 128 | +enum mlx5_ptys_width { |
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| 129 | + MLX5_PTYS_WIDTH_1X = 1 << 0, |
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| 130 | + MLX5_PTYS_WIDTH_2X = 1 << 1, |
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| 131 | + MLX5_PTYS_WIDTH_4X = 1 << 2, |
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| 132 | + MLX5_PTYS_WIDTH_8X = 1 << 3, |
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| 133 | + MLX5_PTYS_WIDTH_12X = 1 << 4, |
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| 134 | +}; |
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109 | 135 | |
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110 | | -#define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF |
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111 | | -#define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF |
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| 136 | +#define MLX5E_PROT_MASK(link_mode) (1 << link_mode) |
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| 137 | +#define MLX5_GET_ETH_PROTO(reg, out, ext, field) \ |
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| 138 | + (ext ? MLX5_GET(reg, out, ext_##field) : \ |
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| 139 | + MLX5_GET(reg, out, field)) |
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112 | 140 | |
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113 | 141 | int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); |
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114 | 142 | int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, |
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115 | 143 | int ptys_size, int proto_mask, u8 local_port); |
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116 | | -int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev, |
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117 | | - u32 *proto_cap, int proto_mask); |
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118 | | -int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev, |
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119 | | - u32 *proto_admin, int proto_mask); |
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120 | | -int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev, |
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121 | | - u8 *link_width_oper, u8 local_port); |
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122 | | -int mlx5_query_port_ib_proto_oper(struct mlx5_core_dev *dev, |
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123 | | - u8 *proto_oper, u8 local_port); |
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124 | | -int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev *dev, |
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125 | | - u32 *proto_oper, u8 local_port); |
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126 | | -int mlx5_set_port_ptys(struct mlx5_core_dev *dev, bool an_disable, |
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127 | | - u32 proto_admin, int proto_mask); |
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| 144 | + |
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| 145 | +int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper, |
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| 146 | + u16 *proto_oper, u8 local_port); |
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128 | 147 | void mlx5_toggle_port_link(struct mlx5_core_dev *dev); |
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129 | 148 | int mlx5_set_port_admin_status(struct mlx5_core_dev *dev, |
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130 | 149 | enum mlx5_port_status status); |
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131 | 150 | int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, |
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132 | 151 | enum mlx5_port_status *status); |
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133 | 152 | int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration); |
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134 | | -void mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask, |
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135 | | - u8 *an_status, |
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136 | | - u8 *an_disable_cap, u8 *an_disable_admin); |
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137 | 153 | |
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138 | 154 | int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port); |
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139 | 155 | void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, u8 port); |
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177 | 193 | int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode); |
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178 | 194 | int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode); |
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179 | 195 | |
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| 196 | +int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen); |
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| 197 | +int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen); |
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180 | 198 | int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable); |
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181 | 199 | void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported, |
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182 | 200 | bool *enabled); |
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