| .. | .. |
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| 1 | 1 | // SPDX-License-Identifier: GPL-2.0 |
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| 2 | | -/** |
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| 2 | +/* |
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| 3 | 3 | * dwc3-omap.c - OMAP Specific Glue layer |
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| 4 | 4 | * |
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| 5 | | - * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com |
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| 5 | + * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com |
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| 6 | 6 | * |
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| 7 | 7 | * Authors: Felipe Balbi <balbi@ti.com>, |
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| 8 | 8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> |
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| .. | .. |
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| 14 | 14 | #include <linux/irq.h> |
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| 15 | 15 | #include <linux/interrupt.h> |
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| 16 | 16 | #include <linux/platform_device.h> |
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| 17 | | -#include <linux/platform_data/dwc3-omap.h> |
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| 18 | 17 | #include <linux/pm_runtime.h> |
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| 19 | 18 | #include <linux/dma-mapping.h> |
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| 20 | 19 | #include <linux/ioport.h> |
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| .. | .. |
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| 105 | 104 | #define USBOTGSS_UTMI_OTG_CTRL_SESSEND BIT(3) |
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| 106 | 105 | #define USBOTGSS_UTMI_OTG_CTRL_SESSVALID BIT(2) |
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| 107 | 106 | #define USBOTGSS_UTMI_OTG_CTRL_VBUSVALID BIT(1) |
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| 107 | + |
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| 108 | +enum dwc3_omap_utmi_mode { |
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| 109 | + DWC3_OMAP_UTMI_MODE_UNKNOWN = 0, |
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| 110 | + DWC3_OMAP_UTMI_MODE_HW, |
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| 111 | + DWC3_OMAP_UTMI_MODE_SW, |
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| 112 | +}; |
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| 108 | 113 | |
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| 109 | 114 | struct dwc3_omap { |
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| 110 | 115 | struct device *dev; |
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| .. | .. |
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| 237 | 242 | break; |
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| 238 | 243 | |
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| 239 | 244 | case OMAP_DWC3_ID_FLOAT: |
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| 240 | | - if (omap->vbus_reg) |
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| 245 | + if (omap->vbus_reg && regulator_is_enabled(omap->vbus_reg)) |
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| 241 | 246 | regulator_disable(omap->vbus_reg); |
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| 242 | 247 | val = dwc3_omap_read_utmi_ctrl(omap); |
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| 243 | 248 | val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG; |
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| .. | .. |
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| 451 | 456 | struct device_node *node = pdev->dev.of_node; |
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| 452 | 457 | |
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| 453 | 458 | struct dwc3_omap *omap; |
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| 454 | | - struct resource *res; |
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| 455 | 459 | struct device *dev = &pdev->dev; |
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| 456 | 460 | struct regulator *vbus_reg = NULL; |
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| 457 | 461 | |
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| 458 | 462 | int ret; |
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| 459 | 463 | int irq; |
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| 460 | | - |
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| 461 | | - u32 reg; |
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| 462 | 464 | |
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| 463 | 465 | void __iomem *base; |
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| 464 | 466 | |
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| .. | .. |
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| 474 | 476 | platform_set_drvdata(pdev, omap); |
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| 475 | 477 | |
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| 476 | 478 | irq = platform_get_irq(pdev, 0); |
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| 477 | | - if (irq < 0) { |
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| 478 | | - dev_err(dev, "missing IRQ resource: %d\n", irq); |
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| 479 | + if (irq < 0) |
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| 479 | 480 | return irq; |
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| 480 | | - } |
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| 481 | 481 | |
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| 482 | | - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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| 483 | | - base = devm_ioremap_resource(dev, res); |
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| 482 | + base = devm_platform_ioremap_resource(pdev, 0); |
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| 484 | 483 | if (IS_ERR(base)) |
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| 485 | 484 | return PTR_ERR(base); |
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| 486 | 485 | |
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| .. | .. |
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| 506 | 505 | |
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| 507 | 506 | dwc3_omap_map_offset(omap); |
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| 508 | 507 | dwc3_omap_set_utmi_mode(omap); |
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| 509 | | - |
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| 510 | | - /* check the DMA Status */ |
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| 511 | | - reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG); |
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| 512 | 508 | |
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| 513 | 509 | ret = dwc3_omap_extcon_register(omap); |
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| 514 | 510 | if (ret < 0) |
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