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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/usb/dwc2/params.c
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@@ -68,14 +68,15 @@
68
68
 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
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 		GAHBCFG_HBSTLEN_SHIFT;
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 	p->change_speed_quirk = true;
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-	p->power_down = false;
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+	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
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 }
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73
 
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 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
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 {
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 	struct dwc2_core_params *p = &hsotg->params;
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77
 
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-	p->power_down = 0;
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+	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
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+	p->phy_utmi_width = 8;
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80
 }
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81
 
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 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
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@@ -88,9 +89,9 @@
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 	p->host_perio_tx_fifo_size = 256;
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 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
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 		GAHBCFG_HBSTLEN_SHIFT;
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+	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
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 	p->lpm = false;
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 	p->g_dma_desc = false;
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-	p->power_down = 0;
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 }
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96
 
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 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
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@@ -121,6 +122,16 @@
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 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
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 		GAHBCFG_HBSTLEN_SHIFT;
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 	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
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+}
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+
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+static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
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+{
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+	struct dwc2_core_params *p = &hsotg->params;
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+
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+	p->lpm = false;
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+	p->lpm_clock_gating = false;
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+	p->besl = false;
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+	p->hird_threshold_en = false;
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135
 }
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136
 
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 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
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@@ -154,6 +165,43 @@
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 	p->host_perio_tx_fifo_size = 256;
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 }
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167
 
168
+static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
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+{
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+	struct dwc2_core_params *p = &hsotg->params;
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+
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+	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
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+	p->speed = DWC2_SPEED_PARAM_FULL;
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+	p->host_rx_fifo_size = 128;
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+	p->host_nperio_tx_fifo_size = 96;
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+	p->host_perio_tx_fifo_size = 96;
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+	p->max_packet_count = 256;
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+	p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
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+	p->i2c_enable = false;
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+	p->activate_stm_fs_transceiver = true;
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+	p->activate_stm_id_vb_detection = true;
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+	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
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+	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
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+	p->host_support_fs_ls_low_power = true;
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+	p->host_ls_low_power_phy_clk = true;
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+}
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+
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+static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
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+{
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+	struct dwc2_core_params *p = &hsotg->params;
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+
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+	p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
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+	p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch");
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+	p->host_rx_fifo_size = 440;
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+	p->host_nperio_tx_fifo_size = 256;
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+	p->host_perio_tx_fifo_size = 256;
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+	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
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+	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
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+	p->lpm = false;
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+	p->lpm_clock_gating = false;
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+	p->besl = false;
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+	p->hird_threshold_en = false;
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+}
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+
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 const struct of_device_id dwc2_of_match_table[] = {
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 	{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
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 	{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },
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@@ -169,12 +217,19 @@
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 	  .data = dwc2_set_amlogic_params },
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 	{ .compatible = "amlogic,meson-gxbb-usb",
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 	  .data = dwc2_set_amlogic_params },
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+	{ .compatible = "amlogic,meson-g12a-usb",
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+	  .data = dwc2_set_amlogic_g12a_params },
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 	{ .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
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+	{ .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
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 	{ .compatible = "st,stm32f4x9-fsotg",
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 	  .data = dwc2_set_stm32f4x9_fsotg_params },
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 	{ .compatible = "st,stm32f4x9-hsotg" },
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 	{ .compatible = "st,stm32f7-hsotg",
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 	  .data = dwc2_set_stm32f7_hsotg_params },
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+	{ .compatible = "st,stm32mp15-fsotg",
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+	  .data = dwc2_set_stm32mp15_fsotg_params },
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+	{ .compatible = "st,stm32mp15-hsotg",
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+	  .data = dwc2_set_stm32mp15_hsotg_params },
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 	{},
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 };
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 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
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@@ -243,6 +298,15 @@
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 	val = (hsotg->hw_params.utmi_phy_data_width ==
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 	       GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
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301
+	if (hsotg->phy) {
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+		/*
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+		 * If using the generic PHY framework, check if the PHY bus
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+		 * width is 8-bit and set the phyif appropriately.
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+		 */
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+		if (phy_get_bus_width(hsotg->phy) == 8)
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+			val = 8;
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+	}
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+
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 	hsotg->params.phy_utmi_width = val;
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311
 }
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312
 
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@@ -266,13 +330,30 @@
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 	int val;
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331
 
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 	if (hsotg->hw_params.hibernation)
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-		val = 2;
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+		val = DWC2_POWER_DOWN_PARAM_HIBERNATION;
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 	else if (hsotg->hw_params.power_optimized)
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-		val = 1;
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+		val = DWC2_POWER_DOWN_PARAM_PARTIAL;
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 	else
273
-		val = 0;
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+		val = DWC2_POWER_DOWN_PARAM_NONE;
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338
 
275
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 	hsotg->params.power_down = val;
340
+}
341
+
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+static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
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+{
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+	struct dwc2_core_params *p = &hsotg->params;
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+
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+	p->lpm = hsotg->hw_params.lpm_mode;
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+	if (p->lpm) {
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+		p->lpm_clock_gating = true;
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+		p->besl = true;
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+		p->hird_threshold_en = true;
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+		p->hird_threshold = 4;
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+	} else {
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+		p->lpm_clock_gating = false;
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+		p->besl = false;
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+		p->hird_threshold_en = false;
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+	}
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 }
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358
 
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 /**
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@@ -293,6 +374,7 @@
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 	dwc2_set_param_speed(hsotg);
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 	dwc2_set_param_phy_utmi_width(hsotg);
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 	dwc2_set_param_power_down(hsotg);
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+	dwc2_set_param_lpm(hsotg);
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 	p->phy_ulpi_ddr = false;
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 	p->phy_ulpi_ext_vbus = false;
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380
 
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@@ -305,15 +387,13 @@
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 	p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
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 	p->uframe_sched = true;
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 	p->external_id_pin_ctl = false;
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-	p->lpm = true;
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-	p->lpm_clock_gating = true;
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-	p->besl = true;
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-	p->hird_threshold_en = true;
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-	p->hird_threshold = 4;
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390
 	p->ipg_isoc_en = false;
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+	p->service_interval = false;
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 	p->max_packet_count = hw->max_packet_count;
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 	p->max_transfer_size = hw->max_transfer_size;
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 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
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+	p->ref_clk_per = 33333;
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+	p->sof_cnt_wkup_alert = 100;
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397
 
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 	if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
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 	    (hsotg->dr_mode == USB_DR_MODE_OTG)) {
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@@ -368,10 +448,7 @@
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 		device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
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 					 &p->g_np_tx_fifo_size);
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450
 
371
-		num = device_property_read_u32_array(hsotg->dev,
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-						     "g-tx-fifo-size",
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-						     NULL, 0);
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-
451
+		num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size");
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 		if (num > 0) {
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 			num = min(num, 15);
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 			memset(p->g_tx_fifo_size, 0,
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@@ -604,6 +681,7 @@
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 	CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
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 	CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
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 	CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
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+	CHECK_BOOL(service_interval, hw->service_interval_mode);
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 	CHECK_RANGE(max_packet_count,
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 		    15, hw->max_packet_count,
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 		    hw->max_packet_count);
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@@ -715,25 +793,6 @@
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 	u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
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794
 	u32 grxfsiz;
717
795
 
718
-	/*
719
-	 * Attempt to ensure this device is really a DWC_otg Controller.
720
-	 * Read and verify the GSNPSID register contents. The value should be
721
-	 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
722
-	 */
723
-
724
-	hw->snpsid = dwc2_readl(hsotg, GSNPSID);
725
-	if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
726
-	    (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
727
-	    (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
728
-		dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
729
-			hw->snpsid);
730
-		return -ENODEV;
731
-	}
732
-
733
-	dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
734
-		hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
735
-		hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
736
-
737
796
 	hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
738
797
 	hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
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798
 	hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
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@@ -792,6 +851,8 @@
792
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 				  GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
793
852
 	hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
794
853
 	hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
854
+	hw->service_interval_mode = !!(hwcfg4 &
855
+				       GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
795
856
 
796
857
 	/* fifo sizes */
797
858
 	hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>