~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,4 +1,4 @@
1		-// SPDX-License-Identifier: GPL-2.0
	1	+/* SPDX-License-Identifier: GPL-2.0 */
2	2	/*
3	3	* Copyright (C) Maxime Coquelin 2015
4	4	* Copyright (C) STMicroelectronics SA 2017
..	..	@@ -27,6 +27,7 @@
27	27	bool has_7bits_data;
28	28	bool has_wakeup;
29	29	bool has_fifo;
	30	+ int fifosize;
30	31	};
31	32
32	33	struct stm32_usart_info {
..	..	@@ -54,6 +55,7 @@
54	55	.cfg = {
55	56	.uart_enable_bit = 13,
56	57	.has_7bits_data = false,
	58	+ .fifosize = 1,
57	59	}
58	60	};
59	61
..	..	@@ -74,6 +76,7 @@
74	76	.cfg = {
75	77	.uart_enable_bit = 0,
76	78	.has_7bits_data = true,
	79	+ .fifosize = 1,
77	80	}
78	81	};
79	82
..	..	@@ -96,6 +99,7 @@
96	99	.has_7bits_data = true,
97	100	.has_wakeup = true,
98	101	.has_fifo = true,
	102	+ .fifosize = 16,
99	103	}
100	104	};
101	105
..	..	@@ -201,6 +205,19 @@
201	205	#define USART_CR3_WUS_MASK GENMASK(21, 20) /* H7 */
202	206	#define USART_CR3_WUS_START_BIT BIT(21) /* H7 */
203	207	#define USART_CR3_WUFIE BIT(22) /* H7 */
	208	+#define USART_CR3_TXFTIE BIT(23) /* H7 */
	209	+#define USART_CR3_TCBGTIE BIT(24) /* H7 */
	210	+#define USART_CR3_RXFTCFG_MASK GENMASK(27, 25) /* H7 */
	211	+#define USART_CR3_RXFTCFG_SHIFT 25 /* H7 */
	212	+#define USART_CR3_RXFTIE BIT(28) /* H7 */
	213	+#define USART_CR3_TXFTCFG_MASK GENMASK(31, 29) /* H7 */
	214	+#define USART_CR3_TXFTCFG_SHIFT 29 /* H7 */
	215	+
	216	+/* TX FIFO threashold set to half of its depth */
	217	+#define USART_CR3_TXFTCFG_HALF 0x2
	218	+
	219	+/* RX FIFO threashold set to half of its depth */
	220	+#define USART_CR3_RXFTCFG_HALF 0x2
204	221
205	222	/* USART_GTPR */
206	223	#define USART_GTPR_PSC_MASK GENMASK(7, 0)
..	..	@@ -239,19 +256,22 @@
239	256	struct stm32_port {
240	257	struct uart_port port;
241	258	struct clk *clk;
242		- struct stm32_usart_info *info;
	259	+ const struct stm32_usart_info *info;
243	260	struct dma_chan rx_ch; / dma rx channel */
244	261	dma_addr_t rx_dma_buf; /* dma rx buffer bus address */
245	262	unsigned char rx_buf; / dma rx buffer cpu address */
246	263	struct dma_chan tx_ch; / dma tx channel */
247	264	dma_addr_t tx_dma_buf; /* dma tx buffer bus address */
248	265	unsigned char tx_buf; / dma tx buffer cpu address */
	266	+ u32 cr1_irq; /* USART_CR1_RXNEIE or RTOIE */
	267	+ u32 cr3_irq; /* USART_CR3_RXFTIE */
249	268	int last_res;
250	269	bool tx_dma_busy; /* dma tx busy */
251	270	bool hw_flow_control;
252	271	bool fifoen;
253	272	int wakeirq;
254	273	int rdr_mask; /* receive data register mask */
	274	+ struct mctrl_gpios gpios; / modem control gpios */
255	275	};
256	276
257	277	static struct stm32_port stm32_ports[STM32_MAX_PORTS];