~hc/RK356X_SDK_RELEASE.git

..	..	@@ -38,10 +38,6 @@
38	38	#include <asm/sgi/hpc3.h>
39	39	#include <asm/sgi/ip22.h>
40	40
41		-#if defined(CONFIG_SERIAL_IP22_ZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
42		-#define SUPPORT_SYSRQ
43		-#endif
44		-
45	41	#include <linux/serial_core.h>
46	42
47	43	#include "ip22zilog.h"
..	..	@@ -1080,6 +1076,7 @@
1080	1076
1081	1077	static void __init ip22zilog_prepare(void)
1082	1078	{
	1079	+ unsigned char sysrq_on = IS_ENABLED(CONFIG_SERIAL_IP22_ZILOG_CONSOLE);
1083	1080	struct uart_ip22zilog_port *up;
1084	1081	struct zilog_layout *rp;
1085	1082	int channel, chip;
..	..	@@ -1115,6 +1112,7 @@
1115	1112	up[(chip * 2) + 0].port.irq = zilog_irq;
1116	1113	up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1117	1114	up[(chip * 2) + 0].port.fifosize = 1;
	1115	+ up[(chip * 2) + 0].port.has_sysrq = sysrq_on;
1118	1116	up[(chip * 2) + 0].port.ops = &ip22zilog_pops;
1119	1117	up[(chip * 2) + 0].port.type = PORT_IP22ZILOG;
1120	1118	up[(chip * 2) + 0].port.flags = 0;
..	..	@@ -1126,6 +1124,7 @@
1126	1124	up[(chip * 2) + 1].port.irq = zilog_irq;
1127	1125	up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1128	1126	up[(chip * 2) + 1].port.fifosize = 1;
	1127	+ up[(chip * 2) + 1].port.has_sysrq = sysrq_on;
1129	1128	up[(chip * 2) + 1].port.ops = &ip22zilog_pops;
1130	1129	up[(chip * 2) + 1].port.type = PORT_IP22ZILOG;
1131	1130	up[(chip * 2) + 1].port.line = (chip * 2) + 1;