~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,38 +1,41 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* drivers/soc/tegra/pmc.c
3	4	*
4	5	* Copyright (c) 2010 Google, Inc
	6	+ * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
5	7	*
6	8	* Author:
7	9	* Colin Cross <ccross@google.com>
8		- *
9		- * This software is licensed under the terms of the GNU General Public
10		- * License version 2, as published by the Free Software Foundation, and
11		- * may be copied, distributed, and modified under those terms.
12		- *
13		- * This program is distributed in the hope that it will be useful,
14		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
15		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16		- * GNU General Public License for more details.
17		- *
18	10	*/
19	11
20	12	#define pr_fmt(fmt) "tegra-pmc: " fmt
21	13
22		-#include <linux/kernel.h>
	14	+#include <linux/arm-smccc.h>
23	15	#include <linux/clk.h>
	16	+#include <linux/clk-provider.h>
	17	+#include <linux/clkdev.h>
	18	+#include <linux/clk/clk-conf.h>
24	19	#include <linux/clk/tegra.h>
25	20	#include <linux/debugfs.h>
26	21	#include <linux/delay.h>
	22	+#include <linux/device.h>
27	23	#include <linux/err.h>
28	24	#include <linux/export.h>
29	25	#include <linux/init.h>
30	26	#include <linux/io.h>
31	27	#include <linux/iopoll.h>
32		-#include <linux/of.h>
	28	+#include <linux/irqdomain.h>
	29	+#include <linux/irq.h>
	30	+#include <linux/kernel.h>
33	31	#include <linux/of_address.h>
34	32	#include <linux/of_clk.h>
	33	+#include <linux/of.h>
	34	+#include <linux/of_irq.h>
35	35	#include <linux/of_platform.h>
	36	+#include <linux/pinctrl/pinconf-generic.h>
	37	+#include <linux/pinctrl/pinconf.h>
	38	+#include <linux/pinctrl/pinctrl.h>
36	39	#include <linux/platform_device.h>
37	40	#include <linux/pm_domain.h>
38	41	#include <linux/reboot.h>
..	..	@@ -45,6 +48,12 @@
45	48	#include <soc/tegra/fuse.h>
46	49	#include <soc/tegra/pmc.h>
47	50
	51	+#include <dt-bindings/interrupt-controller/arm-gic.h>
	52	+#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
	53	+#include <dt-bindings/gpio/tegra186-gpio.h>
	54	+#include <dt-bindings/gpio/tegra194-gpio.h>
	55	+#include <dt-bindings/soc/tegra-pmc.h>
	56	+
48	57	#define PMC_CNTRL 0x0
49	58	#define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
50	59	#define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
..	..	@@ -52,7 +61,16 @@
52	61	#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
53	62	#define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
54	63	#define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
	64	+#define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
	65	+#define PMC_CNTRL_BLINK_EN 7
55	66	#define PMC_CNTRL_MAIN_RST BIT(4)
	67	+
	68	+#define PMC_WAKE_MASK 0x0c
	69	+#define PMC_WAKE_LEVEL 0x10
	70	+#define PMC_WAKE_STATUS 0x14
	71	+#define PMC_SW_WAKE_STATUS 0x18
	72	+#define PMC_DPD_PADS_ORIDE 0x1c
	73	+#define PMC_DPD_PADS_ORIDE_BLINK 20
56	74
57	75	#define DPD_SAMPLE 0x020
58	76	#define DPD_SAMPLE_ENABLE BIT(0)
..	..	@@ -65,6 +83,7 @@
65	83
66	84	#define PWRGATE_STATUS 0x38
67	85
	86	+#define PMC_BLINK_TIMER 0x40
68	87	#define PMC_IMPL_E_33V_PWR 0x40
69	88
70	89	#define PMC_PWR_DET 0x48
..	..	@@ -78,16 +97,24 @@
78	97
79	98	#define PMC_CPUPWRGOOD_TIMER 0xc8
80	99	#define PMC_CPUPWROFF_TIMER 0xcc
	100	+#define PMC_COREPWRGOOD_TIMER 0x3c
	101	+#define PMC_COREPWROFF_TIMER 0xe0
81	102
82	103	#define PMC_PWR_DET_VALUE 0xe4
83	104
84	105	#define PMC_SCRATCH41 0x140
85	106
	107	+#define PMC_WAKE2_MASK 0x160
	108	+#define PMC_WAKE2_LEVEL 0x164
	109	+#define PMC_WAKE2_STATUS 0x168
	110	+#define PMC_SW_WAKE2_STATUS 0x16c
	111	+
	112	+#define PMC_CLK_OUT_CNTRL 0x1a8
	113	+#define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
86	114	#define PMC_SENSOR_CTRL 0x1b0
87	115	#define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
88	116	#define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
89	117
90		-#define PMC_RST_STATUS 0x1b4
91	118	#define PMC_RST_STATUS_POR 0
92	119	#define PMC_RST_STATUS_WATCHDOG 1
93	120	#define PMC_RST_STATUS_SENSOR 2
..	..	@@ -121,8 +148,88 @@
121	148	#define GPU_RG_CNTRL 0x2d4
122	149
123	150	/* Tegra186 and later */
	151	+#define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
	152	+#define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
	153	+#define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
	154	+#define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
	155	+#define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
	156	+#define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
	157	+#define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
	158	+#define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
	159	+#define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
	160	+
124	161	#define WAKE_AOWAKE_CTRL 0x4f4
125	162	#define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
	163	+
	164	+/* for secure PMC */
	165	+#define TEGRA_SMC_PMC 0xc2fffe00
	166	+#define TEGRA_SMC_PMC_READ 0xaa
	167	+#define TEGRA_SMC_PMC_WRITE 0xbb
	168	+
	169	+struct pmc_clk {
	170	+ struct clk_hw hw;
	171	+ unsigned long offs;
	172	+ u32 mux_shift;
	173	+ u32 force_en_shift;
	174	+};
	175	+
	176	+#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
	177	+
	178	+struct pmc_clk_gate {
	179	+ struct clk_hw hw;
	180	+ unsigned long offs;
	181	+ u32 shift;
	182	+};
	183	+
	184	+#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
	185	+
	186	+struct pmc_clk_init_data {
	187	+ char *name;
	188	+ const char const parents;
	189	+ int num_parents;
	190	+ int clk_id;
	191	+ u8 mux_shift;
	192	+ u8 force_en_shift;
	193	+};
	194	+
	195	+static const char * const clk_out1_parents[] = { "osc", "osc_div2",
	196	+ "osc_div4", "extern1",
	197	+};
	198	+
	199	+static const char * const clk_out2_parents[] = { "osc", "osc_div2",
	200	+ "osc_div4", "extern2",
	201	+};
	202	+
	203	+static const char * const clk_out3_parents[] = { "osc", "osc_div2",
	204	+ "osc_div4", "extern3",
	205	+};
	206	+
	207	+static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
	208	+ {
	209	+ .name = "pmc_clk_out_1",
	210	+ .parents = clk_out1_parents,
	211	+ .num_parents = ARRAY_SIZE(clk_out1_parents),
	212	+ .clk_id = TEGRA_PMC_CLK_OUT_1,
	213	+ .mux_shift = 6,
	214	+ .force_en_shift = 2,
	215	+ },
	216	+ {
	217	+ .name = "pmc_clk_out_2",
	218	+ .parents = clk_out2_parents,
	219	+ .num_parents = ARRAY_SIZE(clk_out2_parents),
	220	+ .clk_id = TEGRA_PMC_CLK_OUT_2,
	221	+ .mux_shift = 14,
	222	+ .force_en_shift = 10,
	223	+ },
	224	+ {
	225	+ .name = "pmc_clk_out_3",
	226	+ .parents = clk_out3_parents,
	227	+ .num_parents = ARRAY_SIZE(clk_out3_parents),
	228	+ .clk_id = TEGRA_PMC_CLK_OUT_3,
	229	+ .mux_shift = 22,
	230	+ .force_en_shift = 18,
	231	+ },
	232	+};
126	233
127	234	struct tegra_powergate {
128	235	struct generic_pm_domain genpd;
..	..	@@ -137,6 +244,7 @@
137	244	enum tegra_io_pad id;
138	245	unsigned int dpd;
139	246	unsigned int voltage;
	247	+ const char *name;
140	248	};
141	249
142	250	struct tegra_pmc_regs {
..	..	@@ -145,7 +253,44 @@
145	253	unsigned int dpd_status;
146	254	unsigned int dpd2_req;
147	255	unsigned int dpd2_status;
	256	+ unsigned int rst_status;
	257	+ unsigned int rst_source_shift;
	258	+ unsigned int rst_source_mask;
	259	+ unsigned int rst_level_shift;
	260	+ unsigned int rst_level_mask;
148	261	};
	262	+
	263	+struct tegra_wake_event {
	264	+ const char *name;
	265	+ unsigned int id;
	266	+ unsigned int irq;
	267	+ struct {
	268	+ unsigned int instance;
	269	+ unsigned int pin;
	270	+ } gpio;
	271	+};
	272	+
	273	+#define TEGRA_WAKE_IRQ(_name, _id, _irq) \
	274	+ { \
	275	+ .name = _name, \
	276	+ .id = _id, \
	277	+ .irq = _irq, \
	278	+ .gpio = { \
	279	+ .instance = UINT_MAX, \
	280	+ .pin = UINT_MAX, \
	281	+ }, \
	282	+ }
	283	+
	284	+#define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
	285	+ { \
	286	+ .name = _name, \
	287	+ .id = _id, \
	288	+ .irq = 0, \
	289	+ .gpio = { \
	290	+ .instance = _instance, \
	291	+ .pin = _pin, \
	292	+ }, \
	293	+ }
149	294
150	295	struct tegra_pmc_soc {
151	296	unsigned int num_powergates;
..	..	@@ -157,23 +302,52 @@
157	302	bool has_gpu_clamps;
158	303	bool needs_mbist_war;
159	304	bool has_impl_33v_pwr;
	305	+ bool maybe_tz_only;
160	306
161	307	const struct tegra_io_pad_soc *io_pads;
162	308	unsigned int num_io_pads;
	309	+
	310	+ const struct pinctrl_pin_desc *pin_descs;
	311	+ unsigned int num_pin_descs;
163	312
164	313	const struct tegra_pmc_regs *regs;
165	314	void (init)(struct tegra_pmc pmc);
166	315	void (setup_irq_polarity)(struct tegra_pmc pmc,
167	316	struct device_node *np,
168	317	bool invert);
	318	+ int (irq_set_wake)(struct irq_data data, unsigned int on);
	319	+ int (irq_set_type)(struct irq_data data, unsigned int type);
	320	+ int (powergate_set)(struct tegra_pmc pmc, unsigned int id,
	321	+ bool new_state);
	322	+
	323	+ const char * const *reset_sources;
	324	+ unsigned int num_reset_sources;
	325	+ const char * const *reset_levels;
	326	+ unsigned int num_reset_levels;
	327	+
	328	+ /*
	329	+ * These describe events that can wake the system from sleep (i.e.
	330	+ * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
	331	+ * are dealt with in the LIC.
	332	+ */
	333	+ const struct tegra_wake_event *wake_events;
	334	+ unsigned int num_wake_events;
	335	+
	336	+ const struct pmc_clk_init_data *pmc_clks_data;
	337	+ unsigned int num_pmc_clks;
	338	+ bool has_blink_output;
169	339	};
170	340
171	341	/**
172	342	* struct tegra_pmc - NVIDIA Tegra PMC
173	343	* @dev: pointer to PMC device structure
174	344	* @base: pointer to I/O remapped register region
	345	+ * @wake: pointer to I/O remapped region for WAKE registers
	346	+ * @aotag: pointer to I/O remapped region for AOTAG registers
	347	+ * @scratch: pointer to I/O remapped region for scratch registers
175	348	* @clk: pointer to pclk clock
176	349	* @soc: pointer to SoC data structure
	350	+ * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
177	351	* @debugfs: pointer to debugfs entry
178	352	* @rate: currently configured rate of pclk
179	353	* @suspend_mode: lowest suspend mode available
..	..	@@ -190,6 +364,10 @@
190	364	* @lp0_vec_size: size of the LP0 warm boot code
191	365	* @powergates_available: Bitmap of available power gates
192	366	* @powergates_lock: mutex for power gate register access
	367	+ * @pctl_dev: pin controller exposed by the PMC
	368	+ * @domain: IRQ domain provided by the PMC
	369	+ * @irq: chip implementation for the IRQ domain
	370	+ * @clk_nb: pclk clock changes handler
193	371	*/
194	372	struct tegra_pmc {
195	373	struct device *dev;
..	..	@@ -201,6 +379,7 @@
201	379	struct dentry *debugfs;
202	380
203	381	const struct tegra_pmc_soc *soc;
	382	+ bool tz_only;
204	383
205	384	unsigned long rate;
206	385
..	..	@@ -219,6 +398,13 @@
219	398	DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
220	399
221	400	struct mutex powergates_lock;
	401	+
	402	+ struct pinctrl_dev *pctl_dev;
	403	+
	404	+ struct irq_domain *domain;
	405	+ struct irq_chip irq;
	406	+
	407	+ struct notifier_block clk_nb;
222	408	};
223	409
224	410	static struct tegra_pmc *pmc = &(struct tegra_pmc) {
..	..	@@ -232,30 +418,85 @@
232	418	return container_of(domain, struct tegra_powergate, genpd);
233	419	}
234	420
235		-static u32 tegra_pmc_readl(unsigned long offset)
	421	+static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
236	422	{
	423	+ struct arm_smccc_res res;
	424	+
	425	+ if (pmc->tz_only) {
	426	+ arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
	427	+ 0, 0, 0, &res);
	428	+ if (res.a0) {
	429	+ if (pmc->dev)
	430	+ dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
	431	+ __func__, res.a0);
	432	+ else
	433	+ pr_warn("%s(): SMC failed: %lu\n", __func__,
	434	+ res.a0);
	435	+ }
	436	+
	437	+ return res.a1;
	438	+ }
	439	+
237	440	return readl(pmc->base + offset);
238	441	}
239	442
240		-static void tegra_pmc_writel(u32 value, unsigned long offset)
	443	+static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
	444	+ unsigned long offset)
241	445	{
242		- writel(value, pmc->base + offset);
	446	+ struct arm_smccc_res res;
	447	+
	448	+ if (pmc->tz_only) {
	449	+ arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
	450	+ value, 0, 0, 0, 0, &res);
	451	+ if (res.a0) {
	452	+ if (pmc->dev)
	453	+ dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
	454	+ __func__, res.a0);
	455	+ else
	456	+ pr_warn("%s(): SMC failed: %lu\n", __func__,
	457	+ res.a0);
	458	+ }
	459	+ } else {
	460	+ writel(value, pmc->base + offset);
	461	+ }
243	462	}
244	463
	464	+static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
	465	+{
	466	+ if (pmc->tz_only)
	467	+ return tegra_pmc_readl(pmc, offset);
	468	+
	469	+ return readl(pmc->scratch + offset);
	470	+}
	471	+
	472	+static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
	473	+ unsigned long offset)
	474	+{
	475	+ if (pmc->tz_only)
	476	+ tegra_pmc_writel(pmc, value, offset);
	477	+ else
	478	+ writel(value, pmc->scratch + offset);
	479	+}
	480	+
	481	+/*
	482	+ * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
	483	+ * This currently doesn't work because readx_poll_timeout() can only operate
	484	+ * on functions that take a single argument.
	485	+ */
245	486	static inline bool tegra_powergate_state(int id)
246	487	{
247	488	if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
248		- return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0;
	489	+ return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
249	490	else
250		- return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0;
	491	+ return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
251	492	}
252	493
253		-static inline bool tegra_powergate_is_valid(int id)
	494	+static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
254	495	{
255	496	return (pmc->soc && pmc->soc->powergates[id]);
256	497	}
257	498
258		-static inline bool tegra_powergate_is_available(int id)
	499	+static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
259	500	{
260	501	return test_bit(id, pmc->powergates_available);
261	502	}
..	..	@@ -268,7 +509,7 @@
268	509	return -EINVAL;
269	510
270	511	for (i = 0; i < pmc->soc->num_powergates; i++) {
271		- if (!tegra_powergate_is_valid(i))
	512	+ if (!tegra_powergate_is_valid(pmc, i))
272	513	continue;
273	514
274	515	if (!strcmp(name, pmc->soc->powergates[i]))
..	..	@@ -278,14 +519,72 @@
278	519	return -ENODEV;
279	520	}
280	521
	522	+static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,
	523	+ bool new_state)
	524	+{
	525	+ unsigned int retries = 100;
	526	+ bool status;
	527	+ int ret;
	528	+
	529	+ /*
	530	+ * As per TRM documentation, the toggle command will be dropped by PMC
	531	+ * if there is contention with a HW-initiated toggling (i.e. CPU core
	532	+ * power-gated), the command should be retried in that case.
	533	+ */
	534	+ do {
	535	+ tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START \| id, PWRGATE_TOGGLE);
	536	+
	537	+ /* wait for PMC to execute the command */
	538	+ ret = readx_poll_timeout(tegra_powergate_state, id, status,
	539	+ status == new_state, 1, 10);
	540	+ } while (ret == -ETIMEDOUT && retries--);
	541	+
	542	+ return ret;
	543	+}
	544	+
	545	+static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)
	546	+{
	547	+ return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);
	548	+}
	549	+
	550	+static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,
	551	+ bool new_state)
	552	+{
	553	+ bool status;
	554	+ int err;
	555	+
	556	+ /* wait while PMC power gating is contended */
	557	+ err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
	558	+ status == true, 1, 100);
	559	+ if (err)
	560	+ return err;
	561	+
	562	+ tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START \| id, PWRGATE_TOGGLE);
	563	+
	564	+ /* wait for PMC to accept the command */
	565	+ err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
	566	+ status == true, 1, 100);
	567	+ if (err)
	568	+ return err;
	569	+
	570	+ /* wait for PMC to execute the command */
	571	+ err = readx_poll_timeout(tegra_powergate_state, id, status,
	572	+ status == new_state, 10, 100000);
	573	+ if (err)
	574	+ return err;
	575	+
	576	+ return 0;
	577	+}
	578	+
281	579	/**
282	580	* tegra_powergate_set() - set the state of a partition
	581	+ * @pmc: power management controller
283	582	* @id: partition ID
284	583	* @new_state: new state of the partition
285	584	*/
286		-static int tegra_powergate_set(unsigned int id, bool new_state)
	585	+static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
	586	+ bool new_state)
287	587	{
288		- bool status;
289	588	int err;
290	589
291	590	if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
..	..	@@ -298,17 +597,15 @@
298	597	return 0;
299	598	}
300	599
301		- tegra_pmc_writel(PWRGATE_TOGGLE_START \| id, PWRGATE_TOGGLE);
302		-
303		- err = readx_poll_timeout(tegra_powergate_state, id, status,
304		- status == new_state, 10, 100000);
	600	+ err = pmc->soc->powergate_set(pmc, id, new_state);
305	601
306	602	mutex_unlock(&pmc->powergates_lock);
307	603
308	604	return err;
309	605	}
310	606
311		-static int __tegra_powergate_remove_clamping(unsigned int id)
	607	+static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
	608	+ unsigned int id)
312	609	{
313	610	u32 mask;
314	611
..	..	@@ -320,7 +617,7 @@
320	617	*/
321	618	if (id == TEGRA_POWERGATE_3D) {
322	619	if (pmc->soc->has_gpu_clamps) {
323		- tegra_pmc_writel(0, GPU_RG_CNTRL);
	620	+ tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
324	621	goto out;
325	622	}
326	623	}
..	..	@@ -336,7 +633,7 @@
336	633	else
337	634	mask = (1 << id);
338	635
339		- tegra_pmc_writel(mask, REMOVE_CLAMPING);
	636	+ tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
340	637
341	638	out:
342	639	mutex_unlock(&pmc->powergates_lock);
..	..	@@ -388,7 +685,7 @@
388	685
389	686	usleep_range(10, 20);
390	687
391		- err = tegra_powergate_set(pg->id, true);
	688	+ err = tegra_powergate_set(pg->pmc, pg->id, true);
392	689	if (err < 0)
393	690	return err;
394	691
..	..	@@ -400,7 +697,7 @@
400	697
401	698	usleep_range(10, 20);
402	699
403		- err = __tegra_powergate_remove_clamping(pg->id);
	700	+ err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
404	701	if (err)
405	702	goto disable_clks;
406	703
..	..	@@ -427,7 +724,7 @@
427	724	usleep_range(10, 20);
428	725
429	726	powergate_off:
430		- tegra_powergate_set(pg->id, false);
	727	+ tegra_powergate_set(pg->pmc, pg->id, false);
431	728
432	729	return err;
433	730	}
..	..	@@ -452,7 +749,7 @@
452	749
453	750	usleep_range(10, 20);
454	751
455		- err = tegra_powergate_set(pg->id, false);
	752	+ err = tegra_powergate_set(pg->pmc, pg->id, false);
456	753	if (err)
457	754	goto assert_resets;
458	755
..	..	@@ -473,25 +770,40 @@
473	770	static int tegra_genpd_power_on(struct generic_pm_domain *domain)
474	771	{
475	772	struct tegra_powergate *pg = to_powergate(domain);
	773	+ struct device *dev = pg->pmc->dev;
476	774	int err;
477	775
478	776	err = tegra_powergate_power_up(pg, true);
479		- if (err)
480		- pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name,
481		- err);
	777	+ if (err) {
	778	+ dev_err(dev, "failed to turn on PM domain %s: %d\n",
	779	+ pg->genpd.name, err);
	780	+ goto out;
	781	+ }
482	782
	783	+ reset_control_release(pg->reset);
	784	+
	785	+out:
483	786	return err;
484	787	}
485	788
486	789	static int tegra_genpd_power_off(struct generic_pm_domain *domain)
487	790	{
488	791	struct tegra_powergate *pg = to_powergate(domain);
	792	+ struct device *dev = pg->pmc->dev;
489	793	int err;
490	794
	795	+ err = reset_control_acquire(pg->reset);
	796	+ if (err < 0) {
	797	+ pr_err("failed to acquire resets: %d\n", err);
	798	+ return err;
	799	+ }
	800	+
491	801	err = tegra_powergate_power_down(pg);
492		- if (err)
493		- pr_err("failed to turn off PM domain %s: %d\n",
494		- pg->genpd.name, err);
	802	+ if (err) {
	803	+ dev_err(dev, "failed to turn off PM domain %s: %d\n",
	804	+ pg->genpd.name, err);
	805	+ reset_control_release(pg->reset);
	806	+ }
495	807
496	808	return err;
497	809	}
..	..	@@ -502,11 +814,12 @@
502	814	*/
503	815	int tegra_powergate_power_on(unsigned int id)
504	816	{
505		- if (!tegra_powergate_is_available(id))
	817	+ if (!tegra_powergate_is_available(pmc, id))
506	818	return -EINVAL;
507	819
508		- return tegra_powergate_set(id, true);
	820	+ return tegra_powergate_set(pmc, id, true);
509	821	}
	822	+EXPORT_SYMBOL(tegra_powergate_power_on);
510	823
511	824	/**
512	825	* tegra_powergate_power_off() - power off partition
..	..	@@ -514,20 +827,21 @@
514	827	*/
515	828	int tegra_powergate_power_off(unsigned int id)
516	829	{
517		- if (!tegra_powergate_is_available(id))
	830	+ if (!tegra_powergate_is_available(pmc, id))
518	831	return -EINVAL;
519	832
520		- return tegra_powergate_set(id, false);
	833	+ return tegra_powergate_set(pmc, id, false);
521	834	}
522	835	EXPORT_SYMBOL(tegra_powergate_power_off);
523	836
524	837	/**
525	838	* tegra_powergate_is_powered() - check if partition is powered
	839	+ * @pmc: power management controller
526	840	* @id: partition ID
527	841	*/
528		-int tegra_powergate_is_powered(unsigned int id)
	842	+static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
529	843	{
530		- if (!tegra_powergate_is_valid(id))
	844	+ if (!tegra_powergate_is_valid(pmc, id))
531	845	return -EINVAL;
532	846
533	847	return tegra_powergate_state(id);
..	..	@@ -539,10 +853,10 @@
539	853	*/
540	854	int tegra_powergate_remove_clamping(unsigned int id)
541	855	{
542		- if (!tegra_powergate_is_available(id))
	856	+ if (!tegra_powergate_is_available(pmc, id))
543	857	return -EINVAL;
544	858
545		- return __tegra_powergate_remove_clamping(id);
	859	+ return __tegra_powergate_remove_clamping(pmc, id);
546	860	}
547	861	EXPORT_SYMBOL(tegra_powergate_remove_clamping);
548	862
..	..	@@ -560,7 +874,7 @@
560	874	struct tegra_powergate *pg;
561	875	int err;
562	876
563		- if (!tegra_powergate_is_available(id))
	877	+ if (!tegra_powergate_is_available(pmc, id))
564	878	return -EINVAL;
565	879
566	880	pg = kzalloc(sizeof(*pg), GFP_KERNEL);
..	..	@@ -575,7 +889,8 @@
575	889
576	890	err = tegra_powergate_power_up(pg, false);
577	891	if (err)
578		- pr_err("failed to turn on partition %d: %d\n", id, err);
	892	+ dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
	893	+ err);
579	894
580	895	kfree(pg);
581	896
..	..	@@ -583,15 +898,16 @@
583	898	}
584	899	EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
585	900
586		-#ifdef CONFIG_SMP
587	901	/**
588	902	* tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
	903	+ * @pmc: power management controller
589	904	* @cpuid: CPU partition ID
590	905	*
591	906	* Returns the partition ID corresponding to the CPU partition ID or a
592	907	* negative error code on failure.
593	908	*/
594		-static int tegra_get_cpu_powergate_id(unsigned int cpuid)
	909	+static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
	910	+ unsigned int cpuid)
595	911	{
596	912	if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
597	913	return pmc->soc->cpu_powergates[cpuid];
..	..	@@ -607,11 +923,11 @@
607	923	{
608	924	int id;
609	925
610		- id = tegra_get_cpu_powergate_id(cpuid);
	926	+ id = tegra_get_cpu_powergate_id(pmc, cpuid);
611	927	if (id < 0)
612	928	return false;
613	929
614		- return tegra_powergate_is_powered(id);
	930	+ return tegra_powergate_is_powered(pmc, id);
615	931	}
616	932
617	933	/**
..	..	@@ -622,11 +938,11 @@
622	938	{
623	939	int id;
624	940
625		- id = tegra_get_cpu_powergate_id(cpuid);
	941	+ id = tegra_get_cpu_powergate_id(pmc, cpuid);
626	942	if (id < 0)
627	943	return id;
628	944
629		- return tegra_powergate_set(id, true);
	945	+ return tegra_powergate_set(pmc, id, true);
630	946	}
631	947
632	948	/**
..	..	@@ -637,13 +953,12 @@
637	953	{
638	954	int id;
639	955
640		- id = tegra_get_cpu_powergate_id(cpuid);
	956	+ id = tegra_get_cpu_powergate_id(pmc, cpuid);
641	957	if (id < 0)
642	958	return id;
643	959
644	960	return tegra_powergate_remove_clamping(id);
645	961	}
646		-#endif /* CONFIG_SMP */
647	962
648	963	static int tegra_pmc_restart_notify(struct notifier_block *this,
649	964	unsigned long action, void *data)
..	..	@@ -651,7 +966,7 @@
651	966	const char *cmd = data;
652	967	u32 value;
653	968
654		- value = readl(pmc->scratch + pmc->soc->regs->scratch0);
	969	+ value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
655	970	value &= ~PMC_SCRATCH0_MODE_MASK;
656	971
657	972	if (cmd) {
..	..	@@ -665,12 +980,12 @@
665	980	value \|= PMC_SCRATCH0_MODE_RCM;
666	981	}
667	982
668		- writel(value, pmc->scratch + pmc->soc->regs->scratch0);
	983	+ tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
669	984
670	985	/* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
671		- value = tegra_pmc_readl(PMC_CNTRL);
	986	+ value = tegra_pmc_readl(pmc, PMC_CNTRL);
672	987	value \|= PMC_CNTRL_MAIN_RST;
673		- tegra_pmc_writel(value, PMC_CNTRL);
	988	+ tegra_pmc_writel(pmc, value, PMC_CNTRL);
674	989
675	990	return NOTIFY_DONE;
676	991	}
..	..	@@ -689,7 +1004,7 @@
689	1004	seq_printf(s, "------------------\n");
690	1005
691	1006	for (i = 0; i < pmc->soc->num_powergates; i++) {
692		- status = tegra_powergate_is_powered(i);
	1007	+ status = tegra_powergate_is_powered(pmc, i);
693	1008	if (status < 0)
694	1009	continue;
695	1010
..	..	@@ -700,17 +1015,7 @@
700	1015	return 0;
701	1016	}
702	1017
703		-static int powergate_open(struct inode inode, struct file file)
704		-{
705		- return single_open(file, powergate_show, inode->i_private);
706		-}
707		-
708		-static const struct file_operations powergate_fops = {
709		- .open = powergate_open,
710		- .read = seq_read,
711		- .llseek = seq_lseek,
712		- .release = single_release,
713		-};
	1018	+DEFINE_SHOW_ATTRIBUTE(powergate);
714	1019
715	1020	static int tegra_powergate_debugfs_init(void)
716	1021	{
..	..	@@ -761,39 +1066,56 @@
761	1066	static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
762	1067	struct device_node *np, bool off)
763	1068	{
	1069	+ struct device *dev = pg->pmc->dev;
764	1070	int err;
765	1071
766		- pg->reset = of_reset_control_array_get_exclusive(np);
	1072	+ pg->reset = of_reset_control_array_get_exclusive_released(np);
767	1073	if (IS_ERR(pg->reset)) {
768	1074	err = PTR_ERR(pg->reset);
769		- pr_err("failed to get device resets: %d\n", err);
	1075	+ dev_err(dev, "failed to get device resets: %d\n", err);
770	1076	return err;
771	1077	}
772	1078
773		- if (off)
774		- err = reset_control_assert(pg->reset);
775		- else
776		- err = reset_control_deassert(pg->reset);
	1079	+ err = reset_control_acquire(pg->reset);
	1080	+ if (err < 0) {
	1081	+ pr_err("failed to acquire resets: %d\n", err);
	1082	+ goto out;
	1083	+ }
777	1084
778		- if (err)
	1085	+ if (off) {
	1086	+ err = reset_control_assert(pg->reset);
	1087	+ } else {
	1088	+ err = reset_control_deassert(pg->reset);
	1089	+ if (err < 0)
	1090	+ goto out;
	1091	+
	1092	+ reset_control_release(pg->reset);
	1093	+ }
	1094	+
	1095	+out:
	1096	+ if (err) {
	1097	+ reset_control_release(pg->reset);
779	1098	reset_control_put(pg->reset);
	1099	+ }
780	1100
781	1101	return err;
782	1102	}
783	1103
784		-static void tegra_powergate_add(struct tegra_pmc pmc, struct device_node np)
	1104	+static int tegra_powergate_add(struct tegra_pmc pmc, struct device_node np)
785	1105	{
	1106	+ struct device *dev = pmc->dev;
786	1107	struct tegra_powergate *pg;
787		- int id, err;
	1108	+ int id, err = 0;
788	1109	bool off;
789	1110
790	1111	pg = kzalloc(sizeof(*pg), GFP_KERNEL);
791	1112	if (!pg)
792		- return;
	1113	+ return -ENOMEM;
793	1114
794	1115	id = tegra_powergate_lookup(pmc, np->name);
795	1116	if (id < 0) {
796		- pr_err("powergate lookup failed for %s: %d\n", np->name, id);
	1117	+ dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
	1118	+ err = -ENODEV;
797	1119	goto free_mem;
798	1120	}
799	1121
..	..	@@ -809,17 +1131,17 @@
809	1131	pg->genpd.power_on = tegra_genpd_power_on;
810	1132	pg->pmc = pmc;
811	1133
812		- off = !tegra_powergate_is_powered(pg->id);
	1134	+ off = !tegra_powergate_is_powered(pmc, pg->id);
813	1135
814	1136	err = tegra_powergate_of_get_clks(pg, np);
815	1137	if (err < 0) {
816		- pr_err("failed to get clocks for %s: %d\n", np->name, err);
	1138	+ dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
817	1139	goto set_available;
818	1140	}
819	1141
820	1142	err = tegra_powergate_of_get_resets(pg, np, off);
821	1143	if (err < 0) {
822		- pr_err("failed to get resets for %s: %d\n", np->name, err);
	1144	+ dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
823	1145	goto remove_clks;
824	1146	}
825	1147
..	..	@@ -830,39 +1152,23 @@
830	1152	goto remove_resets;
831	1153	}
832	1154
833		- /*
834		- * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB
835		- * host and super-speed partitions. Once the XHCI driver
836		- * manages the partitions itself this code can be removed. Note
837		- * that we don't register these partitions with the genpd core
838		- * to avoid it from powering down the partitions as they appear
839		- * to be unused.
840		- */
841		- if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) &&
842		- (id == TEGRA_POWERGATE_XUSBA \|\| id == TEGRA_POWERGATE_XUSBC)) {
843		- if (off)
844		- WARN_ON(tegra_powergate_power_up(pg, true));
845		-
846		- goto remove_resets;
847		- }
848		-
849	1155	err = pm_genpd_init(&pg->genpd, NULL, off);
850	1156	if (err < 0) {
851		- pr_err("failed to initialise PM domain %s: %d\n", np->name,
	1157	+ dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
852	1158	err);
853	1159	goto remove_resets;
854	1160	}
855	1161
856	1162	err = of_genpd_add_provider_simple(np, &pg->genpd);
857	1163	if (err < 0) {
858		- pr_err("failed to add PM domain provider for %s: %d\n",
859		- np->name, err);
	1164	+ dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
	1165	+ np, err);
860	1166	goto remove_genpd;
861	1167	}
862	1168
863		- pr_debug("added PM domain %s\n", pg->genpd.name);
	1169	+ dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
864	1170
865		- return;
	1171	+ return 0;
866	1172
867	1173	remove_genpd:
868	1174	pm_genpd_remove(&pg->genpd);
..	..	@@ -881,25 +1187,67 @@
881	1187
882	1188	free_mem:
883	1189	kfree(pg);
	1190	+
	1191	+ return err;
884	1192	}
885	1193
886		-static void tegra_powergate_init(struct tegra_pmc *pmc,
887		- struct device_node *parent)
	1194	+static int tegra_powergate_init(struct tegra_pmc *pmc,
	1195	+ struct device_node *parent)
888	1196	{
889	1197	struct device_node np, child;
890		- unsigned int i;
	1198	+ int err = 0;
891	1199
892		- /* Create a bitmap of the available and valid partitions */
893		- for (i = 0; i < pmc->soc->num_powergates; i++)
894		- if (pmc->soc->powergates[i])
895		- set_bit(i, pmc->powergates_available);
	1200	+ np = of_get_child_by_name(parent, "powergates");
	1201	+ if (!np)
	1202	+ return 0;
	1203	+
	1204	+ for_each_child_of_node(np, child) {
	1205	+ err = tegra_powergate_add(pmc, child);
	1206	+ if (err < 0) {
	1207	+ of_node_put(child);
	1208	+ break;
	1209	+ }
	1210	+ }
	1211	+
	1212	+ of_node_put(np);
	1213	+
	1214	+ return err;
	1215	+}
	1216	+
	1217	+static void tegra_powergate_remove(struct generic_pm_domain *genpd)
	1218	+{
	1219	+ struct tegra_powergate *pg = to_powergate(genpd);
	1220	+
	1221	+ reset_control_put(pg->reset);
	1222	+
	1223	+ while (pg->num_clks--)
	1224	+ clk_put(pg->clks[pg->num_clks]);
	1225	+
	1226	+ kfree(pg->clks);
	1227	+
	1228	+ set_bit(pg->id, pmc->powergates_available);
	1229	+
	1230	+ kfree(pg);
	1231	+}
	1232	+
	1233	+static void tegra_powergate_remove_all(struct device_node *parent)
	1234	+{
	1235	+ struct generic_pm_domain *genpd;
	1236	+ struct device_node np, child;
896	1237
897	1238	np = of_get_child_by_name(parent, "powergates");
898	1239	if (!np)
899	1240	return;
900	1241
901		- for_each_child_of_node(np, child)
902		- tegra_powergate_add(pmc, child);
	1242	+ for_each_child_of_node(np, child) {
	1243	+ of_genpd_del_provider(child);
	1244	+
	1245	+ genpd = of_genpd_remove_last(child);
	1246	+ if (IS_ERR(genpd))
	1247	+ continue;
	1248	+
	1249	+ tegra_powergate_remove(genpd);
	1250	+ }
903	1251
904	1252	of_node_put(np);
905	1253	}
..	..	@@ -916,15 +1264,17 @@
916	1264	return NULL;
917	1265	}
918	1266
919		-static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request,
920		- unsigned long status, u32 mask)
	1267	+static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
	1268	+ enum tegra_io_pad id,
	1269	+ unsigned long *request,
	1270	+ unsigned long *status,
	1271	+ u32 *mask)
921	1272	{
922	1273	const struct tegra_io_pad_soc *pad;
923		- unsigned long rate, value;
924	1274
925	1275	pad = tegra_io_pad_find(pmc, id);
926	1276	if (!pad) {
927		- pr_err("invalid I/O pad ID %u\n", id);
	1277	+ dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
928	1278	return -ENOENT;
929	1279	}
930	1280
..	..	@@ -941,33 +1291,47 @@
941	1291	*request = pmc->soc->regs->dpd2_req;
942	1292	}
943	1293
	1294	+ return 0;
	1295	+}
	1296	+
	1297	+static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
	1298	+ unsigned long request, unsigned long status,
	1299	+ u32 *mask)
	1300	+{
	1301	+ unsigned long rate, value;
	1302	+ int err;
	1303	+
	1304	+ err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
	1305	+ if (err)
	1306	+ return err;
	1307	+
944	1308	if (pmc->clk) {
945		- rate = clk_get_rate(pmc->clk);
	1309	+ rate = pmc->rate;
946	1310	if (!rate) {
947		- pr_err("failed to get clock rate\n");
	1311	+ dev_err(pmc->dev, "failed to get clock rate\n");
948	1312	return -ENODEV;
949	1313	}
950	1314
951		- tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
	1315	+ tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
952	1316
953	1317	/* must be at least 200 ns, in APB (PCLK) clock cycles */
954	1318	value = DIV_ROUND_UP(1000000000, rate);
955	1319	value = DIV_ROUND_UP(200, value);
956		- tegra_pmc_writel(value, SEL_DPD_TIM);
	1320	+ tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
957	1321	}
958	1322
959	1323	return 0;
960	1324	}
961	1325
962		-static int tegra_io_pad_poll(unsigned long offset, u32 mask,
963		- u32 val, unsigned long timeout)
	1326	+static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
	1327	+ u32 mask, u32 val, unsigned long timeout)
964	1328	{
965	1329	u32 value;
966	1330
967	1331	timeout = jiffies + msecs_to_jiffies(timeout);
968	1332
969	1333	while (time_after(timeout, jiffies)) {
970		- value = tegra_pmc_readl(offset);
	1334	+ value = tegra_pmc_readl(pmc, offset);
971	1335	if ((value & mask) == val)
972	1336	return 0;
973	1337
..	..	@@ -977,10 +1341,10 @@
977	1341	return -ETIMEDOUT;
978	1342	}
979	1343
980		-static void tegra_io_pad_unprepare(void)
	1344	+static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
981	1345	{
982	1346	if (pmc->clk)
983		- tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE);
	1347	+ tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
984	1348	}
985	1349
986	1350	/**
..	..	@@ -997,21 +1361,21 @@
997	1361
998	1362	mutex_lock(&pmc->powergates_lock);
999	1363
1000		- err = tegra_io_pad_prepare(id, &request, &status, &mask);
	1364	+ err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1001	1365	if (err < 0) {
1002		- pr_err("failed to prepare I/O pad: %d\n", err);
	1366	+ dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1003	1367	goto unlock;
1004	1368	}
1005	1369
1006		- tegra_pmc_writel(IO_DPD_REQ_CODE_OFF \| mask, request);
	1370	+ tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF \| mask, request);
1007	1371
1008		- err = tegra_io_pad_poll(status, mask, 0, 250);
	1372	+ err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1009	1373	if (err < 0) {
1010		- pr_err("failed to enable I/O pad: %d\n", err);
	1374	+ dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1011	1375	goto unlock;
1012	1376	}
1013	1377
1014		- tegra_io_pad_unprepare();
	1378	+ tegra_io_pad_unprepare(pmc);
1015	1379
1016	1380	unlock:
1017	1381	mutex_unlock(&pmc->powergates_lock);
..	..	@@ -1033,21 +1397,21 @@
1033	1397
1034	1398	mutex_lock(&pmc->powergates_lock);
1035	1399
1036		- err = tegra_io_pad_prepare(id, &request, &status, &mask);
	1400	+ err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1037	1401	if (err < 0) {
1038		- pr_err("failed to prepare I/O pad: %d\n", err);
	1402	+ dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1039	1403	goto unlock;
1040	1404	}
1041	1405
1042		- tegra_pmc_writel(IO_DPD_REQ_CODE_ON \| mask, request);
	1406	+ tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON \| mask, request);
1043	1407
1044		- err = tegra_io_pad_poll(status, mask, mask, 250);
	1408	+ err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1045	1409	if (err < 0) {
1046		- pr_err("failed to disable I/O pad: %d\n", err);
	1410	+ dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1047	1411	goto unlock;
1048	1412	}
1049	1413
1050		- tegra_io_pad_unprepare();
	1414	+ tegra_io_pad_unprepare(pmc);
1051	1415
1052	1416	unlock:
1053	1417	mutex_unlock(&pmc->powergates_lock);
..	..	@@ -1055,8 +1419,24 @@
1055	1419	}
1056	1420	EXPORT_SYMBOL(tegra_io_pad_power_disable);
1057	1421
1058		-int tegra_io_pad_set_voltage(enum tegra_io_pad id,
1059		- enum tegra_io_pad_voltage voltage)
	1422	+static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
	1423	+{
	1424	+ unsigned long request, status;
	1425	+ u32 mask, value;
	1426	+ int err;
	1427	+
	1428	+ err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
	1429	+ &mask);
	1430	+ if (err)
	1431	+ return err;
	1432	+
	1433	+ value = tegra_pmc_readl(pmc, status);
	1434	+
	1435	+ return !(value & mask);
	1436	+}
	1437	+
	1438	+static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
	1439	+ int voltage)
1060	1440	{
1061	1441	const struct tegra_io_pad_soc *pad;
1062	1442	u32 value;
..	..	@@ -1071,29 +1451,29 @@
1071	1451	mutex_lock(&pmc->powergates_lock);
1072	1452
1073	1453	if (pmc->soc->has_impl_33v_pwr) {
1074		- value = tegra_pmc_readl(PMC_IMPL_E_33V_PWR);
	1454	+ value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1075	1455
1076		- if (voltage == TEGRA_IO_PAD_1800000UV)
	1456	+ if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1077	1457	value &= ~BIT(pad->voltage);
1078	1458	else
1079	1459	value \|= BIT(pad->voltage);
1080	1460
1081		- tegra_pmc_writel(value, PMC_IMPL_E_33V_PWR);
	1461	+ tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1082	1462	} else {
1083	1463	/* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1084		- value = tegra_pmc_readl(PMC_PWR_DET);
	1464	+ value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1085	1465	value \|= BIT(pad->voltage);
1086		- tegra_pmc_writel(value, PMC_PWR_DET);
	1466	+ tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1087	1467
1088	1468	/* update I/O voltage */
1089		- value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
	1469	+ value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1090	1470
1091		- if (voltage == TEGRA_IO_PAD_1800000UV)
	1471	+ if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1092	1472	value &= ~BIT(pad->voltage);
1093	1473	else
1094	1474	value \|= BIT(pad->voltage);
1095	1475
1096		- tegra_pmc_writel(value, PMC_PWR_DET_VALUE);
	1476	+ tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1097	1477	}
1098	1478
1099	1479	mutex_unlock(&pmc->powergates_lock);
..	..	@@ -1102,9 +1482,8 @@
1102	1482
1103	1483	return 0;
1104	1484	}
1105		-EXPORT_SYMBOL(tegra_io_pad_set_voltage);
1106	1485
1107		-int tegra_io_pad_get_voltage(enum tegra_io_pad id)
	1486	+static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1108	1487	{
1109	1488	const struct tegra_io_pad_soc *pad;
1110	1489	u32 value;
..	..	@@ -1117,16 +1496,15 @@
1117	1496	return -ENOTSUPP;
1118	1497
1119	1498	if (pmc->soc->has_impl_33v_pwr)
1120		- value = tegra_pmc_readl(PMC_IMPL_E_33V_PWR);
	1499	+ value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1121	1500	else
1122		- value = tegra_pmc_readl(PMC_PWR_DET_VALUE);
	1501	+ value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1123	1502
1124	1503	if ((value & BIT(pad->voltage)) == 0)
1125		- return TEGRA_IO_PAD_1800000UV;
	1504	+ return TEGRA_IO_PAD_VOLTAGE_1V8;
1126	1505
1127		- return TEGRA_IO_PAD_3300000UV;
	1506	+ return TEGRA_IO_PAD_VOLTAGE_3V3;
1128	1507	}
1129		-EXPORT_SYMBOL(tegra_io_pad_get_voltage);
1130	1508
1131	1509	/**
1132	1510	* tegra_io_rail_power_on() - enable power to I/O rail
..	..	@@ -1169,6 +1547,7 @@
1169	1547	void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1170	1548	{
1171	1549	unsigned long long rate = 0;
	1550	+ u64 ticks;
1172	1551	u32 value;
1173	1552
1174	1553	switch (mode) {
..	..	@@ -1177,7 +1556,7 @@
1177	1556	break;
1178	1557
1179	1558	case TEGRA_SUSPEND_LP2:
1180		- rate = clk_get_rate(pmc->clk);
	1559	+ rate = pmc->rate;
1181	1560	break;
1182	1561
1183	1562	default:
..	..	@@ -1187,26 +1566,18 @@
1187	1566	if (WARN_ON_ONCE(rate == 0))
1188	1567	rate = 100000000;
1189	1568
1190		- if (rate != pmc->rate) {
1191		- u64 ticks;
	1569	+ ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
	1570	+ do_div(ticks, USEC_PER_SEC);
	1571	+ tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1192	1572
1193		- ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1194		- do_div(ticks, USEC_PER_SEC);
1195		- tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER);
	1573	+ ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
	1574	+ do_div(ticks, USEC_PER_SEC);
	1575	+ tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1196	1576
1197		- ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1198		- do_div(ticks, USEC_PER_SEC);
1199		- tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER);
1200		-
1201		- wmb();
1202		-
1203		- pmc->rate = rate;
1204		- }
1205		-
1206		- value = tegra_pmc_readl(PMC_CNTRL);
	1577	+ value = tegra_pmc_readl(pmc, PMC_CNTRL);
1207	1578	value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1208	1579	value \|= PMC_CNTRL_CPU_PWRREQ_OE;
1209		- tegra_pmc_writel(value, PMC_CNTRL);
	1580	+ tegra_pmc_writel(pmc, value, PMC_CNTRL);
1210	1581	}
1211	1582	#endif
1212	1583
..	..	@@ -1328,13 +1699,13 @@
1328	1699	if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1329	1700	pinmux = 0;
1330	1701
1331		- value = tegra_pmc_readl(PMC_SENSOR_CTRL);
	1702	+ value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1332	1703	value \|= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1333		- tegra_pmc_writel(value, PMC_SENSOR_CTRL);
	1704	+ tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1334	1705
1335	1706	value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) \|
1336	1707	(reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1337		- tegra_pmc_writel(value, PMC_SCRATCH54);
	1708	+ tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1338	1709
1339	1710	value = PMC_SCRATCH55_RESET_TEGRA;
1340	1711	value \|= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
..	..	@@ -1352,16 +1723,779 @@
1352	1723
1353	1724	value \|= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1354	1725
1355		- tegra_pmc_writel(value, PMC_SCRATCH55);
	1726	+ tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1356	1727
1357		- value = tegra_pmc_readl(PMC_SENSOR_CTRL);
	1728	+ value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1358	1729	value \|= PMC_SENSOR_CTRL_ENABLE_RST;
1359		- tegra_pmc_writel(value, PMC_SENSOR_CTRL);
	1730	+ tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1360	1731
1361	1732	dev_info(pmc->dev, "emergency thermal reset enabled\n");
1362	1733
1363	1734	out:
1364	1735	of_node_put(np);
	1736	+}
	1737	+
	1738	+static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
	1739	+{
	1740	+ struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
	1741	+
	1742	+ return pmc->soc->num_io_pads;
	1743	+}
	1744	+
	1745	+static const char tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev pctl,
	1746	+ unsigned int group)
	1747	+{
	1748	+ struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
	1749	+
	1750	+ return pmc->soc->io_pads[group].name;
	1751	+}
	1752	+
	1753	+static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
	1754	+ unsigned int group,
	1755	+ const unsigned int **pins,
	1756	+ unsigned int *num_pins)
	1757	+{
	1758	+ struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
	1759	+
	1760	+ *pins = &pmc->soc->io_pads[group].id;
	1761	+ *num_pins = 1;
	1762	+
	1763	+ return 0;
	1764	+}
	1765	+
	1766	+static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
	1767	+ .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
	1768	+ .get_group_name = tegra_io_pad_pinctrl_get_group_name,
	1769	+ .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
	1770	+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
	1771	+ .dt_free_map = pinconf_generic_dt_free_map,
	1772	+};
	1773	+
	1774	+static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
	1775	+ unsigned int pin, unsigned long *config)
	1776	+{
	1777	+ enum pin_config_param param = pinconf_to_config_param(*config);
	1778	+ struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
	1779	+ const struct tegra_io_pad_soc *pad;
	1780	+ int ret;
	1781	+ u32 arg;
	1782	+
	1783	+ pad = tegra_io_pad_find(pmc, pin);
	1784	+ if (!pad)
	1785	+ return -EINVAL;
	1786	+
	1787	+ switch (param) {
	1788	+ case PIN_CONFIG_POWER_SOURCE:
	1789	+ ret = tegra_io_pad_get_voltage(pmc, pad->id);
	1790	+ if (ret < 0)
	1791	+ return ret;
	1792	+
	1793	+ arg = ret;
	1794	+ break;
	1795	+
	1796	+ case PIN_CONFIG_LOW_POWER_MODE:
	1797	+ ret = tegra_io_pad_is_powered(pmc, pad->id);
	1798	+ if (ret < 0)
	1799	+ return ret;
	1800	+
	1801	+ arg = !ret;
	1802	+ break;
	1803	+
	1804	+ default:
	1805	+ return -EINVAL;
	1806	+ }
	1807	+
	1808	+ *config = pinconf_to_config_packed(param, arg);
	1809	+
	1810	+ return 0;
	1811	+}
	1812	+
	1813	+static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
	1814	+ unsigned int pin, unsigned long *configs,
	1815	+ unsigned int num_configs)
	1816	+{
	1817	+ struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
	1818	+ const struct tegra_io_pad_soc *pad;
	1819	+ enum pin_config_param param;
	1820	+ unsigned int i;
	1821	+ int err;
	1822	+ u32 arg;
	1823	+
	1824	+ pad = tegra_io_pad_find(pmc, pin);
	1825	+ if (!pad)
	1826	+ return -EINVAL;
	1827	+
	1828	+ for (i = 0; i < num_configs; ++i) {
	1829	+ param = pinconf_to_config_param(configs[i]);
	1830	+ arg = pinconf_to_config_argument(configs[i]);
	1831	+
	1832	+ switch (param) {
	1833	+ case PIN_CONFIG_LOW_POWER_MODE:
	1834	+ if (arg)
	1835	+ err = tegra_io_pad_power_disable(pad->id);
	1836	+ else
	1837	+ err = tegra_io_pad_power_enable(pad->id);
	1838	+ if (err)
	1839	+ return err;
	1840	+ break;
	1841	+ case PIN_CONFIG_POWER_SOURCE:
	1842	+ if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
	1843	+ arg != TEGRA_IO_PAD_VOLTAGE_3V3)
	1844	+ return -EINVAL;
	1845	+ err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
	1846	+ if (err)
	1847	+ return err;
	1848	+ break;
	1849	+ default:
	1850	+ return -EINVAL;
	1851	+ }
	1852	+ }
	1853	+
	1854	+ return 0;
	1855	+}
	1856	+
	1857	+static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
	1858	+ .pin_config_get = tegra_io_pad_pinconf_get,
	1859	+ .pin_config_set = tegra_io_pad_pinconf_set,
	1860	+ .is_generic = true,
	1861	+};
	1862	+
	1863	+static struct pinctrl_desc tegra_pmc_pctl_desc = {
	1864	+ .pctlops = &tegra_io_pad_pinctrl_ops,
	1865	+ .confops = &tegra_io_pad_pinconf_ops,
	1866	+};
	1867	+
	1868	+static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
	1869	+{
	1870	+ int err;
	1871	+
	1872	+ if (!pmc->soc->num_pin_descs)
	1873	+ return 0;
	1874	+
	1875	+ tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
	1876	+ tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
	1877	+ tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
	1878	+
	1879	+ pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
	1880	+ pmc);
	1881	+ if (IS_ERR(pmc->pctl_dev)) {
	1882	+ err = PTR_ERR(pmc->pctl_dev);
	1883	+ dev_err(pmc->dev, "failed to register pin controller: %d\n",
	1884	+ err);
	1885	+ return err;
	1886	+ }
	1887	+
	1888	+ return 0;
	1889	+}
	1890	+
	1891	+static ssize_t reset_reason_show(struct device *dev,
	1892	+ struct device_attribute attr, char buf)
	1893	+{
	1894	+ u32 value;
	1895	+
	1896	+ value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
	1897	+ value &= pmc->soc->regs->rst_source_mask;
	1898	+ value >>= pmc->soc->regs->rst_source_shift;
	1899	+
	1900	+ if (WARN_ON(value >= pmc->soc->num_reset_sources))
	1901	+ return sprintf(buf, "%s\n", "UNKNOWN");
	1902	+
	1903	+ return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
	1904	+}
	1905	+
	1906	+static DEVICE_ATTR_RO(reset_reason);
	1907	+
	1908	+static ssize_t reset_level_show(struct device *dev,
	1909	+ struct device_attribute attr, char buf)
	1910	+{
	1911	+ u32 value;
	1912	+
	1913	+ value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
	1914	+ value &= pmc->soc->regs->rst_level_mask;
	1915	+ value >>= pmc->soc->regs->rst_level_shift;
	1916	+
	1917	+ if (WARN_ON(value >= pmc->soc->num_reset_levels))
	1918	+ return sprintf(buf, "%s\n", "UNKNOWN");
	1919	+
	1920	+ return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
	1921	+}
	1922	+
	1923	+static DEVICE_ATTR_RO(reset_level);
	1924	+
	1925	+static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
	1926	+{
	1927	+ struct device *dev = pmc->dev;
	1928	+ int err = 0;
	1929	+
	1930	+ if (pmc->soc->reset_sources) {
	1931	+ err = device_create_file(dev, &dev_attr_reset_reason);
	1932	+ if (err < 0)
	1933	+ dev_warn(dev,
	1934	+ "failed to create attr \"reset_reason\": %d\n",
	1935	+ err);
	1936	+ }
	1937	+
	1938	+ if (pmc->soc->reset_levels) {
	1939	+ err = device_create_file(dev, &dev_attr_reset_level);
	1940	+ if (err < 0)
	1941	+ dev_warn(dev,
	1942	+ "failed to create attr \"reset_level\": %d\n",
	1943	+ err);
	1944	+ }
	1945	+}
	1946	+
	1947	+static int tegra_pmc_irq_translate(struct irq_domain *domain,
	1948	+ struct irq_fwspec *fwspec,
	1949	+ unsigned long *hwirq,
	1950	+ unsigned int *type)
	1951	+{
	1952	+ if (WARN_ON(fwspec->param_count < 2))
	1953	+ return -EINVAL;
	1954	+
	1955	+ *hwirq = fwspec->param[0];
	1956	+ *type = fwspec->param[1];
	1957	+
	1958	+ return 0;
	1959	+}
	1960	+
	1961	+static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
	1962	+ unsigned int num_irqs, void *data)
	1963	+{
	1964	+ struct tegra_pmc *pmc = domain->host_data;
	1965	+ const struct tegra_pmc_soc *soc = pmc->soc;
	1966	+ struct irq_fwspec *fwspec = data;
	1967	+ unsigned int i;
	1968	+ int err = 0;
	1969	+
	1970	+ if (WARN_ON(num_irqs > 1))
	1971	+ return -EINVAL;
	1972	+
	1973	+ for (i = 0; i < soc->num_wake_events; i++) {
	1974	+ const struct tegra_wake_event *event = &soc->wake_events[i];
	1975	+
	1976	+ if (fwspec->param_count == 2) {
	1977	+ struct irq_fwspec spec;
	1978	+
	1979	+ if (event->id != fwspec->param[0])
	1980	+ continue;
	1981	+
	1982	+ err = irq_domain_set_hwirq_and_chip(domain, virq,
	1983	+ event->id,
	1984	+ &pmc->irq, pmc);
	1985	+ if (err < 0)
	1986	+ break;
	1987	+
	1988	+ spec.fwnode = &pmc->dev->of_node->fwnode;
	1989	+ spec.param_count = 3;
	1990	+ spec.param[0] = GIC_SPI;
	1991	+ spec.param[1] = event->irq;
	1992	+ spec.param[2] = fwspec->param[1];
	1993	+
	1994	+ err = irq_domain_alloc_irqs_parent(domain, virq,
	1995	+ num_irqs, &spec);
	1996	+
	1997	+ break;
	1998	+ }
	1999	+
	2000	+ if (fwspec->param_count == 3) {
	2001	+ if (event->gpio.instance != fwspec->param[0] \|\|
	2002	+ event->gpio.pin != fwspec->param[1])
	2003	+ continue;
	2004	+
	2005	+ err = irq_domain_set_hwirq_and_chip(domain, virq,
	2006	+ event->id,
	2007	+ &pmc->irq, pmc);
	2008	+
	2009	+ /* GPIO hierarchies stop at the PMC level */
	2010	+ if (!err && domain->parent)
	2011	+ err = irq_domain_disconnect_hierarchy(domain->parent,
	2012	+ virq);
	2013	+ break;
	2014	+ }
	2015	+ }
	2016	+
	2017	+ /* If there is no wake-up event, there is no PMC mapping */
	2018	+ if (i == soc->num_wake_events)
	2019	+ err = irq_domain_disconnect_hierarchy(domain, virq);
	2020	+
	2021	+ return err;
	2022	+}
	2023	+
	2024	+static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
	2025	+ .translate = tegra_pmc_irq_translate,
	2026	+ .alloc = tegra_pmc_irq_alloc,
	2027	+};
	2028	+
	2029	+static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
	2030	+{
	2031	+ struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
	2032	+ unsigned int offset, bit;
	2033	+ u32 value;
	2034	+
	2035	+ offset = data->hwirq / 32;
	2036	+ bit = data->hwirq % 32;
	2037	+
	2038	+ /* clear wake status */
	2039	+ tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
	2040	+ tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
	2041	+
	2042	+ tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
	2043	+ tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
	2044	+
	2045	+ /* enable PMC wake */
	2046	+ if (data->hwirq >= 32)
	2047	+ offset = PMC_WAKE2_MASK;
	2048	+ else
	2049	+ offset = PMC_WAKE_MASK;
	2050	+
	2051	+ value = tegra_pmc_readl(pmc, offset);
	2052	+
	2053	+ if (on)
	2054	+ value \|= BIT(bit);
	2055	+ else
	2056	+ value &= ~BIT(bit);
	2057	+
	2058	+ tegra_pmc_writel(pmc, value, offset);
	2059	+
	2060	+ return 0;
	2061	+}
	2062	+
	2063	+static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
	2064	+{
	2065	+ struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
	2066	+ unsigned int offset, bit;
	2067	+ u32 value;
	2068	+
	2069	+ offset = data->hwirq / 32;
	2070	+ bit = data->hwirq % 32;
	2071	+
	2072	+ if (data->hwirq >= 32)
	2073	+ offset = PMC_WAKE2_LEVEL;
	2074	+ else
	2075	+ offset = PMC_WAKE_LEVEL;
	2076	+
	2077	+ value = tegra_pmc_readl(pmc, offset);
	2078	+
	2079	+ switch (type) {
	2080	+ case IRQ_TYPE_EDGE_RISING:
	2081	+ case IRQ_TYPE_LEVEL_HIGH:
	2082	+ value \|= BIT(bit);
	2083	+ break;
	2084	+
	2085	+ case IRQ_TYPE_EDGE_FALLING:
	2086	+ case IRQ_TYPE_LEVEL_LOW:
	2087	+ value &= ~BIT(bit);
	2088	+ break;
	2089	+
	2090	+ case IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING:
	2091	+ value ^= BIT(bit);
	2092	+ break;
	2093	+
	2094	+ default:
	2095	+ return -EINVAL;
	2096	+ }
	2097	+
	2098	+ tegra_pmc_writel(pmc, value, offset);
	2099	+
	2100	+ return 0;
	2101	+}
	2102	+
	2103	+static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
	2104	+{
	2105	+ struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
	2106	+ unsigned int offset, bit;
	2107	+ u32 value;
	2108	+
	2109	+ offset = data->hwirq / 32;
	2110	+ bit = data->hwirq % 32;
	2111	+
	2112	+ /* clear wake status */
	2113	+ writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
	2114	+
	2115	+ /* route wake to tier 2 */
	2116	+ value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
	2117	+
	2118	+ if (!on)
	2119	+ value &= ~(1 << bit);
	2120	+ else
	2121	+ value \|= 1 << bit;
	2122	+
	2123	+ writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
	2124	+
	2125	+ /* enable wakeup event */
	2126	+ writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
	2127	+
	2128	+ return 0;
	2129	+}
	2130	+
	2131	+static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
	2132	+{
	2133	+ struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
	2134	+ u32 value;
	2135	+
	2136	+ value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
	2137	+
	2138	+ switch (type) {
	2139	+ case IRQ_TYPE_EDGE_RISING:
	2140	+ case IRQ_TYPE_LEVEL_HIGH:
	2141	+ value \|= WAKE_AOWAKE_CNTRL_LEVEL;
	2142	+ break;
	2143	+
	2144	+ case IRQ_TYPE_EDGE_FALLING:
	2145	+ case IRQ_TYPE_LEVEL_LOW:
	2146	+ value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
	2147	+ break;
	2148	+
	2149	+ case IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING:
	2150	+ value ^= WAKE_AOWAKE_CNTRL_LEVEL;
	2151	+ break;
	2152	+
	2153	+ default:
	2154	+ return -EINVAL;
	2155	+ }
	2156	+
	2157	+ writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
	2158	+
	2159	+ return 0;
	2160	+}
	2161	+
	2162	+static void tegra_irq_mask_parent(struct irq_data *data)
	2163	+{
	2164	+ if (data->parent_data)
	2165	+ irq_chip_mask_parent(data);
	2166	+}
	2167	+
	2168	+static void tegra_irq_unmask_parent(struct irq_data *data)
	2169	+{
	2170	+ if (data->parent_data)
	2171	+ irq_chip_unmask_parent(data);
	2172	+}
	2173	+
	2174	+static void tegra_irq_eoi_parent(struct irq_data *data)
	2175	+{
	2176	+ if (data->parent_data)
	2177	+ irq_chip_eoi_parent(data);
	2178	+}
	2179	+
	2180	+static int tegra_irq_set_affinity_parent(struct irq_data *data,
	2181	+ const struct cpumask *dest,
	2182	+ bool force)
	2183	+{
	2184	+ if (data->parent_data)
	2185	+ return irq_chip_set_affinity_parent(data, dest, force);
	2186	+
	2187	+ return -EINVAL;
	2188	+}
	2189	+
	2190	+static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
	2191	+{
	2192	+ struct irq_domain *parent = NULL;
	2193	+ struct device_node *np;
	2194	+
	2195	+ np = of_irq_find_parent(pmc->dev->of_node);
	2196	+ if (np) {
	2197	+ parent = irq_find_host(np);
	2198	+ of_node_put(np);
	2199	+ }
	2200	+
	2201	+ if (!parent)
	2202	+ return 0;
	2203	+
	2204	+ pmc->irq.name = dev_name(pmc->dev);
	2205	+ pmc->irq.irq_mask = tegra_irq_mask_parent;
	2206	+ pmc->irq.irq_unmask = tegra_irq_unmask_parent;
	2207	+ pmc->irq.irq_eoi = tegra_irq_eoi_parent;
	2208	+ pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
	2209	+ pmc->irq.irq_set_type = pmc->soc->irq_set_type;
	2210	+ pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
	2211	+
	2212	+ pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
	2213	+ &tegra_pmc_irq_domain_ops, pmc);
	2214	+ if (!pmc->domain) {
	2215	+ dev_err(pmc->dev, "failed to allocate domain\n");
	2216	+ return -ENOMEM;
	2217	+ }
	2218	+
	2219	+ return 0;
	2220	+}
	2221	+
	2222	+static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
	2223	+ unsigned long action, void *ptr)
	2224	+{
	2225	+ struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
	2226	+ struct clk_notifier_data *data = ptr;
	2227	+
	2228	+ switch (action) {
	2229	+ case PRE_RATE_CHANGE:
	2230	+ mutex_lock(&pmc->powergates_lock);
	2231	+ break;
	2232	+
	2233	+ case POST_RATE_CHANGE:
	2234	+ pmc->rate = data->new_rate;
	2235	+ fallthrough;
	2236	+
	2237	+ case ABORT_RATE_CHANGE:
	2238	+ mutex_unlock(&pmc->powergates_lock);
	2239	+ break;
	2240	+
	2241	+ default:
	2242	+ WARN_ON_ONCE(1);
	2243	+ return notifier_from_errno(-EINVAL);
	2244	+ }
	2245	+
	2246	+ return NOTIFY_OK;
	2247	+}
	2248	+
	2249	+static void pmc_clk_fence_udelay(u32 offset)
	2250	+{
	2251	+ tegra_pmc_readl(pmc, offset);
	2252	+ /* pmc clk propagation delay 2 us */
	2253	+ udelay(2);
	2254	+}
	2255	+
	2256	+static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
	2257	+{
	2258	+ struct pmc_clk *clk = to_pmc_clk(hw);
	2259	+ u32 val;
	2260	+
	2261	+ val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
	2262	+ val &= PMC_CLK_OUT_MUX_MASK;
	2263	+
	2264	+ return val;
	2265	+}
	2266	+
	2267	+static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
	2268	+{
	2269	+ struct pmc_clk *clk = to_pmc_clk(hw);
	2270	+ u32 val;
	2271	+
	2272	+ val = tegra_pmc_readl(pmc, clk->offs);
	2273	+ val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
	2274	+ val \|= index << clk->mux_shift;
	2275	+ tegra_pmc_writel(pmc, val, clk->offs);
	2276	+ pmc_clk_fence_udelay(clk->offs);
	2277	+
	2278	+ return 0;
	2279	+}
	2280	+
	2281	+static int pmc_clk_is_enabled(struct clk_hw *hw)
	2282	+{
	2283	+ struct pmc_clk *clk = to_pmc_clk(hw);
	2284	+ u32 val;
	2285	+
	2286	+ val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
	2287	+
	2288	+ return val ? 1 : 0;
	2289	+}
	2290	+
	2291	+static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
	2292	+{
	2293	+ u32 val;
	2294	+
	2295	+ val = tegra_pmc_readl(pmc, offs);
	2296	+ val = state ? (val \| BIT(shift)) : (val & ~BIT(shift));
	2297	+ tegra_pmc_writel(pmc, val, offs);
	2298	+ pmc_clk_fence_udelay(offs);
	2299	+}
	2300	+
	2301	+static int pmc_clk_enable(struct clk_hw *hw)
	2302	+{
	2303	+ struct pmc_clk *clk = to_pmc_clk(hw);
	2304	+
	2305	+ pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
	2306	+
	2307	+ return 0;
	2308	+}
	2309	+
	2310	+static void pmc_clk_disable(struct clk_hw *hw)
	2311	+{
	2312	+ struct pmc_clk *clk = to_pmc_clk(hw);
	2313	+
	2314	+ pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
	2315	+}
	2316	+
	2317	+static const struct clk_ops pmc_clk_ops = {
	2318	+ .get_parent = pmc_clk_mux_get_parent,
	2319	+ .set_parent = pmc_clk_mux_set_parent,
	2320	+ .determine_rate = __clk_mux_determine_rate,
	2321	+ .is_enabled = pmc_clk_is_enabled,
	2322	+ .enable = pmc_clk_enable,
	2323	+ .disable = pmc_clk_disable,
	2324	+};
	2325	+
	2326	+static struct clk *
	2327	+tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
	2328	+ const struct pmc_clk_init_data *data,
	2329	+ unsigned long offset)
	2330	+{
	2331	+ struct clk_init_data init;
	2332	+ struct pmc_clk *pmc_clk;
	2333	+
	2334	+ pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
	2335	+ if (!pmc_clk)
	2336	+ return ERR_PTR(-ENOMEM);
	2337	+
	2338	+ init.name = data->name;
	2339	+ init.ops = &pmc_clk_ops;
	2340	+ init.parent_names = data->parents;
	2341	+ init.num_parents = data->num_parents;
	2342	+ init.flags = CLK_SET_RATE_NO_REPARENT \| CLK_SET_RATE_PARENT \|
	2343	+ CLK_SET_PARENT_GATE;
	2344	+
	2345	+ pmc_clk->hw.init = &init;
	2346	+ pmc_clk->offs = offset;
	2347	+ pmc_clk->mux_shift = data->mux_shift;
	2348	+ pmc_clk->force_en_shift = data->force_en_shift;
	2349	+
	2350	+ return clk_register(NULL, &pmc_clk->hw);
	2351	+}
	2352	+
	2353	+static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
	2354	+{
	2355	+ struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
	2356	+
	2357	+ return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
	2358	+}
	2359	+
	2360	+static int pmc_clk_gate_enable(struct clk_hw *hw)
	2361	+{
	2362	+ struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
	2363	+
	2364	+ pmc_clk_set_state(gate->offs, gate->shift, 1);
	2365	+
	2366	+ return 0;
	2367	+}
	2368	+
	2369	+static void pmc_clk_gate_disable(struct clk_hw *hw)
	2370	+{
	2371	+ struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
	2372	+
	2373	+ pmc_clk_set_state(gate->offs, gate->shift, 0);
	2374	+}
	2375	+
	2376	+static const struct clk_ops pmc_clk_gate_ops = {
	2377	+ .is_enabled = pmc_clk_gate_is_enabled,
	2378	+ .enable = pmc_clk_gate_enable,
	2379	+ .disable = pmc_clk_gate_disable,
	2380	+};
	2381	+
	2382	+static struct clk *
	2383	+tegra_pmc_clk_gate_register(struct tegra_pmc pmc, const char name,
	2384	+ const char *parent_name, unsigned long offset,
	2385	+ u32 shift)
	2386	+{
	2387	+ struct clk_init_data init;
	2388	+ struct pmc_clk_gate *gate;
	2389	+
	2390	+ gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
	2391	+ if (!gate)
	2392	+ return ERR_PTR(-ENOMEM);
	2393	+
	2394	+ init.name = name;
	2395	+ init.ops = &pmc_clk_gate_ops;
	2396	+ init.parent_names = &parent_name;
	2397	+ init.num_parents = 1;
	2398	+ init.flags = 0;
	2399	+
	2400	+ gate->hw.init = &init;
	2401	+ gate->offs = offset;
	2402	+ gate->shift = shift;
	2403	+
	2404	+ return clk_register(NULL, &gate->hw);
	2405	+}
	2406	+
	2407	+static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
	2408	+ struct device_node *np)
	2409	+{
	2410	+ struct clk *clk;
	2411	+ struct clk_onecell_data *clk_data;
	2412	+ unsigned int num_clks;
	2413	+ int i, err;
	2414	+
	2415	+ num_clks = pmc->soc->num_pmc_clks;
	2416	+ if (pmc->soc->has_blink_output)
	2417	+ num_clks += 1;
	2418	+
	2419	+ if (!num_clks)
	2420	+ return;
	2421	+
	2422	+ clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
	2423	+ if (!clk_data)
	2424	+ return;
	2425	+
	2426	+ clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
	2427	+ sizeof(*clk_data->clks), GFP_KERNEL);
	2428	+ if (!clk_data->clks)
	2429	+ return;
	2430	+
	2431	+ clk_data->clk_num = TEGRA_PMC_CLK_MAX;
	2432	+
	2433	+ for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
	2434	+ clk_data->clks[i] = ERR_PTR(-ENOENT);
	2435	+
	2436	+ for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
	2437	+ const struct pmc_clk_init_data *data;
	2438	+
	2439	+ data = pmc->soc->pmc_clks_data + i;
	2440	+
	2441	+ clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
	2442	+ if (IS_ERR(clk)) {
	2443	+ dev_warn(pmc->dev, "unable to register clock %s: %d\n",
	2444	+ data->name, PTR_ERR_OR_ZERO(clk));
	2445	+ return;
	2446	+ }
	2447	+
	2448	+ err = clk_register_clkdev(clk, data->name, NULL);
	2449	+ if (err) {
	2450	+ dev_warn(pmc->dev,
	2451	+ "unable to register %s clock lookup: %d\n",
	2452	+ data->name, err);
	2453	+ return;
	2454	+ }
	2455	+
	2456	+ clk_data->clks[data->clk_id] = clk;
	2457	+ }
	2458	+
	2459	+ if (pmc->soc->has_blink_output) {
	2460	+ tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
	2461	+ clk = tegra_pmc_clk_gate_register(pmc,
	2462	+ "pmc_blink_override",
	2463	+ "clk_32k",
	2464	+ PMC_DPD_PADS_ORIDE,
	2465	+ PMC_DPD_PADS_ORIDE_BLINK);
	2466	+ if (IS_ERR(clk)) {
	2467	+ dev_warn(pmc->dev,
	2468	+ "unable to register pmc_blink_override: %d\n",
	2469	+ PTR_ERR_OR_ZERO(clk));
	2470	+ return;
	2471	+ }
	2472	+
	2473	+ clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
	2474	+ "pmc_blink_override",
	2475	+ PMC_CNTRL,
	2476	+ PMC_CNTRL_BLINK_EN);
	2477	+ if (IS_ERR(clk)) {
	2478	+ dev_warn(pmc->dev,
	2479	+ "unable to register pmc_blink: %d\n",
	2480	+ PTR_ERR_OR_ZERO(clk));
	2481	+ return;
	2482	+ }
	2483	+
	2484	+ err = clk_register_clkdev(clk, "pmc_blink", NULL);
	2485	+ if (err) {
	2486	+ dev_warn(pmc->dev,
	2487	+ "unable to register pmc_blink lookup: %d\n",
	2488	+ err);
	2489	+ return;
	2490	+ }
	2491	+
	2492	+ clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
	2493	+ }
	2494	+
	2495	+ err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
	2496	+ if (err)
	2497	+ dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
	2498	+ err);
1365	2499	}
1366	2500
1367	2501	static int tegra_pmc_probe(struct platform_device *pdev)
..	..	@@ -1427,45 +2561,95 @@
1427	2561	pmc->clk = NULL;
1428	2562	}
1429	2563
	2564	+ /*
	2565	+ * PCLK clock rate can't be retrieved using CLK API because it
	2566	+ * causes lockup if CPU enters LP2 idle state from some other
	2567	+ * CLK notifier, hence we're caching the rate's value locally.
	2568	+ */
	2569	+ if (pmc->clk) {
	2570	+ pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
	2571	+ err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
	2572	+ if (err) {
	2573	+ dev_err(&pdev->dev,
	2574	+ "failed to register clk notifier\n");
	2575	+ return err;
	2576	+ }
	2577	+
	2578	+ pmc->rate = clk_get_rate(pmc->clk);
	2579	+ }
	2580	+
1430	2581	pmc->dev = &pdev->dev;
1431	2582
1432	2583	tegra_pmc_init(pmc);
1433	2584
1434	2585	tegra_pmc_init_tsense_reset(pmc);
1435	2586
	2587	+ tegra_pmc_reset_sysfs_init(pmc);
	2588	+
1436	2589	if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1437	2590	err = tegra_powergate_debugfs_init();
1438	2591	if (err < 0)
1439		- return err;
	2592	+ goto cleanup_sysfs;
1440	2593	}
1441	2594
1442	2595	err = register_restart_handler(&tegra_pmc_restart_handler);
1443	2596	if (err) {
1444		- debugfs_remove(pmc->debugfs);
1445	2597	dev_err(&pdev->dev, "unable to register restart handler, %d\n",
1446	2598	err);
1447		- return err;
	2599	+ goto cleanup_debugfs;
1448	2600	}
	2601	+
	2602	+ err = tegra_pmc_pinctrl_init(pmc);
	2603	+ if (err)
	2604	+ goto cleanup_restart_handler;
	2605	+
	2606	+ err = tegra_powergate_init(pmc, pdev->dev.of_node);
	2607	+ if (err < 0)
	2608	+ goto cleanup_powergates;
	2609	+
	2610	+ err = tegra_pmc_irq_init(pmc);
	2611	+ if (err < 0)
	2612	+ goto cleanup_powergates;
1449	2613
1450	2614	mutex_lock(&pmc->powergates_lock);
1451	2615	iounmap(pmc->base);
1452	2616	pmc->base = base;
1453	2617	mutex_unlock(&pmc->powergates_lock);
1454	2618
	2619	+ tegra_pmc_clock_register(pmc, pdev->dev.of_node);
	2620	+ platform_set_drvdata(pdev, pmc);
	2621	+
1455	2622	return 0;
	2623	+
	2624	+cleanup_powergates:
	2625	+ tegra_powergate_remove_all(pdev->dev.of_node);
	2626	+cleanup_restart_handler:
	2627	+ unregister_restart_handler(&tegra_pmc_restart_handler);
	2628	+cleanup_debugfs:
	2629	+ debugfs_remove(pmc->debugfs);
	2630	+cleanup_sysfs:
	2631	+ device_remove_file(&pdev->dev, &dev_attr_reset_reason);
	2632	+ device_remove_file(&pdev->dev, &dev_attr_reset_level);
	2633	+ clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
	2634	+
	2635	+ return err;
1456	2636	}
1457	2637
1458	2638	#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
1459	2639	static int tegra_pmc_suspend(struct device *dev)
1460	2640	{
1461		- tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
	2641	+ struct tegra_pmc *pmc = dev_get_drvdata(dev);
	2642	+
	2643	+ tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
1462	2644
1463	2645	return 0;
1464	2646	}
1465	2647
1466	2648	static int tegra_pmc_resume(struct device *dev)
1467	2649	{
1468		- tegra_pmc_writel(0x0, PMC_SCRATCH41);
	2650	+ struct tegra_pmc *pmc = dev_get_drvdata(dev);
	2651	+
	2652	+ tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
1469	2653
1470	2654	return 0;
1471	2655	}
..	..	@@ -1490,31 +2674,51 @@
1490	2674	.dpd_status = 0x1bc,
1491	2675	.dpd2_req = 0x1c0,
1492	2676	.dpd2_status = 0x1c4,
	2677	+ .rst_status = 0x1b4,
	2678	+ .rst_source_shift = 0x0,
	2679	+ .rst_source_mask = 0x7,
	2680	+ .rst_level_shift = 0x0,
	2681	+ .rst_level_mask = 0x0,
1493	2682	};
1494	2683
1495	2684	static void tegra20_pmc_init(struct tegra_pmc *pmc)
1496	2685	{
1497		- u32 value;
	2686	+ u32 value, osc, pmu, off;
1498	2687
1499	2688	/* Always enable CPU power request */
1500		- value = tegra_pmc_readl(PMC_CNTRL);
	2689	+ value = tegra_pmc_readl(pmc, PMC_CNTRL);
1501	2690	value \|= PMC_CNTRL_CPU_PWRREQ_OE;
1502		- tegra_pmc_writel(value, PMC_CNTRL);
	2691	+ tegra_pmc_writel(pmc, value, PMC_CNTRL);
1503	2692
1504		- value = tegra_pmc_readl(PMC_CNTRL);
	2693	+ value = tegra_pmc_readl(pmc, PMC_CNTRL);
1505	2694
1506	2695	if (pmc->sysclkreq_high)
1507	2696	value &= ~PMC_CNTRL_SYSCLK_POLARITY;
1508	2697	else
1509	2698	value \|= PMC_CNTRL_SYSCLK_POLARITY;
1510	2699
	2700	+ if (pmc->corereq_high)
	2701	+ value &= ~PMC_CNTRL_PWRREQ_POLARITY;
	2702	+ else
	2703	+ value \|= PMC_CNTRL_PWRREQ_POLARITY;
	2704	+
1511	2705	/* configure the output polarity while the request is tristated */
1512		- tegra_pmc_writel(value, PMC_CNTRL);
	2706	+ tegra_pmc_writel(pmc, value, PMC_CNTRL);
1513	2707
1514	2708	/* now enable the request */
1515		- value = tegra_pmc_readl(PMC_CNTRL);
	2709	+ value = tegra_pmc_readl(pmc, PMC_CNTRL);
1516	2710	value \|= PMC_CNTRL_SYSCLK_OE;
1517		- tegra_pmc_writel(value, PMC_CNTRL);
	2711	+ tegra_pmc_writel(pmc, value, PMC_CNTRL);
	2712	+
	2713	+ /* program core timings which are applicable only for suspend state */
	2714	+ if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
	2715	+ osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
	2716	+ pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
	2717	+ off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
	2718	+ tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) \| (pmu & 0xff),
	2719	+ PMC_COREPWRGOOD_TIMER);
	2720	+ tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
	2721	+ }
1518	2722	}
1519	2723
1520	2724	static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
..	..	@@ -1523,14 +2727,14 @@
1523	2727	{
1524	2728	u32 value;
1525	2729
1526		- value = tegra_pmc_readl(PMC_CNTRL);
	2730	+ value = tegra_pmc_readl(pmc, PMC_CNTRL);
1527	2731
1528	2732	if (invert)
1529	2733	value \|= PMC_CNTRL_INTR_POLARITY;
1530	2734	else
1531	2735	value &= ~PMC_CNTRL_INTR_POLARITY;
1532	2736
1533		- tegra_pmc_writel(value, PMC_CNTRL);
	2737	+ tegra_pmc_writel(pmc, value, PMC_CNTRL);
1534	2738	}
1535	2739
1536	2740	static const struct tegra_pmc_soc tegra20_pmc_soc = {
..	..	@@ -1540,11 +2744,24 @@
1540	2744	.cpu_powergates = NULL,
1541	2745	.has_tsense_reset = false,
1542	2746	.has_gpu_clamps = false,
	2747	+ .needs_mbist_war = false,
	2748	+ .has_impl_33v_pwr = false,
	2749	+ .maybe_tz_only = false,
1543	2750	.num_io_pads = 0,
1544	2751	.io_pads = NULL,
	2752	+ .num_pin_descs = 0,
	2753	+ .pin_descs = NULL,
1545	2754	.regs = &tegra20_pmc_regs,
1546	2755	.init = tegra20_pmc_init,
1547	2756	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
	2757	+ .powergate_set = tegra20_powergate_set,
	2758	+ .reset_sources = NULL,
	2759	+ .num_reset_sources = 0,
	2760	+ .reset_levels = NULL,
	2761	+ .num_reset_levels = 0,
	2762	+ .pmc_clks_data = NULL,
	2763	+ .num_pmc_clks = 0,
	2764	+ .has_blink_output = true,
1548	2765	};
1549	2766
1550	2767	static const char * const tegra30_powergates[] = {
..	..	@@ -1571,6 +2788,14 @@
1571	2788	TEGRA_POWERGATE_CPU3,
1572	2789	};
1573	2790
	2791	+static const char * const tegra30_reset_sources[] = {
	2792	+ "POWER_ON_RESET",
	2793	+ "WATCHDOG",
	2794	+ "SENSOR",
	2795	+ "SW_MAIN",
	2796	+ "LP0"
	2797	+};
	2798	+
1574	2799	static const struct tegra_pmc_soc tegra30_pmc_soc = {
1575	2800	.num_powergates = ARRAY_SIZE(tegra30_powergates),
1576	2801	.powergates = tegra30_powergates,
..	..	@@ -1578,12 +2803,24 @@
1578	2803	.cpu_powergates = tegra30_cpu_powergates,
1579	2804	.has_tsense_reset = true,
1580	2805	.has_gpu_clamps = false,
	2806	+ .needs_mbist_war = false,
1581	2807	.has_impl_33v_pwr = false,
	2808	+ .maybe_tz_only = false,
1582	2809	.num_io_pads = 0,
1583	2810	.io_pads = NULL,
	2811	+ .num_pin_descs = 0,
	2812	+ .pin_descs = NULL,
1584	2813	.regs = &tegra20_pmc_regs,
1585	2814	.init = tegra20_pmc_init,
1586	2815	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
	2816	+ .powergate_set = tegra20_powergate_set,
	2817	+ .reset_sources = tegra30_reset_sources,
	2818	+ .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
	2819	+ .reset_levels = NULL,
	2820	+ .num_reset_levels = 0,
	2821	+ .pmc_clks_data = tegra_pmc_clks_data,
	2822	+ .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
	2823	+ .has_blink_output = true,
1587	2824	};
1588	2825
1589	2826	static const char * const tegra114_powergates[] = {
..	..	@@ -1621,12 +2858,24 @@
1621	2858	.cpu_powergates = tegra114_cpu_powergates,
1622	2859	.has_tsense_reset = true,
1623	2860	.has_gpu_clamps = false,
	2861	+ .needs_mbist_war = false,
1624	2862	.has_impl_33v_pwr = false,
	2863	+ .maybe_tz_only = false,
1625	2864	.num_io_pads = 0,
1626	2865	.io_pads = NULL,
	2866	+ .num_pin_descs = 0,
	2867	+ .pin_descs = NULL,
1627	2868	.regs = &tegra20_pmc_regs,
1628	2869	.init = tegra20_pmc_init,
1629	2870	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
	2871	+ .powergate_set = tegra114_powergate_set,
	2872	+ .reset_sources = tegra30_reset_sources,
	2873	+ .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
	2874	+ .reset_levels = NULL,
	2875	+ .num_reset_levels = 0,
	2876	+ .pmc_clks_data = tegra_pmc_clks_data,
	2877	+ .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
	2878	+ .has_blink_output = true,
1630	2879	};
1631	2880
1632	2881	static const char * const tegra124_powergates[] = {
..	..	@@ -1662,37 +2911,59 @@
1662	2911	TEGRA_POWERGATE_CPU3,
1663	2912	};
1664	2913
	2914	+#define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \
	2915	+ ((struct tegra_io_pad_soc) { \
	2916	+ .id = (_id), \
	2917	+ .dpd = (_dpd), \
	2918	+ .voltage = (_voltage), \
	2919	+ .name = (_name), \
	2920	+ })
	2921	+
	2922	+#define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \
	2923	+ ((struct pinctrl_pin_desc) { \
	2924	+ .number = (_id), \
	2925	+ .name = (_name) \
	2926	+ })
	2927	+
	2928	+#define TEGRA124_IO_PAD_TABLE(_pad) \
	2929	+ /* .id .dpd .voltage .name */ \
	2930	+ _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
	2931	+ _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
	2932	+ _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
	2933	+ _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
	2934	+ _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
	2935	+ _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
	2936	+ _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
	2937	+ _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
	2938	+ _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
	2939	+ _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
	2940	+ _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
	2941	+ _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
	2942	+ _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
	2943	+ _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
	2944	+ _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
	2945	+ _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
	2946	+ _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
	2947	+ _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
	2948	+ _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
	2949	+ _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
	2950	+ _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
	2951	+ _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
	2952	+ _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
	2953	+ _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
	2954	+ _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
	2955	+ _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
	2956	+ _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
	2957	+ _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
	2958	+ _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
	2959	+ _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
	2960	+
1665	2961	static const struct tegra_io_pad_soc tegra124_io_pads[] = {
1666		- { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
1667		- { .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX },
1668		- { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX },
1669		- { .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX },
1670		- { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1671		- { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1672		- { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1673		- { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1674		- { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1675		- { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1676		- { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1677		- { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1678		- { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1679		- { .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX },
1680		- { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1681		- { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1682		- { .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX },
1683		- { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1684		- { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1685		- { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1686		- { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
1687		- { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX },
1688		- { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX },
1689		- { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX },
1690		- { .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX },
1691		- { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
1692		- { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1693		- { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1694		- { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1695		- { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
	2962	+ TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
	2963	+};
	2964	+
	2965	+static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
	2966	+ TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
1696	2967	};
1697	2968
1698	2969	static const struct tegra_pmc_soc tegra124_pmc_soc = {
..	..	@@ -1702,12 +2973,24 @@
1702	2973	.cpu_powergates = tegra124_cpu_powergates,
1703	2974	.has_tsense_reset = true,
1704	2975	.has_gpu_clamps = true,
	2976	+ .needs_mbist_war = false,
1705	2977	.has_impl_33v_pwr = false,
	2978	+ .maybe_tz_only = false,
1706	2979	.num_io_pads = ARRAY_SIZE(tegra124_io_pads),
1707	2980	.io_pads = tegra124_io_pads,
	2981	+ .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
	2982	+ .pin_descs = tegra124_pin_descs,
1708	2983	.regs = &tegra20_pmc_regs,
1709	2984	.init = tegra20_pmc_init,
1710	2985	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
	2986	+ .powergate_set = tegra114_powergate_set,
	2987	+ .reset_sources = tegra30_reset_sources,
	2988	+ .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
	2989	+ .reset_levels = NULL,
	2990	+ .num_reset_levels = 0,
	2991	+ .pmc_clks_data = tegra_pmc_clks_data,
	2992	+ .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
	2993	+ .has_blink_output = true,
1711	2994	};
1712	2995
1713	2996	static const char * const tegra210_powergates[] = {
..	..	@@ -1744,45 +3027,67 @@
1744	3027	TEGRA_POWERGATE_CPU3,
1745	3028	};
1746	3029
	3030	+#define TEGRA210_IO_PAD_TABLE(_pad) \
	3031	+ /* .id .dpd .voltage .name */ \
	3032	+ _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
	3033	+ _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
	3034	+ _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
	3035	+ _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
	3036	+ _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
	3037	+ _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
	3038	+ _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
	3039	+ _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
	3040	+ _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
	3041	+ _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
	3042	+ _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
	3043	+ _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
	3044	+ _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
	3045	+ _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
	3046	+ _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
	3047	+ _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
	3048	+ _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
	3049	+ _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
	3050	+ _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
	3051	+ _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
	3052	+ _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
	3053	+ _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
	3054	+ _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
	3055	+ _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
	3056	+ _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
	3057	+ _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
	3058	+ _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
	3059	+ _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
	3060	+ _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
	3061	+ _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
	3062	+ _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
	3063	+ _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
	3064	+ _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
	3065	+ _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
	3066	+ _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
	3067	+ _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
	3068	+ _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
	3069	+ _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
	3070	+
1747	3071	static const struct tegra_io_pad_soc tegra210_io_pads[] = {
1748		- { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 },
1749		- { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 },
1750		- { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 },
1751		- { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1752		- { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1753		- { .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX },
1754		- { .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX },
1755		- { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX },
1756		- { .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX },
1757		- { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 },
1758		- { .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX },
1759		- { .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 },
1760		- { .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX },
1761		- { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1762		- { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX },
1763		- { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX },
1764		- { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX },
1765		- { .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX },
1766		- { .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX },
1767		- { .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 },
1768		- { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX },
1769		- { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1770		- { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX },
1771		- { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1772		- { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX },
1773		- { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX },
1774		- { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1775		- { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 },
1776		- { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 },
1777		- { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 },
1778		- { .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 },
1779		- { .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 },
1780		- { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 },
1781		- { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1782		- { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1783		- { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1784		- { .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX },
1785		- { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
	3072	+ TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
	3073	+};
	3074	+
	3075	+static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
	3076	+ TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
	3077	+};
	3078	+
	3079	+static const char * const tegra210_reset_sources[] = {
	3080	+ "POWER_ON_RESET",
	3081	+ "WATCHDOG",
	3082	+ "SENSOR",
	3083	+ "SW_MAIN",
	3084	+ "LP0",
	3085	+ "AOTAG"
	3086	+};
	3087	+
	3088	+static const struct tegra_wake_event tegra210_wake_events[] = {
	3089	+ TEGRA_WAKE_IRQ("rtc", 16, 2),
	3090	+ TEGRA_WAKE_IRQ("pmu", 51, 86),
1786	3091	};
1787	3092
1788	3093	static const struct tegra_pmc_soc tegra210_pmc_soc = {
..	..	@@ -1792,54 +3097,77 @@
1792	3097	.cpu_powergates = tegra210_cpu_powergates,
1793	3098	.has_tsense_reset = true,
1794	3099	.has_gpu_clamps = true,
1795		- .has_impl_33v_pwr = false,
1796	3100	.needs_mbist_war = true,
	3101	+ .has_impl_33v_pwr = false,
	3102	+ .maybe_tz_only = true,
1797	3103	.num_io_pads = ARRAY_SIZE(tegra210_io_pads),
1798	3104	.io_pads = tegra210_io_pads,
	3105	+ .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
	3106	+ .pin_descs = tegra210_pin_descs,
1799	3107	.regs = &tegra20_pmc_regs,
1800	3108	.init = tegra20_pmc_init,
1801	3109	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
	3110	+ .powergate_set = tegra114_powergate_set,
	3111	+ .irq_set_wake = tegra210_pmc_irq_set_wake,
	3112	+ .irq_set_type = tegra210_pmc_irq_set_type,
	3113	+ .reset_sources = tegra210_reset_sources,
	3114	+ .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
	3115	+ .reset_levels = NULL,
	3116	+ .num_reset_levels = 0,
	3117	+ .num_wake_events = ARRAY_SIZE(tegra210_wake_events),
	3118	+ .wake_events = tegra210_wake_events,
	3119	+ .pmc_clks_data = tegra_pmc_clks_data,
	3120	+ .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
	3121	+ .has_blink_output = true,
1802	3122	};
1803	3123
	3124	+#define TEGRA186_IO_PAD_TABLE(_pad) \
	3125	+ /* .id .dpd .voltage .name */ \
	3126	+ _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
	3127	+ _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
	3128	+ _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
	3129	+ _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
	3130	+ _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
	3131	+ _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
	3132	+ _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
	3133	+ _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
	3134	+ _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
	3135	+ _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
	3136	+ _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
	3137	+ _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
	3138	+ _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
	3139	+ _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
	3140	+ _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
	3141	+ _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
	3142	+ _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
	3143	+ _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
	3144	+ _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
	3145	+ _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
	3146	+ _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
	3147	+ _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
	3148	+ _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
	3149	+ _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
	3150	+ _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
	3151	+ _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
	3152	+ _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
	3153	+ _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
	3154	+ _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
	3155	+ _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
	3156	+ _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
	3157	+ _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
	3158	+ _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
	3159	+ _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
	3160	+ _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
	3161	+ _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
	3162	+ _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
	3163	+ _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
	3164	+
1804	3165	static const struct tegra_io_pad_soc tegra186_io_pads[] = {
1805		- { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
1806		- { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
1807		- { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX },
1808		- { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
1809		- { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX },
1810		- { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX },
1811		- { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
1812		- { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX },
1813		- { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX },
1814		- { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX },
1815		- { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX },
1816		- { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX },
1817		- { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
1818		- { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
1819		- { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX },
1820		- { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX },
1821		- { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX },
1822		- { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX },
1823		- { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
1824		- { .id = TEGRA_IO_PAD_SDMMC2_HV, .dpd = 34, .voltage = 5 },
1825		- { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX },
1826		- { .id = TEGRA_IO_PAD_CAM, .dpd = 38, .voltage = UINT_MAX },
1827		- { .id = TEGRA_IO_PAD_DSIB, .dpd = 40, .voltage = UINT_MAX },
1828		- { .id = TEGRA_IO_PAD_DSIC, .dpd = 41, .voltage = UINT_MAX },
1829		- { .id = TEGRA_IO_PAD_DSID, .dpd = 42, .voltage = UINT_MAX },
1830		- { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX },
1831		- { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX },
1832		- { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX },
1833		- { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX },
1834		- { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX },
1835		- { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX },
1836		- { .id = TEGRA_IO_PAD_DMIC_HV, .dpd = 52, .voltage = 2 },
1837		- { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX },
1838		- { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = 4 },
1839		- { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = 6 },
1840		- { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX },
1841		- { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 1 },
1842		- { .id = TEGRA_IO_PAD_AO_HV, .dpd = UINT_MAX, .voltage = 0 },
	3166	+ TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
	3167	+};
	3168	+
	3169	+static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
	3170	+ TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
1843	3171	};
1844	3172
1845	3173	static const struct tegra_pmc_regs tegra186_pmc_regs = {
..	..	@@ -1848,6 +3176,11 @@
1848	3176	.dpd_status = 0x78,
1849	3177	.dpd2_req = 0x7c,
1850	3178	.dpd2_status = 0x80,
	3179	+ .rst_status = 0x70,
	3180	+ .rst_source_shift = 0x2,
	3181	+ .rst_source_mask = 0x3c,
	3182	+ .rst_level_shift = 0x0,
	3183	+ .rst_level_mask = 0x3,
1851	3184	};
1852	3185
1853	3186	static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
..	..	@@ -1861,15 +3194,15 @@
1861	3194
1862	3195	index = of_property_match_string(np, "reg-names", "wake");
1863	3196	if (index < 0) {
1864		- pr_err("failed to find PMC wake registers\n");
	3197	+ dev_err(pmc->dev, "failed to find PMC wake registers\n");
1865	3198	return;
1866	3199	}
1867	3200
1868	3201	of_address_to_resource(np, index, &regs);
1869	3202
1870		- wake = ioremap_nocache(regs.start, resource_size(&regs));
	3203	+ wake = ioremap(regs.start, resource_size(&regs));
1871	3204	if (!wake) {
1872		- pr_err("failed to map PMC wake registers\n");
	3205	+ dev_err(pmc->dev, "failed to map PMC wake registers\n");
1873	3206	return;
1874	3207	}
1875	3208
..	..	@@ -1885,6 +3218,34 @@
1885	3218	iounmap(wake);
1886	3219	}
1887	3220
	3221	+static const char * const tegra186_reset_sources[] = {
	3222	+ "SYS_RESET",
	3223	+ "AOWDT",
	3224	+ "MCCPLEXWDT",
	3225	+ "BPMPWDT",
	3226	+ "SCEWDT",
	3227	+ "SPEWDT",
	3228	+ "APEWDT",
	3229	+ "BCCPLEXWDT",
	3230	+ "SENSOR",
	3231	+ "AOTAG",
	3232	+ "VFSENSOR",
	3233	+ "SWREST",
	3234	+ "SC7",
	3235	+ "HSM",
	3236	+ "CORESIGHT"
	3237	+};
	3238	+
	3239	+static const char * const tegra186_reset_levels[] = {
	3240	+ "L0", "L1", "L2", "WARM"
	3241	+};
	3242	+
	3243	+static const struct tegra_wake_event tegra186_wake_events[] = {
	3244	+ TEGRA_WAKE_IRQ("pmu", 24, 209),
	3245	+ TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
	3246	+ TEGRA_WAKE_IRQ("rtc", 73, 10),
	3247	+};
	3248	+
1888	3249	static const struct tegra_pmc_soc tegra186_pmc_soc = {
1889	3250	.num_powergates = 0,
1890	3251	.powergates = NULL,
..	..	@@ -1892,16 +3253,232 @@
1892	3253	.cpu_powergates = NULL,
1893	3254	.has_tsense_reset = false,
1894	3255	.has_gpu_clamps = false,
	3256	+ .needs_mbist_war = false,
1895	3257	.has_impl_33v_pwr = true,
	3258	+ .maybe_tz_only = false,
1896	3259	.num_io_pads = ARRAY_SIZE(tegra186_io_pads),
1897	3260	.io_pads = tegra186_io_pads,
	3261	+ .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
	3262	+ .pin_descs = tegra186_pin_descs,
1898	3263	.regs = &tegra186_pmc_regs,
1899	3264	.init = NULL,
1900	3265	.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
	3266	+ .irq_set_wake = tegra186_pmc_irq_set_wake,
	3267	+ .irq_set_type = tegra186_pmc_irq_set_type,
	3268	+ .reset_sources = tegra186_reset_sources,
	3269	+ .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
	3270	+ .reset_levels = tegra186_reset_levels,
	3271	+ .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
	3272	+ .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
	3273	+ .wake_events = tegra186_wake_events,
	3274	+ .pmc_clks_data = NULL,
	3275	+ .num_pmc_clks = 0,
	3276	+ .has_blink_output = false,
	3277	+};
	3278	+
	3279	+#define TEGRA194_IO_PAD_TABLE(_pad) \
	3280	+ /* .id .dpd .voltage .name */ \
	3281	+ _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
	3282	+ _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
	3283	+ _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
	3284	+ _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
	3285	+ _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
	3286	+ _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
	3287	+ _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
	3288	+ _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \
	3289	+ _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \
	3290	+ _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \
	3291	+ _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \
	3292	+ _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \
	3293	+ _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
	3294	+ _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \
	3295	+ _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \
	3296	+ _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
	3297	+ _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \
	3298	+ _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \
	3299	+ _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \
	3300	+ _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \
	3301	+ _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \
	3302	+ _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \
	3303	+ _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \
	3304	+ _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
	3305	+ _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \
	3306	+ _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \
	3307	+ _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
	3308	+ _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
	3309	+ _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
	3310	+ _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \
	3311	+ _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \
	3312	+ _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \
	3313	+ _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
	3314	+ _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \
	3315	+ _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
	3316	+ _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
	3317	+ _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
	3318	+ _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
	3319	+ _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
	3320	+ _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
	3321	+ _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
	3322	+ _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \
	3323	+ _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \
	3324	+ _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
	3325	+ _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
	3326	+ _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
	3327	+ _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
	3328	+ _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
	3329	+ _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
	3330	+
	3331	+static const struct tegra_io_pad_soc tegra194_io_pads[] = {
	3332	+ TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD)
	3333	+};
	3334	+
	3335	+static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
	3336	+ TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
	3337	+};
	3338	+
	3339	+static const struct tegra_pmc_regs tegra194_pmc_regs = {
	3340	+ .scratch0 = 0x2000,
	3341	+ .dpd_req = 0x74,
	3342	+ .dpd_status = 0x78,
	3343	+ .dpd2_req = 0x7c,
	3344	+ .dpd2_status = 0x80,
	3345	+ .rst_status = 0x70,
	3346	+ .rst_source_shift = 0x2,
	3347	+ .rst_source_mask = 0x7c,
	3348	+ .rst_level_shift = 0x0,
	3349	+ .rst_level_mask = 0x3,
	3350	+};
	3351	+
	3352	+static const char * const tegra194_reset_sources[] = {
	3353	+ "SYS_RESET_N",
	3354	+ "AOWDT",
	3355	+ "BCCPLEXWDT",
	3356	+ "BPMPWDT",
	3357	+ "SCEWDT",
	3358	+ "SPEWDT",
	3359	+ "APEWDT",
	3360	+ "LCCPLEXWDT",
	3361	+ "SENSOR",
	3362	+ "AOTAG",
	3363	+ "VFSENSOR",
	3364	+ "MAINSWRST",
	3365	+ "SC7",
	3366	+ "HSM",
	3367	+ "CSITE",
	3368	+ "RCEWDT",
	3369	+ "PVA0WDT",
	3370	+ "PVA1WDT",
	3371	+ "L1A_ASYNC",
	3372	+ "BPMPBOOT",
	3373	+ "FUSECRC",
	3374	+};
	3375	+
	3376	+static const struct tegra_wake_event tegra194_wake_events[] = {
	3377	+ TEGRA_WAKE_IRQ("pmu", 24, 209),
	3378	+ TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
	3379	+ TEGRA_WAKE_IRQ("rtc", 73, 10),
	3380	+};
	3381	+
	3382	+static const struct tegra_pmc_soc tegra194_pmc_soc = {
	3383	+ .num_powergates = 0,
	3384	+ .powergates = NULL,
	3385	+ .num_cpu_powergates = 0,
	3386	+ .cpu_powergates = NULL,
	3387	+ .has_tsense_reset = false,
	3388	+ .has_gpu_clamps = false,
	3389	+ .needs_mbist_war = false,
	3390	+ .has_impl_33v_pwr = true,
	3391	+ .maybe_tz_only = false,
	3392	+ .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
	3393	+ .io_pads = tegra194_io_pads,
	3394	+ .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
	3395	+ .pin_descs = tegra194_pin_descs,
	3396	+ .regs = &tegra194_pmc_regs,
	3397	+ .init = NULL,
	3398	+ .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
	3399	+ .irq_set_wake = tegra186_pmc_irq_set_wake,
	3400	+ .irq_set_type = tegra186_pmc_irq_set_type,
	3401	+ .reset_sources = tegra194_reset_sources,
	3402	+ .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
	3403	+ .reset_levels = tegra186_reset_levels,
	3404	+ .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
	3405	+ .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
	3406	+ .wake_events = tegra194_wake_events,
	3407	+ .pmc_clks_data = NULL,
	3408	+ .num_pmc_clks = 0,
	3409	+ .has_blink_output = false,
	3410	+};
	3411	+
	3412	+static const struct tegra_pmc_regs tegra234_pmc_regs = {
	3413	+ .scratch0 = 0x2000,
	3414	+ .dpd_req = 0,
	3415	+ .dpd_status = 0,
	3416	+ .dpd2_req = 0,
	3417	+ .dpd2_status = 0,
	3418	+ .rst_status = 0x70,
	3419	+ .rst_source_shift = 0x2,
	3420	+ .rst_source_mask = 0xfc,
	3421	+ .rst_level_shift = 0x0,
	3422	+ .rst_level_mask = 0x3,
	3423	+};
	3424	+
	3425	+static const char * const tegra234_reset_sources[] = {
	3426	+ "SYS_RESET_N",
	3427	+ "AOWDT",
	3428	+ "BCCPLEXWDT",
	3429	+ "BPMPWDT",
	3430	+ "SCEWDT",
	3431	+ "SPEWDT",
	3432	+ "APEWDT",
	3433	+ "LCCPLEXWDT",
	3434	+ "SENSOR",
	3435	+ "AOTAG",
	3436	+ "VFSENSOR",
	3437	+ "MAINSWRST",
	3438	+ "SC7",
	3439	+ "HSM",
	3440	+ "CSITE",
	3441	+ "RCEWDT",
	3442	+ "PVA0WDT",
	3443	+ "PVA1WDT",
	3444	+ "L1A_ASYNC",
	3445	+ "BPMPBOOT",
	3446	+ "FUSECRC",
	3447	+};
	3448	+
	3449	+static const struct tegra_pmc_soc tegra234_pmc_soc = {
	3450	+ .num_powergates = 0,
	3451	+ .powergates = NULL,
	3452	+ .num_cpu_powergates = 0,
	3453	+ .cpu_powergates = NULL,
	3454	+ .has_tsense_reset = false,
	3455	+ .has_gpu_clamps = false,
	3456	+ .needs_mbist_war = false,
	3457	+ .has_impl_33v_pwr = true,
	3458	+ .maybe_tz_only = false,
	3459	+ .num_io_pads = 0,
	3460	+ .io_pads = NULL,
	3461	+ .num_pin_descs = 0,
	3462	+ .pin_descs = NULL,
	3463	+ .regs = &tegra234_pmc_regs,
	3464	+ .init = NULL,
	3465	+ .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
	3466	+ .irq_set_wake = tegra186_pmc_irq_set_wake,
	3467	+ .irq_set_type = tegra186_pmc_irq_set_type,
	3468	+ .reset_sources = tegra234_reset_sources,
	3469	+ .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),
	3470	+ .reset_levels = tegra186_reset_levels,
	3471	+ .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
	3472	+ .num_wake_events = 0,
	3473	+ .wake_events = NULL,
	3474	+ .pmc_clks_data = NULL,
	3475	+ .num_pmc_clks = 0,
	3476	+ .has_blink_output = false,
1901	3477	};
1902	3478
1903	3479	static const struct of_device_id tegra_pmc_match[] = {
1904		- { .compatible = "nvidia,tegra194-pmc", .data = &tegra186_pmc_soc },
	3480	+ { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
	3481	+ { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
1905	3482	{ .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
1906	3483	{ .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
1907	3484	{ .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
..	..	@@ -1925,6 +3502,32 @@
1925	3502	};
1926	3503	builtin_platform_driver(tegra_pmc_driver);
1927	3504
	3505	+static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
	3506	+{
	3507	+ u32 value, saved;
	3508	+
	3509	+ saved = readl(pmc->base + pmc->soc->regs->scratch0);
	3510	+ value = saved ^ 0xffffffff;
	3511	+
	3512	+ if (value == 0xffffffff)
	3513	+ value = 0xdeadbeef;
	3514	+
	3515	+ /* write pattern and read it back */
	3516	+ writel(value, pmc->base + pmc->soc->regs->scratch0);
	3517	+ value = readl(pmc->base + pmc->soc->regs->scratch0);
	3518	+
	3519	+ /* if we read all-zeroes, access is restricted to TZ only */
	3520	+ if (value == 0) {
	3521	+ pr_info("access to PMC is restricted to TZ\n");
	3522	+ return true;
	3523	+ }
	3524	+
	3525	+ /* restore original value */
	3526	+ writel(saved, pmc->base + pmc->soc->regs->scratch0);
	3527	+
	3528	+ return false;
	3529	+}
	3530	+
1928	3531	/*
1929	3532	* Early initialization to allow access to registers in the very early boot
1930	3533	* process.
..	..	@@ -1934,6 +3537,7 @@
1934	3537	const struct of_device_id *match;
1935	3538	struct device_node *np;
1936	3539	struct resource regs;
	3540	+ unsigned int i;
1937	3541	bool invert;
1938	3542
1939	3543	mutex_init(&pmc->powergates_lock);
..	..	@@ -1977,7 +3581,7 @@
1977	3581	}
1978	3582	}
1979	3583
1980		- pmc->base = ioremap_nocache(regs.start, resource_size(&regs));
	3584	+ pmc->base = ioremap(regs.start, resource_size(&regs));
1981	3585	if (!pmc->base) {
1982	3586	pr_err("failed to map PMC registers\n");
1983	3587	of_node_put(np);
..	..	@@ -1987,7 +3591,13 @@
1987	3591	if (np) {
1988	3592	pmc->soc = match->data;
1989	3593
1990		- tegra_powergate_init(pmc, np);
	3594	+ if (pmc->soc->maybe_tz_only)
	3595	+ pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
	3596	+
	3597	+ /* Create a bitmap of the available and valid partitions */
	3598	+ for (i = 0; i < pmc->soc->num_powergates; i++)
	3599	+ if (pmc->soc->powergates[i])
	3600	+ set_bit(i, pmc->powergates_available);
1991	3601
1992	3602	/*
1993	3603	* Invert the interrupt polarity if a PMC device tree node