~hc/RK356X_SDK_RELEASE.git

..	..	@@ -74,32 +74,62 @@
74	74	#define MAX_HBA_QUEUE_DEPTH 30000
75	75	#define MAX_CHAIN_DEPTH 100000
76	76	static int max_queue_depth = -1;
77		-module_param(max_queue_depth, int, 0);
	77	+module_param(max_queue_depth, int, 0444);
78	78	MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
79	79
80	80	static int max_sgl_entries = -1;
81		-module_param(max_sgl_entries, int, 0);
	81	+module_param(max_sgl_entries, int, 0444);
82	82	MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
83	83
84	84	static int msix_disable = -1;
85		-module_param(msix_disable, int, 0);
	85	+module_param(msix_disable, int, 0444);
86	86	MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
87	87
88	88	static int smp_affinity_enable = 1;
89		-module_param(smp_affinity_enable, int, S_IRUGO);
	89	+module_param(smp_affinity_enable, int, 0444);
90	90	MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disable Default: enable(1)");
91	91
92	92	static int max_msix_vectors = -1;
93		-module_param(max_msix_vectors, int, 0);
	93	+module_param(max_msix_vectors, int, 0444);
94	94	MODULE_PARM_DESC(max_msix_vectors,
95	95	" max msix vectors");
	96	+
	97	+static int irqpoll_weight = -1;
	98	+module_param(irqpoll_weight, int, 0444);
	99	+MODULE_PARM_DESC(irqpoll_weight,
	100	+ "irq poll weight (default= one fourth of HBA queue depth)");
96	101
97	102	static int mpt3sas_fwfault_debug;
98	103	MODULE_PARM_DESC(mpt3sas_fwfault_debug,
99	104	" enable detection of firmware fault and halt firmware - (default=0)");
100	105
	106	+static int perf_mode = -1;
	107	+module_param(perf_mode, int, 0444);
	108	+MODULE_PARM_DESC(perf_mode,
	109	+ "Performance mode (only for Aero/Sea Generation), options:\n\t\t"
	110	+ "0 - balanced: high iops mode is enabled &\n\t\t"
	111	+ "interrupt coalescing is enabled only on high iops queues,\n\t\t"
	112	+ "1 - iops: high iops mode is disabled &\n\t\t"
	113	+ "interrupt coalescing is enabled on all queues,\n\t\t"
	114	+ "2 - latency: high iops mode is disabled &\n\t\t"
	115	+ "interrupt coalescing is enabled on all queues with timeout value 0xA,\n"
	116	+ "\t\tdefault - default perf_mode is 'balanced'"
	117	+ );
	118	+
	119	+enum mpt3sas_perf_mode {
	120	+ MPT_PERF_MODE_DEFAULT = -1,
	121	+ MPT_PERF_MODE_BALANCED = 0,
	122	+ MPT_PERF_MODE_IOPS = 1,
	123	+ MPT_PERF_MODE_LATENCY = 2,
	124	+};
	125	+
	126	+static int
	127	+_base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc,
	128	+ u32 ioc_state, int timeout);
101	129	static int
102	130	_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc);
	131	+static void
	132	+_base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc);
103	133
104	134	/**
105	135	* mpt3sas_base_check_cmd_timeout - Function
..	..	@@ -122,8 +152,8 @@
122	152	if (!(status & MPT3_CMD_RESET))
123	153	issue_reset = 1;
124	154
125		- pr_err(MPT3SAS_FMT "Command %s\n", ioc->name,
126		- ((issue_reset == 0) ? "terminated due to Host Reset" : "Timeout"));
	155	+ ioc_err(ioc, "Command %s\n",
	156	+ issue_reset == 0 ? "terminated due to Host Reset" : "Timeout");
127	157	_debug_dump_mf(mpi_request, sz);
128	158
129	159	return issue_reset;
..	..	@@ -155,6 +185,32 @@
155	185	}
156	186	module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
157	187	param_get_int, &mpt3sas_fwfault_debug, 0644);
	188	+
	189	+/**
	190	+ * _base_readl_aero - retry readl for max three times.
	191	+ * @addr: MPT Fusion system interface register address
	192	+ *
	193	+ * Retry the readl() for max three times if it gets zero value
	194	+ * while reading the system interface register.
	195	+ */
	196	+static inline u32
	197	+_base_readl_aero(const volatile void __iomem *addr)
	198	+{
	199	+ u32 i = 0, ret_val;
	200	+
	201	+ do {
	202	+ ret_val = readl(addr);
	203	+ i++;
	204	+ } while (ret_val == 0 && i < 3);
	205	+
	206	+ return ret_val;
	207	+}
	208	+
	209	+static inline u32
	210	+_base_readl(const volatile void __iomem *addr)
	211	+{
	212	+ return readl(addr);
	213	+}
158	214
159	215	/**
160	216	* _base_clone_reply_to_sys_mem - copies reply to reply free iomem
..	..	@@ -336,9 +392,7 @@
336	392	return ct->chain_buffer;
337	393	}
338	394	}
339		- pr_info(MPT3SAS_FMT
340		- "Provided chain_buffer_dma address is not in the lookup list\n",
341		- ioc->name);
	395	+ ioc_info(ioc, "Provided chain_buffer_dma address is not in the lookup list\n");
342	396	return NULL;
343	397	}
344	398
..	..	@@ -357,7 +411,7 @@
357	411	{
358	412	Mpi2SGESimple32_t sgel, sgel_next;
359	413	u32 sgl_flags, sge_chain_count = 0;
360		- bool is_write = 0;
	414	+ bool is_write = false;
361	415	u16 i = 0;
362	416	void __iomem *buffer_iomem;
363	417	phys_addr_t buffer_iomem_phys;
..	..	@@ -394,7 +448,7 @@
394	448	/* Get scsi_cmd using smid */
395	449	scmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
396	450	if (scmd == NULL) {
397		- pr_err(MPT3SAS_FMT "scmd is NULL\n", ioc->name);
	451	+ ioc_err(ioc, "scmd is NULL\n");
398	452	return;
399	453	}
400	454
..	..	@@ -426,7 +480,7 @@
426	480
427	481	if (le32_to_cpu(sgel->FlagsLength) &
428	482	(MPI2_SGE_FLAGS_HOST_TO_IOC << MPI2_SGE_FLAGS_SHIFT))
429		- is_write = 1;
	483	+ is_write = true;
430	484
431	485	for (i = 0; i < MPT_MIN_PHYS_SEGMENTS + ioc->facts.MaxChainDepth; i++) {
432	486
..	..	@@ -532,11 +586,11 @@
532	586	struct MPT3SAS_ADAPTER ioc = (struct MPT3SAS_ADAPTER )arg;
533	587	struct pci_dev *pdev;
534	588
535		- if ((ioc == NULL))
	589	+ if (!ioc)
536	590	return -1;
537	591
538	592	pdev = ioc->pdev;
539		- if ((pdev == NULL))
	593	+ if (!pdev)
540	594	return -1;
541	595	pci_stop_and_remove_bus_device_locked(pdev);
542	596	return 0;
..	..	@@ -560,14 +614,14 @@
560	614
561	615
562	616	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
563		- if (ioc->shost_recovery \|\| ioc->pci_error_recovery)
	617	+ if ((ioc->shost_recovery && (ioc->ioc_coredump_loop == 0)) \|\|
	618	+ ioc->pci_error_recovery)
564	619	goto rearm_timer;
565	620	spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
566	621
567	622	doorbell = mpt3sas_base_get_iocstate(ioc, 0);
568	623	if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
569		- pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
570		- ioc->name);
	624	+ ioc_err(ioc, "SAS host is non-operational !!!!\n");
571	625
572	626	/* It may be possible that EEH recovery can resolve some of
573	627	* pci bus failure issues rather removing the dead ioc function
..	..	@@ -600,30 +654,72 @@
600	654	p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
601	655	"%s_dead_ioc_%d", ioc->driver_name, ioc->id);
602	656	if (IS_ERR(p))
603		- pr_err(MPT3SAS_FMT
604		- "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
605		- ioc->name, __func__);
	657	+ ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
	658	+ __func__);
606	659	else
607		- pr_err(MPT3SAS_FMT
608		- "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
609		- ioc->name, __func__);
	660	+ ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
	661	+ __func__);
610	662	return; /* don't rearm timer */
611	663	}
612	664
613		- ioc->non_operational_loop = 0;
	665	+ if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) {
	666	+ u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
	667	+ ioc->manu_pg11.CoreDumpTOSec :
	668	+ MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
614	669
	670	+ timeout /= (FAULT_POLLING_INTERVAL/1000);
	671	+
	672	+ if (ioc->ioc_coredump_loop == 0) {
	673	+ mpt3sas_print_coredump_info(ioc,
	674	+ doorbell & MPI2_DOORBELL_DATA_MASK);
	675	+ /* do not accept any IOs and disable the interrupts */
	676	+ spin_lock_irqsave(
	677	+ &ioc->ioc_reset_in_progress_lock, flags);
	678	+ ioc->shost_recovery = 1;
	679	+ spin_unlock_irqrestore(
	680	+ &ioc->ioc_reset_in_progress_lock, flags);
	681	+ mpt3sas_base_mask_interrupts(ioc);
	682	+ _base_clear_outstanding_commands(ioc);
	683	+ }
	684	+
	685	+ ioc_info(ioc, "%s: CoreDump loop %d.",
	686	+ __func__, ioc->ioc_coredump_loop);
	687	+
	688	+ /* Wait until CoreDump completes or times out */
	689	+ if (ioc->ioc_coredump_loop++ < timeout) {
	690	+ spin_lock_irqsave(
	691	+ &ioc->ioc_reset_in_progress_lock, flags);
	692	+ goto rearm_timer;
	693	+ }
	694	+ }
	695	+
	696	+ if (ioc->ioc_coredump_loop) {
	697	+ if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_COREDUMP)
	698	+ ioc_err(ioc, "%s: CoreDump completed. LoopCount: %d",
	699	+ __func__, ioc->ioc_coredump_loop);
	700	+ else
	701	+ ioc_err(ioc, "%s: CoreDump Timed out. LoopCount: %d",
	702	+ __func__, ioc->ioc_coredump_loop);
	703	+ ioc->ioc_coredump_loop = MPT3SAS_COREDUMP_LOOP_DONE;
	704	+ }
	705	+ ioc->non_operational_loop = 0;
615	706	if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
616	707	rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
617		- pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
618		- __func__, (rc == 0) ? "success" : "failed");
	708	+ ioc_warn(ioc, "%s: hard reset: %s\n",
	709	+ __func__, rc == 0 ? "success" : "failed");
619	710	doorbell = mpt3sas_base_get_iocstate(ioc, 0);
620		- if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
621		- mpt3sas_base_fault_info(ioc, doorbell &
	711	+ if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
	712	+ mpt3sas_print_fault_code(ioc, doorbell &
	713	+ MPI2_DOORBELL_DATA_MASK);
	714	+ } else if ((doorbell & MPI2_IOC_STATE_MASK) ==
	715	+ MPI2_IOC_STATE_COREDUMP)
	716	+ mpt3sas_print_coredump_info(ioc, doorbell &
622	717	MPI2_DOORBELL_DATA_MASK);
623	718	if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
624	719	MPI2_IOC_STATE_OPERATIONAL)
625	720	return; /* don't rearm timer */
626	721	}
	722	+ ioc->ioc_coredump_loop = 0;
627	723
628	724	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
629	725	rearm_timer:
..	..	@@ -657,8 +753,7 @@
657	753	ioc->fault_reset_work_q =
658	754	create_singlethread_workqueue(ioc->fault_reset_work_q_name);
659	755	if (!ioc->fault_reset_work_q) {
660		- pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
661		- ioc->name, __func__, __LINE__);
	756	+ ioc_err(ioc, "%s: failed (line=%d)\n", __func__, __LINE__);
662	757	return;
663	758	}
664	759	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
..	..	@@ -700,8 +795,51 @@
700	795	void
701	796	mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
702	797	{
703		- pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
704		- ioc->name, fault_code);
	798	+ ioc_err(ioc, "fault_state(0x%04x)!\n", fault_code);
	799	+}
	800	+
	801	+/**
	802	+ * mpt3sas_base_coredump_info - verbose translation of firmware CoreDump state
	803	+ * @ioc: per adapter object
	804	+ * @fault_code: fault code
	805	+ *
	806	+ * Return nothing.
	807	+ */
	808	+void
	809	+mpt3sas_base_coredump_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code)
	810	+{
	811	+ ioc_err(ioc, "coredump_state(0x%04x)!\n", fault_code);
	812	+}
	813	+
	814	+/**
	815	+ * mpt3sas_base_wait_for_coredump_completion - Wait until coredump
	816	+ * completes or times out
	817	+ * @ioc: per adapter object
	818	+ * @caller: caller function name
	819	+ *
	820	+ * Returns 0 for success, non-zero for failure.
	821	+ */
	822	+int
	823	+mpt3sas_base_wait_for_coredump_completion(struct MPT3SAS_ADAPTER *ioc,
	824	+ const char *caller)
	825	+{
	826	+ u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
	827	+ ioc->manu_pg11.CoreDumpTOSec :
	828	+ MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
	829	+
	830	+ int ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_FAULT,
	831	+ timeout);
	832	+
	833	+ if (ioc_state)
	834	+ ioc_err(ioc,
	835	+ "%s: CoreDump timed out. (ioc_state=0x%x)\n",
	836	+ caller, ioc_state);
	837	+ else
	838	+ ioc_info(ioc,
	839	+ "%s: CoreDump completed. (ioc_state=0x%x)\n",
	840	+ caller, ioc_state);
	841	+
	842	+ return ioc_state;
705	843	}
706	844
707	845	/**
..	..	@@ -723,13 +861,17 @@
723	861
724	862	dump_stack();
725	863
726		- doorbell = readl(&ioc->chip->Doorbell);
727		- if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
728		- mpt3sas_base_fault_info(ioc , doorbell);
729		- else {
	864	+ doorbell = ioc->base_readl(&ioc->chip->Doorbell);
	865	+ if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
	866	+ mpt3sas_print_fault_code(ioc, doorbell &
	867	+ MPI2_DOORBELL_DATA_MASK);
	868	+ } else if ((doorbell & MPI2_IOC_STATE_MASK) ==
	869	+ MPI2_IOC_STATE_COREDUMP) {
	870	+ mpt3sas_print_coredump_info(ioc, doorbell &
	871	+ MPI2_DOORBELL_DATA_MASK);
	872	+ } else {
730	873	writel(0xC0FFEE00, &ioc->chip->Doorbell);
731		- pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
732		- ioc->name);
	874	+ ioc_err(ioc, "Firmware is halted due to command timeout\n");
733	875	}
734	876
735	877	if (ioc->fwfault_debug == 2)
..	..	@@ -956,8 +1098,8 @@
956	1098	break;
957	1099	}
958	1100
959		- pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
960		- ioc->name, desc, ioc_status, request_hdr, func_str);
	1101	+ ioc_warn(ioc, "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
	1102	+ desc, ioc_status, request_hdr, func_str);
961	1103
962	1104	_debug_dump_mf(request_hdr, frame_sz/4);
963	1105	}
..	..	@@ -1003,9 +1145,9 @@
1003	1145	{
1004	1146	Mpi2EventDataSasDiscovery_t *event_data =
1005	1147	(Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
1006		- pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
1007		- (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
1008		- "start" : "stop");
	1148	+ ioc_info(ioc, "Discovery: (%s)",
	1149	+ event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED ?
	1150	+ "start" : "stop");
1009	1151	if (event_data->DiscoveryStatus)
1010	1152	pr_cont(" discovery_status(0x%08x)",
1011	1153	le32_to_cpu(event_data->DiscoveryStatus));
..	..	@@ -1059,14 +1201,13 @@
1059	1201	{
1060	1202	Mpi26EventDataPCIeEnumeration_t *event_data =
1061	1203	(Mpi26EventDataPCIeEnumeration_t *)mpi_reply->EventData;
1062		- pr_info(MPT3SAS_FMT "PCIE Enumeration: (%s)", ioc->name,
1063		- (event_data->ReasonCode ==
1064		- MPI26_EVENT_PCIE_ENUM_RC_STARTED) ?
1065		- "start" : "stop");
	1204	+ ioc_info(ioc, "PCIE Enumeration: (%s)",
	1205	+ event_data->ReasonCode == MPI26_EVENT_PCIE_ENUM_RC_STARTED ?
	1206	+ "start" : "stop");
1066	1207	if (event_data->EnumerationStatus)
1067		- pr_info("enumeration_status(0x%08x)",
1068		- le32_to_cpu(event_data->EnumerationStatus));
1069		- pr_info("\n");
	1208	+ pr_cont("enumeration_status(0x%08x)",
	1209	+ le32_to_cpu(event_data->EnumerationStatus));
	1210	+ pr_cont("\n");
1070	1211	return;
1071	1212	}
1072	1213	case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
..	..	@@ -1077,7 +1218,7 @@
1077	1218	if (!desc)
1078	1219	return;
1079	1220
1080		- pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
	1221	+ ioc_info(ioc, "%s\n", desc);
1081	1222	}
1082	1223
1083	1224	/**
..	..	@@ -1128,11 +1269,9 @@
1128	1269	break;
1129	1270	}
1130	1271
1131		- pr_warn(MPT3SAS_FMT
1132		- "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
1133		- ioc->name, log_info,
1134		- originator_str, sas_loginfo.dw.code,
1135		- sas_loginfo.dw.subcode);
	1272	+ ioc_warn(ioc, "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
	1273	+ log_info,
	1274	+ originator_str, sas_loginfo.dw.code, sas_loginfo.dw.subcode);
1136	1275	}
1137	1276
1138	1277	/**
..	..	@@ -1152,8 +1291,8 @@
1152	1291
1153	1292	mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1154	1293	if (unlikely(!mpi_reply)) {
1155		- pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
1156		- ioc->name, __FILE__, __LINE__, __func__);
	1294	+ ioc_err(ioc, "mpi_reply not valid at %s:%d/%s()!\n",
	1295	+ __FILE__, __LINE__, __func__);
1157	1296	return;
1158	1297	}
1159	1298	ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
..	..	@@ -1249,9 +1388,9 @@
1249	1388	delayed_event_ack->EventContext = mpi_reply->EventContext;
1250	1389	list_add_tail(&delayed_event_ack->list,
1251	1390	&ioc->delayed_event_ack_list);
1252		- dewtprintk(ioc, pr_info(MPT3SAS_FMT
1253		- "DELAYED: EVENT ACK: event (0x%04x)\n",
1254		- ioc->name, le16_to_cpu(mpi_reply->Event)));
	1391	+ dewtprintk(ioc,
	1392	+ ioc_info(ioc, "DELAYED: EVENT ACK: event (0x%04x)\n",
	1393	+ le16_to_cpu(mpi_reply->Event)));
1255	1394	goto out;
1256	1395	}
1257	1396
..	..	@@ -1262,7 +1401,7 @@
1262	1401	ack_request->EventContext = mpi_reply->EventContext;
1263	1402	ack_request->VF_ID = 0; /* TODO */
1264	1403	ack_request->VP_ID = 0;
1265		- mpt3sas_base_put_smid_default(ioc, smid);
	1404	+ ioc->put_smid_default(ioc, smid);
1266	1405
1267	1406	out:
1268	1407
..	..	@@ -1325,35 +1464,35 @@
1325	1464	}
1326	1465
1327	1466	/**
1328		- * _base_mask_interrupts - disable interrupts
	1467	+ * mpt3sas_base_mask_interrupts - disable interrupts
1329	1468	* @ioc: per adapter object
1330	1469	*
1331	1470	* Disabling ResetIRQ, Reply and Doorbell Interrupts
1332	1471	*/
1333		-static void
1334		-_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
	1472	+void
	1473	+mpt3sas_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1335	1474	{
1336	1475	u32 him_register;
1337	1476
1338	1477	ioc->mask_interrupts = 1;
1339		- him_register = readl(&ioc->chip->HostInterruptMask);
	1478	+ him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1340	1479	him_register \|= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
1341	1480	writel(him_register, &ioc->chip->HostInterruptMask);
1342		- readl(&ioc->chip->HostInterruptMask);
	1481	+ ioc->base_readl(&ioc->chip->HostInterruptMask);
1343	1482	}
1344	1483
1345	1484	/**
1346		- * _base_unmask_interrupts - enable interrupts
	1485	+ * mpt3sas_base_unmask_interrupts - enable interrupts
1347	1486	* @ioc: per adapter object
1348	1487	*
1349	1488	* Enabling only Reply Interrupts
1350	1489	*/
1351		-static void
1352		-_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
	1490	+void
	1491	+mpt3sas_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1353	1492	{
1354	1493	u32 him_register;
1355	1494
1356		- him_register = readl(&ioc->chip->HostInterruptMask);
	1495	+ him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1357	1496	him_register &= ~MPI2_HIM_RIM;
1358	1497	writel(him_register, &ioc->chip->HostInterruptMask);
1359	1498	ioc->mask_interrupts = 0;
..	..	@@ -1367,20 +1506,30 @@
1367	1506	} u;
1368	1507	};
1369	1508
1370		-/**
1371		- * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
1372		- * @irq: irq number (not used)
1373		- * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
1374		- *
1375		- * Return: IRQ_HANDLED if processed, else IRQ_NONE.
1376		- */
1377		-static irqreturn_t
1378		-_base_interrupt(int irq, void *bus_id)
	1509	+static u32 base_mod64(u64 dividend, u32 divisor)
1379	1510	{
1380		- struct adapter_reply_queue *reply_q = bus_id;
	1511	+ u32 remainder;
	1512	+
	1513	+ if (!divisor)
	1514	+ pr_err("mpt3sas: DIVISOR is zero, in div fn\n");
	1515	+ remainder = do_div(dividend, divisor);
	1516	+ return remainder;
	1517	+}
	1518	+
	1519	+/**
	1520	+ * _base_process_reply_queue - Process reply descriptors from reply
	1521	+ * descriptor post queue.
	1522	+ * @reply_q: per IRQ's reply queue object.
	1523	+ *
	1524	+ * Return: number of reply descriptors processed from reply
	1525	+ * descriptor queue.
	1526	+ */
	1527	+static int
	1528	+_base_process_reply_queue(struct adapter_reply_queue *reply_q)
	1529	+{
1381	1530	union reply_descriptor rd;
1382		- u32 completed_cmds;
1383		- u8 request_desript_type;
	1531	+ u64 completed_cmds;
	1532	+ u8 request_descript_type;
1384	1533	u16 smid;
1385	1534	u8 cb_idx;
1386	1535	u32 reply;
..	..	@@ -1389,21 +1538,18 @@
1389	1538	Mpi2ReplyDescriptorsUnion_t *rpf;
1390	1539	u8 rc;
1391	1540
1392		- if (ioc->mask_interrupts)
1393		- return IRQ_NONE;
1394		-
	1541	+ completed_cmds = 0;
1395	1542	if (!atomic_add_unless(&reply_q->busy, 1, 1))
1396		- return IRQ_NONE;
	1543	+ return completed_cmds;
1397	1544
1398	1545	rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
1399		- request_desript_type = rpf->Default.ReplyFlags
	1546	+ request_descript_type = rpf->Default.ReplyFlags
1400	1547	& MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1401		- if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
	1548	+ if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
1402	1549	atomic_dec(&reply_q->busy);
1403		- return IRQ_NONE;
	1550	+ return completed_cmds;
1404	1551	}
1405	1552
1406		- completed_cmds = 0;
1407	1553	cb_idx = 0xFF;
1408	1554	do {
1409	1555	rd.word = le64_to_cpu(rpf->Words);
..	..	@@ -1411,11 +1557,11 @@
1411	1557	goto out;
1412	1558	reply = 0;
1413	1559	smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
1414		- if (request_desript_type ==
	1560	+ if (request_descript_type ==
1415	1561	MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS \|\|
1416		- request_desript_type ==
	1562	+ request_descript_type ==
1417	1563	MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS \|\|
1418		- request_desript_type ==
	1564	+ request_descript_type ==
1419	1565	MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS) {
1420	1566	cb_idx = _base_get_cb_idx(ioc, smid);
1421	1567	if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
..	..	@@ -1425,7 +1571,7 @@
1425	1571	if (rc)
1426	1572	mpt3sas_base_free_smid(ioc, smid);
1427	1573	}
1428		- } else if (request_desript_type ==
	1574	+ } else if (request_descript_type ==
1429	1575	MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
1430	1576	reply = le32_to_cpu(
1431	1577	rpf->AddressReply.ReplyFrameAddress);
..	..	@@ -1471,7 +1617,7 @@
1471	1617	(reply_q->reply_post_host_index ==
1472	1618	(ioc->reply_post_queue_depth - 1)) ? 0 :
1473	1619	reply_q->reply_post_host_index + 1;
1474		- request_desript_type =
	1620	+ request_descript_type =
1475	1621	reply_q->reply_post_free[reply_q->reply_post_host_index].
1476	1622	Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1477	1623	completed_cmds++;
..	..	@@ -1480,7 +1626,7 @@
1480	1626	* So that FW can find enough entries to post the Reply
1481	1627	* Descriptors in the reply descriptor post queue.
1482	1628	*/
1483		- if (completed_cmds > ioc->hba_queue_depth/3) {
	1629	+ if (completed_cmds >= ioc->thresh_hold) {
1484	1630	if (ioc->combined_reply_queue) {
1485	1631	writel(reply_q->reply_post_host_index \|
1486	1632	((msix_index & 7) <<
..	..	@@ -1492,9 +1638,14 @@
1492	1638	MPI2_RPHI_MSIX_INDEX_SHIFT),
1493	1639	&ioc->chip->ReplyPostHostIndex);
1494	1640	}
1495		- completed_cmds = 1;
	1641	+ if (!reply_q->irq_poll_scheduled) {
	1642	+ reply_q->irq_poll_scheduled = true;
	1643	+ irq_poll_sched(&reply_q->irqpoll);
	1644	+ }
	1645	+ atomic_dec(&reply_q->busy);
	1646	+ return completed_cmds;
1496	1647	}
1497		- if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
	1648	+ if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1498	1649	goto out;
1499	1650	if (!reply_q->reply_post_host_index)
1500	1651	rpf = reply_q->reply_post_free;
..	..	@@ -1506,14 +1657,14 @@
1506	1657
1507	1658	if (!completed_cmds) {
1508	1659	atomic_dec(&reply_q->busy);
1509		- return IRQ_NONE;
	1660	+ return completed_cmds;
1510	1661	}
1511	1662
1512	1663	if (ioc->is_warpdrive) {
1513	1664	writel(reply_q->reply_post_host_index,
1514	1665	ioc->reply_post_host_index[msix_index]);
1515	1666	atomic_dec(&reply_q->busy);
1516		- return IRQ_HANDLED;
	1667	+ return completed_cmds;
1517	1668	}
1518	1669
1519	1670	/* Update Reply Post Host Index.
..	..	@@ -1540,7 +1691,89 @@
1540	1691	MPI2_RPHI_MSIX_INDEX_SHIFT),
1541	1692	&ioc->chip->ReplyPostHostIndex);
1542	1693	atomic_dec(&reply_q->busy);
1543		- return IRQ_HANDLED;
	1694	+ return completed_cmds;
	1695	+}
	1696	+
	1697	+/**
	1698	+ * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
	1699	+ * @irq: irq number (not used)
	1700	+ * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
	1701	+ *
	1702	+ * Return: IRQ_HANDLED if processed, else IRQ_NONE.
	1703	+ */
	1704	+static irqreturn_t
	1705	+_base_interrupt(int irq, void *bus_id)
	1706	+{
	1707	+ struct adapter_reply_queue *reply_q = bus_id;
	1708	+ struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
	1709	+
	1710	+ if (ioc->mask_interrupts)
	1711	+ return IRQ_NONE;
	1712	+ if (reply_q->irq_poll_scheduled)
	1713	+ return IRQ_HANDLED;
	1714	+ return ((_base_process_reply_queue(reply_q) > 0) ?
	1715	+ IRQ_HANDLED : IRQ_NONE);
	1716	+}
	1717	+
	1718	+/**
	1719	+ * _base_irqpoll - IRQ poll callback handler
	1720	+ * @irqpoll: irq_poll object
	1721	+ * @budget: irq poll weight
	1722	+ *
	1723	+ * returns number of reply descriptors processed
	1724	+ */
	1725	+static int
	1726	+_base_irqpoll(struct irq_poll *irqpoll, int budget)
	1727	+{
	1728	+ struct adapter_reply_queue *reply_q;
	1729	+ int num_entries = 0;
	1730	+
	1731	+ reply_q = container_of(irqpoll, struct adapter_reply_queue,
	1732	+ irqpoll);
	1733	+ if (reply_q->irq_line_enable) {
	1734	+ disable_irq_nosync(reply_q->os_irq);
	1735	+ reply_q->irq_line_enable = false;
	1736	+ }
	1737	+ num_entries = _base_process_reply_queue(reply_q);
	1738	+ if (num_entries < budget) {
	1739	+ irq_poll_complete(irqpoll);
	1740	+ reply_q->irq_poll_scheduled = false;
	1741	+ reply_q->irq_line_enable = true;
	1742	+ enable_irq(reply_q->os_irq);
	1743	+ /*
	1744	+ * Go for one more round of processing the
	1745	+ * reply descriptor post queue incase if HBA
	1746	+ * Firmware has posted some reply descriptors
	1747	+ * while reenabling the IRQ.
	1748	+ */
	1749	+ _base_process_reply_queue(reply_q);
	1750	+ }
	1751	+
	1752	+ return num_entries;
	1753	+}
	1754	+
	1755	+/**
	1756	+ * _base_init_irqpolls - initliaze IRQ polls
	1757	+ * @ioc: per adapter object
	1758	+ *
	1759	+ * returns nothing
	1760	+ */
	1761	+static void
	1762	+_base_init_irqpolls(struct MPT3SAS_ADAPTER *ioc)
	1763	+{
	1764	+ struct adapter_reply_queue reply_q, next;
	1765	+
	1766	+ if (list_empty(&ioc->reply_queue_list))
	1767	+ return;
	1768	+
	1769	+ list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
	1770	+ irq_poll_init(&reply_q->irqpoll,
	1771	+ ioc->hba_queue_depth/4, _base_irqpoll);
	1772	+ reply_q->irq_poll_scheduled = false;
	1773	+ reply_q->irq_line_enable = true;
	1774	+ reply_q->os_irq = pci_irq_vector(ioc->pdev,
	1775	+ reply_q->msix_index);
	1776	+ }
1544	1777	}
1545	1778
1546	1779	/**
..	..	@@ -1559,12 +1792,14 @@
1559	1792	/**
1560	1793	* mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
1561	1794	* @ioc: per adapter object
	1795	+ * @poll: poll over reply descriptor pools incase interrupt for
	1796	+ * timed-out SCSI command got delayed
1562	1797	* Context: non ISR conext
1563	1798	*
1564	1799	* Called when a Task Management request has completed.
1565	1800	*/
1566	1801	void
1567		-mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc)
	1802	+mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc, u8 poll)
1568	1803	{
1569	1804	struct adapter_reply_queue *reply_q;
1570	1805
..	..	@@ -1582,6 +1817,24 @@
1582	1817	if (reply_q->msix_index == 0)
1583	1818	continue;
1584	1819	synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index));
	1820	+ if (reply_q->irq_poll_scheduled) {
	1821	+ /* Calling irq_poll_disable will wait for any pending
	1822	+ * callbacks to have completed.
	1823	+ */
	1824	+ irq_poll_disable(&reply_q->irqpoll);
	1825	+ irq_poll_enable(&reply_q->irqpoll);
	1826	+ /* check how the scheduled poll has ended,
	1827	+ * clean up only if necessary
	1828	+ */
	1829	+ if (reply_q->irq_poll_scheduled) {
	1830	+ reply_q->irq_poll_scheduled = false;
	1831	+ reply_q->irq_line_enable = true;
	1832	+ enable_irq(reply_q->os_irq);
	1833	+ }
	1834	+ }
	1835	+
	1836	+ if (poll)
	1837	+ _base_process_reply_queue(reply_q);
1585	1838	}
1586	1839	}
1587	1840
..	..	@@ -2122,6 +2375,11 @@
2122	2375	bool build_prp = true;
2123	2376
2124	2377	data_length = scsi_bufflen(scmd);
	2378	+ if (pcie_device &&
	2379	+ (mpt3sas_scsih_is_pcie_scsi_device(pcie_device->device_info))) {
	2380	+ build_prp = false;
	2381	+ return build_prp;
	2382	+ }
2125	2383
2126	2384	/* If Datalenth is <= 16K and number of SGE’s entries are <= 2
2127	2385	* we built IEEE SGL
..	..	@@ -2270,7 +2528,7 @@
2270	2528	sges_left = scsi_dma_map(scmd);
2271	2529	if (sges_left < 0) {
2272	2530	sdev_printk(KERN_ERR, scmd->device,
2273		- "pci_map_sg failed: request for %d bytes!\n",
	2531	+ "scsi_dma_map failed: request for %d bytes!\n",
2274	2532	scsi_bufflen(scmd));
2275	2533	return -ENOMEM;
2276	2534	}
..	..	@@ -2418,7 +2676,7 @@
2418	2676	sges_left = scsi_dma_map(scmd);
2419	2677	if (sges_left < 0) {
2420	2678	sdev_printk(KERN_ERR, scmd->device,
2421		- "pci_map_sg failed: request for %d bytes!\n",
	2679	+ "scsi_dma_map failed: request for %d bytes!\n",
2422	2680	scsi_bufflen(scmd));
2423	2681	return -ENOMEM;
2424	2682	}
..	..	@@ -2564,57 +2822,33 @@
2564	2822	_base_config_dma_addressing(struct MPT3SAS_ADAPTER ioc, struct pci_dev pdev)
2565	2823	{
2566	2824	struct sysinfo s;
2567		- u64 consistent_dma_mask;
2568		- /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
2569		- int dma_mask = (ioc->hba_mpi_version_belonged > MPI2_VERSION) ? 63 : 64;
2570	2825
2571		- if (ioc->is_mcpu_endpoint)
2572		- goto try_32bit;
2573		-
2574		- if (ioc->dma_mask)
2575		- consistent_dma_mask = DMA_BIT_MASK(dma_mask);
2576		- else
2577		- consistent_dma_mask = DMA_BIT_MASK(32);
2578		-
2579		- if (sizeof(dma_addr_t) > 4) {
2580		- const uint64_t required_mask =
2581		- dma_get_required_mask(&pdev->dev);
2582		- if ((required_mask > DMA_BIT_MASK(32)) &&
2583		- !pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_mask)) &&
2584		- !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
2585		- ioc->base_add_sg_single = &_base_add_sg_single_64;
2586		- ioc->sge_size = sizeof(Mpi2SGESimple64_t);
2587		- ioc->dma_mask = dma_mask;
2588		- goto out;
2589		- }
2590		- }
2591		-
2592		- try_32bit:
2593		- if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
2594		- && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
2595		- ioc->base_add_sg_single = &_base_add_sg_single_32;
2596		- ioc->sge_size = sizeof(Mpi2SGESimple32_t);
	2826	+ if (ioc->is_mcpu_endpoint \|\|
	2827	+ sizeof(dma_addr_t) == 4 \|\| ioc->use_32bit_dma \|\|
	2828	+ dma_get_required_mask(&pdev->dev) <= DMA_BIT_MASK(32))
2597	2829	ioc->dma_mask = 32;
2598		- } else
	2830	+ /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
	2831	+ else if (ioc->hba_mpi_version_belonged > MPI2_VERSION)
	2832	+ ioc->dma_mask = 63;
	2833	+ else
	2834	+ ioc->dma_mask = 64;
	2835	+
	2836	+ if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask)) \|\|
	2837	+ dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask)))
2599	2838	return -ENODEV;
2600	2839
2601		- out:
2602		- si_meminfo(&s);
2603		- pr_info(MPT3SAS_FMT
2604		- "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
2605		- ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
2606		-
2607		- return 0;
2608		-}
2609		-
2610		-static int
2611		-_base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
2612		- struct pci_dev *pdev)
2613		-{
2614		- if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(ioc->dma_mask))) {
2615		- if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2616		- return -ENODEV;
	2840	+ if (ioc->dma_mask > 32) {
	2841	+ ioc->base_add_sg_single = &_base_add_sg_single_64;
	2842	+ ioc->sge_size = sizeof(Mpi2SGESimple64_t);
	2843	+ } else {
	2844	+ ioc->base_add_sg_single = &_base_add_sg_single_32;
	2845	+ ioc->sge_size = sizeof(Mpi2SGESimple32_t);
2617	2846	}
	2847	+
	2848	+ si_meminfo(&s);
	2849	+ ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
	2850	+ ioc->dma_mask, convert_to_kb(s.totalram));
	2851	+
2618	2852	return 0;
2619	2853	}
2620	2854
..	..	@@ -2641,8 +2875,7 @@
2641	2875
2642	2876	base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
2643	2877	if (!base) {
2644		- dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
2645		- ioc->name));
	2878	+ dfailprintk(ioc, ioc_info(ioc, "msix not supported\n"));
2646	2879	return -EINVAL;
2647	2880	}
2648	2881
..	..	@@ -2660,9 +2893,8 @@
2660	2893	pci_read_config_word(ioc->pdev, base + 2, &message_control);
2661	2894	ioc->msix_vector_count = (message_control & 0x3FF) + 1;
2662	2895	}
2663		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
2664		- "msix is supported, vector_count(%d)\n",
2665		- ioc->name, ioc->msix_vector_count));
	2896	+ dinitprintk(ioc, ioc_info(ioc, "msix is supported, vector_count(%d)\n",
	2897	+ ioc->msix_vector_count));
2666	2898	return 0;
2667	2899	}
2668	2900
..	..	@@ -2682,6 +2914,9 @@
2682	2914
2683	2915	list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
2684	2916	list_del(&reply_q->list);
	2917	+ if (ioc->smp_affinity_enable)
	2918	+ irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
	2919	+ reply_q->msix_index), NULL);
2685	2920	free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index),
2686	2921	reply_q);
2687	2922	kfree(reply_q);
..	..	@@ -2704,8 +2939,8 @@
2704	2939
2705	2940	reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
2706	2941	if (!reply_q) {
2707		- pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
2708		- ioc->name, (int)sizeof(struct adapter_reply_queue));
	2942	+ ioc_err(ioc, "unable to allocate memory %zu!\n",
	2943	+ sizeof(struct adapter_reply_queue));
2709	2944	return -ENOMEM;
2710	2945	}
2711	2946	reply_q->ioc = ioc;
..	..	@@ -2721,7 +2956,7 @@
2721	2956	r = request_irq(pci_irq_vector(pdev, index), _base_interrupt,
2722	2957	IRQF_SHARED, reply_q->name, reply_q);
2723	2958	if (r) {
2724		- pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
	2959	+ pr_err("%s: unable to allocate interrupt %d!\n",
2725	2960	reply_q->name, pci_irq_vector(pdev, index));
2726	2961	kfree(reply_q);
2727	2962	return -EBUSY;
..	..	@@ -2746,8 +2981,12 @@
2746	2981	{
2747	2982	unsigned int cpu, nr_cpus, nr_msix, index = 0;
2748	2983	struct adapter_reply_queue *reply_q;
	2984	+ int local_numa_node;
2749	2985
2750	2986	if (!_base_is_controller_msix_enabled(ioc))
	2987	+ return;
	2988	+
	2989	+ if (ioc->msix_load_balance)
2751	2990	return;
2752	2991
2753	2992	memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
..	..	@@ -2758,14 +2997,33 @@
2758	2997	if (!nr_msix)
2759	2998	return;
2760	2999
2761		- if (smp_affinity_enable) {
	3000	+ if (ioc->smp_affinity_enable) {
	3001	+
	3002	+ /*
	3003	+ * set irq affinity to local numa node for those irqs
	3004	+ * corresponding to high iops queues.
	3005	+ */
	3006	+ if (ioc->high_iops_queues) {
	3007	+ local_numa_node = dev_to_node(&ioc->pdev->dev);
	3008	+ for (index = 0; index < ioc->high_iops_queues;
	3009	+ index++) {
	3010	+ irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
	3011	+ index), cpumask_of_node(local_numa_node));
	3012	+ }
	3013	+ }
	3014	+
2762	3015	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
2763		- const cpumask_t *mask = pci_irq_get_affinity(ioc->pdev,
2764		- reply_q->msix_index);
2765		- if (!mask) {
2766		- pr_warn(MPT3SAS_FMT "no affinity for msi %x\n",
2767		- ioc->name, reply_q->msix_index);
	3016	+ const cpumask_t *mask;
	3017	+
	3018	+ if (reply_q->msix_index < ioc->high_iops_queues)
2768	3019	continue;
	3020	+
	3021	+ mask = pci_irq_get_affinity(ioc->pdev,
	3022	+ reply_q->msix_index);
	3023	+ if (!mask) {
	3024	+ ioc_warn(ioc, "no affinity for msi %x\n",
	3025	+ reply_q->msix_index);
	3026	+ goto fall_back;
2769	3027	}
2770	3028
2771	3029	for_each_cpu_and(cpu, mask, cpu_online_mask) {
..	..	@@ -2776,11 +3034,17 @@
2776	3034	}
2777	3035	return;
2778	3036	}
	3037	+
	3038	+fall_back:
2779	3039	cpu = cpumask_first(cpu_online_mask);
	3040	+ nr_msix -= ioc->high_iops_queues;
	3041	+ index = 0;
2780	3042
2781	3043	list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
2782		-
2783	3044	unsigned int i, group = nr_cpus / nr_msix;
	3045	+
	3046	+ if (reply_q->msix_index < ioc->high_iops_queues)
	3047	+ continue;
2784	3048
2785	3049	if (cpu >= nr_cpus)
2786	3050	break;
..	..	@@ -2797,6 +3061,52 @@
2797	3061	}
2798	3062
2799	3063	/**
	3064	+ * _base_check_and_enable_high_iops_queues - enable high iops mode
	3065	+ * @ioc: per adapter object
	3066	+ * @hba_msix_vector_count: msix vectors supported by HBA
	3067	+ *
	3068	+ * Enable high iops queues only if
	3069	+ * - HBA is a SEA/AERO controller and
	3070	+ * - MSI-Xs vector supported by the HBA is 128 and
	3071	+ * - total CPU count in the system >=16 and
	3072	+ * - loaded driver with default max_msix_vectors module parameter and
	3073	+ * - system booted in non kdump mode
	3074	+ *
	3075	+ * returns nothing.
	3076	+ */
	3077	+static void
	3078	+_base_check_and_enable_high_iops_queues(struct MPT3SAS_ADAPTER *ioc,
	3079	+ int hba_msix_vector_count)
	3080	+{
	3081	+ u16 lnksta, speed;
	3082	+
	3083	+ if (perf_mode == MPT_PERF_MODE_IOPS \|\|
	3084	+ perf_mode == MPT_PERF_MODE_LATENCY) {
	3085	+ ioc->high_iops_queues = 0;
	3086	+ return;
	3087	+ }
	3088	+
	3089	+ if (perf_mode == MPT_PERF_MODE_DEFAULT) {
	3090	+
	3091	+ pcie_capability_read_word(ioc->pdev, PCI_EXP_LNKSTA, &lnksta);
	3092	+ speed = lnksta & PCI_EXP_LNKSTA_CLS;
	3093	+
	3094	+ if (speed < 0x4) {
	3095	+ ioc->high_iops_queues = 0;
	3096	+ return;
	3097	+ }
	3098	+ }
	3099	+
	3100	+ if (!reset_devices && ioc->is_aero_ioc &&
	3101	+ hba_msix_vector_count == MPT3SAS_GEN35_MAX_MSIX_QUEUES &&
	3102	+ num_online_cpus() >= MPT3SAS_HIGH_IOPS_REPLY_QUEUES &&
	3103	+ max_msix_vectors == -1)
	3104	+ ioc->high_iops_queues = MPT3SAS_HIGH_IOPS_REPLY_QUEUES;
	3105	+ else
	3106	+ ioc->high_iops_queues = 0;
	3107	+}
	3108	+
	3109	+/**
2800	3110	* _base_disable_msix - disables msix
2801	3111	* @ioc: per adapter object
2802	3112	*
..	..	@@ -2806,8 +3116,35 @@
2806	3116	{
2807	3117	if (!ioc->msix_enable)
2808	3118	return;
2809		- pci_disable_msix(ioc->pdev);
	3119	+ pci_free_irq_vectors(ioc->pdev);
2810	3120	ioc->msix_enable = 0;
	3121	+}
	3122	+
	3123	+/**
	3124	+ * _base_alloc_irq_vectors - allocate msix vectors
	3125	+ * @ioc: per adapter object
	3126	+ *
	3127	+ */
	3128	+static int
	3129	+_base_alloc_irq_vectors(struct MPT3SAS_ADAPTER *ioc)
	3130	+{
	3131	+ int i, irq_flags = PCI_IRQ_MSIX;
	3132	+ struct irq_affinity desc = { .pre_vectors = ioc->high_iops_queues };
	3133	+ struct irq_affinity *descp = &desc;
	3134	+
	3135	+ if (ioc->smp_affinity_enable)
	3136	+ irq_flags \|= PCI_IRQ_AFFINITY;
	3137	+ else
	3138	+ descp = NULL;
	3139	+
	3140	+ ioc_info(ioc, " %d %d\n", ioc->high_iops_queues,
	3141	+ ioc->reply_queue_count);
	3142	+
	3143	+ i = pci_alloc_irq_vectors_affinity(ioc->pdev,
	3144	+ ioc->high_iops_queues,
	3145	+ ioc->reply_queue_count, irq_flags, descp);
	3146	+
	3147	+ return i;
2811	3148	}
2812	3149
2813	3150	/**
..	..	@@ -2821,7 +3158,8 @@
2821	3158	int r;
2822	3159	int i, local_max_msix_vectors;
2823	3160	u8 try_msix = 0;
2824		- unsigned int irq_flags = PCI_IRQ_MSIX;
	3161	+
	3162	+ ioc->msix_load_balance = false;
2825	3163
2826	3164	if (msix_disable == -1 \|\| msix_disable == 0)
2827	3165	try_msix = 1;
..	..	@@ -2832,12 +3170,15 @@
2832	3170	if (_base_check_enable_msix(ioc) != 0)
2833	3171	goto try_ioapic;
2834	3172
2835		- ioc->reply_queue_count = min_t(int, ioc->cpu_count,
	3173	+ ioc_info(ioc, "MSI-X vectors supported: %d\n", ioc->msix_vector_count);
	3174	+ pr_info("\t no of cores: %d, max_msix_vectors: %d\n",
	3175	+ ioc->cpu_count, max_msix_vectors);
	3176	+ if (ioc->is_aero_ioc)
	3177	+ _base_check_and_enable_high_iops_queues(ioc,
	3178	+ ioc->msix_vector_count);
	3179	+ ioc->reply_queue_count =
	3180	+ min_t(int, ioc->cpu_count + ioc->high_iops_queues,
2836	3181	ioc->msix_vector_count);
2837		-
2838		- printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
2839		- ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
2840		- ioc->cpu_count, max_msix_vectors);
2841	3182
2842	3183	if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
2843	3184	local_max_msix_vectors = (reset_devices) ? 1 : 8;
..	..	@@ -2850,18 +3191,27 @@
2850	3191	else if (local_max_msix_vectors == 0)
2851	3192	goto try_ioapic;
2852	3193
2853		- if (ioc->msix_vector_count < ioc->cpu_count)
2854		- smp_affinity_enable = 0;
	3194	+ /*
	3195	+ * Enable msix_load_balance only if combined reply queue mode is
	3196	+ * disabled on SAS3 & above generation HBA devices.
	3197	+ */
	3198	+ if (!ioc->combined_reply_queue &&
	3199	+ ioc->hba_mpi_version_belonged != MPI2_VERSION) {
	3200	+ ioc_info(ioc,
	3201	+ "combined ReplyQueue is off, Enabling msix load balance\n");
	3202	+ ioc->msix_load_balance = true;
	3203	+ }
2855	3204
2856		- if (smp_affinity_enable)
2857		- irq_flags \|= PCI_IRQ_AFFINITY;
	3205	+ /*
	3206	+ * smp affinity setting is not need when msix load balance
	3207	+ * is enabled.
	3208	+ */
	3209	+ if (ioc->msix_load_balance)
	3210	+ ioc->smp_affinity_enable = 0;
2858	3211
2859		- r = pci_alloc_irq_vectors(ioc->pdev, 1, ioc->reply_queue_count,
2860		- irq_flags);
	3212	+ r = _base_alloc_irq_vectors(ioc);
2861	3213	if (r < 0) {
2862		- dfailprintk(ioc, pr_info(MPT3SAS_FMT
2863		- "pci_alloc_irq_vectors failed (r=%d) !!!\n",
2864		- ioc->name, r));
	3214	+ ioc_info(ioc, "pci_alloc_irq_vectors failed (r=%d) !!!\n", r);
2865	3215	goto try_ioapic;
2866	3216	}
2867	3217
..	..	@@ -2876,17 +3226,21 @@
2876	3226	}
2877	3227	}
2878	3228
	3229	+ ioc_info(ioc, "High IOPs queues : %s\n",
	3230	+ ioc->high_iops_queues ? "enabled" : "disabled");
	3231	+
2879	3232	return 0;
2880	3233
2881	3234	/* failback to io_apic interrupt routing */
2882	3235	try_ioapic:
2883		-
	3236	+ ioc->high_iops_queues = 0;
	3237	+ ioc_info(ioc, "High IOPs queues : disabled\n");
2884	3238	ioc->reply_queue_count = 1;
2885	3239	r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY);
2886	3240	if (r < 0) {
2887		- dfailprintk(ioc, pr_info(MPT3SAS_FMT
2888		- "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n",
2889		- ioc->name, r));
	3241	+ dfailprintk(ioc,
	3242	+ ioc_info(ioc, "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n",
	3243	+ r));
2890	3244	} else
2891	3245	r = _base_request_irq(ioc, 0);
2892	3246
..	..	@@ -2902,8 +3256,7 @@
2902	3256	{
2903	3257	struct pci_dev *pdev = ioc->pdev;
2904	3258
2905		- dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n",
2906		- ioc->name, __func__));
	3259	+ dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
2907	3260
2908	3261	_base_free_irq(ioc);
2909	3262	_base_disable_msix(ioc);
..	..	@@ -2924,6 +3277,43 @@
2924	3277	}
2925	3278	}
2926	3279
	3280	+static int
	3281	+_base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
	3282	+
	3283	+/**
	3284	+ * _base_check_for_fault_and_issue_reset - check if IOC is in fault state
	3285	+ * and if it is in fault state then issue diag reset.
	3286	+ * @ioc: per adapter object
	3287	+ *
	3288	+ * Returns: 0 for success, non-zero for failure.
	3289	+ */
	3290	+static int
	3291	+_base_check_for_fault_and_issue_reset(struct MPT3SAS_ADAPTER *ioc)
	3292	+{
	3293	+ u32 ioc_state;
	3294	+ int rc = -EFAULT;
	3295	+
	3296	+ dinitprintk(ioc, pr_info("%s\n", __func__));
	3297	+ if (ioc->pci_error_recovery)
	3298	+ return 0;
	3299	+ ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
	3300	+ dhsprintk(ioc, pr_info("%s: ioc_state(0x%08x)\n", __func__, ioc_state));
	3301	+
	3302	+ if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
	3303	+ mpt3sas_print_fault_code(ioc, ioc_state &
	3304	+ MPI2_DOORBELL_DATA_MASK);
	3305	+ rc = _base_diag_reset(ioc);
	3306	+ } else if ((ioc_state & MPI2_IOC_STATE_MASK) ==
	3307	+ MPI2_IOC_STATE_COREDUMP) {
	3308	+ mpt3sas_print_coredump_info(ioc, ioc_state &
	3309	+ MPI2_DOORBELL_DATA_MASK);
	3310	+ mpt3sas_base_wait_for_coredump_completion(ioc, __func__);
	3311	+ rc = _base_diag_reset(ioc);
	3312	+ }
	3313	+
	3314	+ return rc;
	3315	+}
	3316	+
2927	3317	/**
2928	3318	* mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
2929	3319	* @ioc: per adapter object
..	..	@@ -2936,18 +3326,16 @@
2936	3326	struct pci_dev *pdev = ioc->pdev;
2937	3327	u32 memap_sz;
2938	3328	u32 pio_sz;
2939		- int i, r = 0;
	3329	+ int i, r = 0, rc;
2940	3330	u64 pio_chip = 0;
2941	3331	phys_addr_t chip_phys = 0;
2942	3332	struct adapter_reply_queue *reply_q;
2943	3333
2944		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
2945		- ioc->name, __func__));
	3334	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
2946	3335
2947	3336	ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
2948	3337	if (pci_enable_device_mem(pdev)) {
2949		- pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
2950		- ioc->name);
	3338	+ ioc_warn(ioc, "pci_enable_device_mem: failed\n");
2951	3339	ioc->bars = 0;
2952	3340	return -ENODEV;
2953	3341	}
..	..	@@ -2955,8 +3343,7 @@
2955	3343
2956	3344	if (pci_request_selected_regions(pdev, ioc->bars,
2957	3345	ioc->driver_name)) {
2958		- pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
2959		- ioc->name);
	3346	+ ioc_warn(ioc, "pci_request_selected_regions: failed\n");
2960	3347	ioc->bars = 0;
2961	3348	r = -ENODEV;
2962	3349	goto out_fail;
..	..	@@ -2969,8 +3356,7 @@
2969	3356
2970	3357
2971	3358	if (_base_config_dma_addressing(ioc, pdev) != 0) {
2972		- pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
2973		- ioc->name, pci_name(pdev));
	3359	+ ioc_warn(ioc, "no suitable DMA mask for %s\n", pci_name(pdev));
2974	3360	r = -ENODEV;
2975	3361	goto out_fail;
2976	3362	}
..	..	@@ -2993,17 +3379,20 @@
2993	3379	}
2994	3380
2995	3381	if (ioc->chip == NULL) {
2996		- pr_err(MPT3SAS_FMT "unable to map adapter memory! "
2997		- " or resource not found\n", ioc->name);
	3382	+ ioc_err(ioc,
	3383	+ "unable to map adapter memory! or resource not found\n");
2998	3384	r = -EINVAL;
2999	3385	goto out_fail;
3000	3386	}
3001	3387
3002		- _base_mask_interrupts(ioc);
	3388	+ mpt3sas_base_mask_interrupts(ioc);
3003	3389
3004	3390	r = _base_get_ioc_facts(ioc);
3005		- if (r)
3006		- goto out_fail;
	3391	+ if (r) {
	3392	+ rc = _base_check_for_fault_and_issue_reset(ioc);
	3393	+ if (rc \|\| (_base_get_ioc_facts(ioc)))
	3394	+ goto out_fail;
	3395	+ }
3007	3396
3008	3397	if (!ioc->rdpq_array_enable_assigned) {
3009	3398	ioc->rdpq_array_enable = ioc->rdpq_array_capable;
..	..	@@ -3014,6 +3403,8 @@
3014	3403	if (r)
3015	3404	goto out_fail;
3016	3405
	3406	+ if (!ioc->is_driver_loading)
	3407	+ _base_init_irqpolls(ioc);
3017	3408	/* Use the Combined reply queue feature only for SAS3 C0 & higher
3018	3409	* revision HBAs and also only when reply queue count is greater than 8
3019	3410	*/
..	..	@@ -3028,9 +3419,8 @@
3028	3419	ioc->combined_reply_index_count,
3029	3420	sizeof(resource_size_t *), GFP_KERNEL);
3030	3421	if (!ioc->replyPostRegisterIndex) {
3031		- dfailprintk(ioc, printk(MPT3SAS_FMT
3032		- "allocation for reply Post Register Index failed!!!\n",
3033		- ioc->name));
	3422	+ ioc_err(ioc,
	3423	+ "allocation for replyPostRegisterIndex failed!\n");
3034	3424	r = -ENOMEM;
3035	3425	goto out_fail;
3036	3426	}
..	..	@@ -3055,15 +3445,15 @@
3055	3445	}
3056	3446
3057	3447	list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
3058		- pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
3059		- reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
3060		- "IO-APIC enabled"),
3061		- pci_irq_vector(ioc->pdev, reply_q->msix_index));
	3448	+ pr_info("%s: %s enabled: IRQ %d\n",
	3449	+ reply_q->name,
	3450	+ ioc->msix_enable ? "PCI-MSI-X" : "IO-APIC",
	3451	+ pci_irq_vector(ioc->pdev, reply_q->msix_index));
3062	3452
3063		- pr_info(MPT3SAS_FMT "iomem(%pap), mapped(0x%p), size(%d)\n",
3064		- ioc->name, &chip_phys, ioc->chip, memap_sz);
3065		- pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
3066		- ioc->name, (unsigned long long)pio_chip, pio_sz);
	3453	+ ioc_info(ioc, "iomem(%pap), mapped(0x%p), size(%d)\n",
	3454	+ &chip_phys, ioc->chip, memap_sz);
	3455	+ ioc_info(ioc, "ioport(0x%016llx), size(%d)\n",
	3456	+ (unsigned long long)pio_chip, pio_sz);
3067	3457
3068	3458	/* Save PCI configuration state for recovery from PCI AER/EEH errors */
3069	3459	pci_save_state(pdev);
..	..	@@ -3155,10 +3545,71 @@
3155	3545	return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
3156	3546	}
3157	3547
	3548	+/**
	3549	+ * _base_get_msix_index - get the msix index
	3550	+ * @ioc: per adapter object
	3551	+ * @scmd: scsi_cmnd object
	3552	+ *
	3553	+ * returns msix index of general reply queues,
	3554	+ * i.e. reply queue on which IO request's reply
	3555	+ * should be posted by the HBA firmware.
	3556	+ */
3158	3557	static inline u8
3159		-_base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
	3558	+_base_get_msix_index(struct MPT3SAS_ADAPTER *ioc,
	3559	+ struct scsi_cmnd *scmd)
3160	3560	{
	3561	+ /* Enables reply_queue load balancing */
	3562	+ if (ioc->msix_load_balance)
	3563	+ return ioc->reply_queue_count ?
	3564	+ base_mod64(atomic64_add_return(1,
	3565	+ &ioc->total_io_cnt), ioc->reply_queue_count) : 0;
	3566	+
3161	3567	return ioc->cpu_msix_table[raw_smp_processor_id()];
	3568	+}
	3569	+
	3570	+/**
	3571	+ * _base_sdev_nr_inflight_request -get number of inflight requests
	3572	+ * of a request queue.
	3573	+ * @q: request_queue object
	3574	+ *
	3575	+ * returns number of inflight request of a request queue.
	3576	+ */
	3577	+inline unsigned long
	3578	+_base_sdev_nr_inflight_request(struct request_queue *q)
	3579	+{
	3580	+ struct blk_mq_hw_ctx *hctx = q->queue_hw_ctx[0];
	3581	+
	3582	+ return atomic_read(&hctx->nr_active);
	3583	+}
	3584	+
	3585	+
	3586	+/**
	3587	+ * _base_get_high_iops_msix_index - get the msix index of
	3588	+ * high iops queues
	3589	+ * @ioc: per adapter object
	3590	+ * @scmd: scsi_cmnd object
	3591	+ *
	3592	+ * Returns: msix index of high iops reply queues.
	3593	+ * i.e. high iops reply queue on which IO request's
	3594	+ * reply should be posted by the HBA firmware.
	3595	+ */
	3596	+static inline u8
	3597	+_base_get_high_iops_msix_index(struct MPT3SAS_ADAPTER *ioc,
	3598	+ struct scsi_cmnd *scmd)
	3599	+{
	3600	+ /**
	3601	+ * Round robin the IO interrupts among the high iops
	3602	+ * reply queues in terms of batch count 16 when outstanding
	3603	+ * IOs on the target device is >=8.
	3604	+ */
	3605	+ if (_base_sdev_nr_inflight_request(scmd->device->request_queue) >
	3606	+ MPT3SAS_DEVICE_HIGH_IOPS_DEPTH)
	3607	+ return base_mod64((
	3608	+ atomic64_add_return(1, &ioc->high_iops_outstanding) /
	3609	+ MPT3SAS_HIGH_IOPS_BATCH_COUNT),
	3610	+ MPT3SAS_HIGH_IOPS_REPLY_QUEUES);
	3611	+
	3612	+ return _base_get_msix_index(ioc, scmd);
3162	3613	}
3163	3614
3164	3615	/**
..	..	@@ -3178,8 +3629,7 @@
3178	3629	spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3179	3630	if (list_empty(&ioc->internal_free_list)) {
3180	3631	spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3181		- pr_err(MPT3SAS_FMT "%s: smid not available\n",
3182		- ioc->name, __func__);
	3632	+ ioc_err(ioc, "%s: smid not available\n", __func__);
3183	3633	return 0;
3184	3634	}
3185	3635
..	..	@@ -3210,8 +3660,8 @@
3210	3660
3211	3661	smid = tag + 1;
3212	3662	request->cb_idx = cb_idx;
3213		- request->msix_io = _base_get_msix_index(ioc);
3214	3663	request->smid = smid;
	3664	+ request->scmd = scmd;
3215	3665	INIT_LIST_HEAD(&request->chain_list);
3216	3666	return smid;
3217	3667	}
..	..	@@ -3265,6 +3715,7 @@
3265	3715	return;
3266	3716	st->cb_idx = 0xFF;
3267	3717	st->direct_io = 0;
	3718	+ st->scmd = NULL;
3268	3719	atomic_set(&ioc->chain_lookup[st->smid - 1].chain_offset, 0);
3269	3720	st->smid = 0;
3270	3721	}
..	..	@@ -3334,7 +3785,6 @@
3334	3785	spin_lock_irqsave(writeq_lock, flags);
3335	3786	__raw_writel((u32)(b), addr);
3336	3787	__raw_writel((u32)(b >> 32), (addr + 4));
3337		- mmiowb();
3338	3788	spin_unlock_irqrestore(writeq_lock, flags);
3339	3789	}
3340	3790
..	..	@@ -3365,13 +3815,37 @@
3365	3815	#endif
3366	3816
3367	3817	/**
	3818	+ * _base_set_and_get_msix_index - get the msix index and assign to msix_io
	3819	+ * variable of scsi tracker
	3820	+ * @ioc: per adapter object
	3821	+ * @smid: system request message index
	3822	+ *
	3823	+ * returns msix index.
	3824	+ */
	3825	+static u8
	3826	+_base_set_and_get_msix_index(struct MPT3SAS_ADAPTER *ioc, u16 smid)
	3827	+{
	3828	+ struct scsiio_tracker *st = NULL;
	3829	+
	3830	+ if (smid < ioc->hi_priority_smid)
	3831	+ st = _get_st_from_smid(ioc, smid);
	3832	+
	3833	+ if (st == NULL)
	3834	+ return _base_get_msix_index(ioc, NULL);
	3835	+
	3836	+ st->msix_io = ioc->get_msix_index_for_smlio(ioc, st->scmd);
	3837	+ return st->msix_io;
	3838	+}
	3839	+
	3840	+/**
3368	3841	* _base_put_smid_mpi_ep_scsi_io - send SCSI_IO request to firmware
3369	3842	* @ioc: per adapter object
3370	3843	* @smid: system request message index
3371	3844	* @handle: device handle
3372	3845	*/
3373	3846	static void
3374		-_base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
	3847	+_base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc,
	3848	+ u16 smid, u16 handle)
3375	3849	{
3376	3850	Mpi2RequestDescriptorUnion_t descriptor;
3377	3851	u64 request = (u64 )&descriptor;
..	..	@@ -3384,7 +3858,7 @@
3384	3858	_base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
3385	3859	ioc->request_sz);
3386	3860	descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
3387		- descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
	3861	+ descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
3388	3862	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3389	3863	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3390	3864	descriptor.SCSIIO.LMID = 0;
..	..	@@ -3406,7 +3880,7 @@
3406	3880
3407	3881
3408	3882	descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
3409		- descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
	3883	+ descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
3410	3884	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3411	3885	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3412	3886	descriptor.SCSIIO.LMID = 0;
..	..	@@ -3415,13 +3889,13 @@
3415	3889	}
3416	3890
3417	3891	/**
3418		- * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
	3892	+ * _base_put_smid_fast_path - send fast path request to firmware
3419	3893	* @ioc: per adapter object
3420	3894	* @smid: system request message index
3421	3895	* @handle: device handle
3422	3896	*/
3423		-void
3424		-mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
	3897	+static void
	3898	+_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
3425	3899	u16 handle)
3426	3900	{
3427	3901	Mpi2RequestDescriptorUnion_t descriptor;
..	..	@@ -3429,7 +3903,7 @@
3429	3903
3430	3904	descriptor.SCSIIO.RequestFlags =
3431	3905	MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
3432		- descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
	3906	+ descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
3433	3907	descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3434	3908	descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3435	3909	descriptor.SCSIIO.LMID = 0;
..	..	@@ -3438,13 +3912,13 @@
3438	3912	}
3439	3913
3440	3914	/**
3441		- * mpt3sas_base_put_smid_hi_priority - send Task Management request to firmware
	3915	+ * _base_put_smid_hi_priority - send Task Management request to firmware
3442	3916	* @ioc: per adapter object
3443	3917	* @smid: system request message index
3444	3918	* @msix_task: msix_task will be same as msix of IO incase of task abort else 0.
3445	3919	*/
3446		-void
3447		-mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
	3920	+static void
	3921	+_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
3448	3922	u16 msix_task)
3449	3923	{
3450	3924	Mpi2RequestDescriptorUnion_t descriptor;
..	..	@@ -3493,7 +3967,7 @@
3493	3967
3494	3968	descriptor.Default.RequestFlags =
3495	3969	MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED;
3496		- descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
	3970	+ descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
3497	3971	descriptor.Default.SMID = cpu_to_le16(smid);
3498	3972	descriptor.Default.LMID = 0;
3499	3973	descriptor.Default.DescriptorTypeDependent = 0;
..	..	@@ -3502,12 +3976,12 @@
3502	3976	}
3503	3977
3504	3978	/**
3505		- * mpt3sas_base_put_smid_default - Default, primarily used for config pages
	3979	+ * _base_put_smid_default - Default, primarily used for config pages
3506	3980	* @ioc: per adapter object
3507	3981	* @smid: system request message index
3508	3982	*/
3509		-void
3510		-mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
	3983	+static void
	3984	+_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3511	3985	{
3512	3986	Mpi2RequestDescriptorUnion_t descriptor;
3513	3987	void *mpi_req_iomem;
..	..	@@ -3525,7 +3999,7 @@
3525	3999	}
3526	4000	request = (u64 *)&descriptor;
3527	4001	descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
3528		- descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
	4002	+ descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
3529	4003	descriptor.Default.SMID = cpu_to_le16(smid);
3530	4004	descriptor.Default.LMID = 0;
3531	4005	descriptor.Default.DescriptorTypeDependent = 0;
..	..	@@ -3536,6 +4010,95 @@
3536	4010	else
3537	4011	_base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3538	4012	&ioc->scsi_lookup_lock);
	4013	+}
	4014	+
	4015	+/**
	4016	+ * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using
	4017	+ * Atomic Request Descriptor
	4018	+ * @ioc: per adapter object
	4019	+ * @smid: system request message index
	4020	+ * @handle: device handle, unused in this function, for function type match
	4021	+ *
	4022	+ * Return nothing.
	4023	+ */
	4024	+static void
	4025	+_base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
	4026	+ u16 handle)
	4027	+{
	4028	+ Mpi26AtomicRequestDescriptor_t descriptor;
	4029	+ u32 request = (u32 )&descriptor;
	4030	+
	4031	+ descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
	4032	+ descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
	4033	+ descriptor.SMID = cpu_to_le16(smid);
	4034	+
	4035	+ writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
	4036	+}
	4037	+
	4038	+/**
	4039	+ * _base_put_smid_fast_path_atomic - send fast path request to firmware
	4040	+ * using Atomic Request Descriptor
	4041	+ * @ioc: per adapter object
	4042	+ * @smid: system request message index
	4043	+ * @handle: device handle, unused in this function, for function type match
	4044	+ * Return nothing
	4045	+ */
	4046	+static void
	4047	+_base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
	4048	+ u16 handle)
	4049	+{
	4050	+ Mpi26AtomicRequestDescriptor_t descriptor;
	4051	+ u32 request = (u32 )&descriptor;
	4052	+
	4053	+ descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
	4054	+ descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
	4055	+ descriptor.SMID = cpu_to_le16(smid);
	4056	+
	4057	+ writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
	4058	+}
	4059	+
	4060	+/**
	4061	+ * _base_put_smid_hi_priority_atomic - send Task Management request to
	4062	+ * firmware using Atomic Request Descriptor
	4063	+ * @ioc: per adapter object
	4064	+ * @smid: system request message index
	4065	+ * @msix_task: msix_task will be same as msix of IO incase of task abort else 0
	4066	+ *
	4067	+ * Return nothing.
	4068	+ */
	4069	+static void
	4070	+_base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
	4071	+ u16 msix_task)
	4072	+{
	4073	+ Mpi26AtomicRequestDescriptor_t descriptor;
	4074	+ u32 request = (u32 )&descriptor;
	4075	+
	4076	+ descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
	4077	+ descriptor.MSIxIndex = msix_task;
	4078	+ descriptor.SMID = cpu_to_le16(smid);
	4079	+
	4080	+ writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
	4081	+}
	4082	+
	4083	+/**
	4084	+ * _base_put_smid_default - Default, primarily used for config pages
	4085	+ * use Atomic Request Descriptor
	4086	+ * @ioc: per adapter object
	4087	+ * @smid: system request message index
	4088	+ *
	4089	+ * Return nothing.
	4090	+ */
	4091	+static void
	4092	+_base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid)
	4093	+{
	4094	+ Mpi26AtomicRequestDescriptor_t descriptor;
	4095	+ u32 request = (u32 )&descriptor;
	4096	+
	4097	+ descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
	4098	+ descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
	4099	+ descriptor.SMID = cpu_to_le16(smid);
	4100	+
	4101	+ writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
3539	4102	}
3540	4103
3541	4104	/**
..	..	@@ -3554,89 +4117,87 @@
3554	4117	case MPI2_MFGPAGE_DEVID_SAS2008:
3555	4118	switch (ioc->pdev->subsystem_device) {
3556	4119	case MPT2SAS_INTEL_RMS2LL080_SSDID:
3557		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3558		- MPT2SAS_INTEL_RMS2LL080_BRANDING);
	4120	+ ioc_info(ioc, "%s\n",
	4121	+ MPT2SAS_INTEL_RMS2LL080_BRANDING);
3559	4122	break;
3560	4123	case MPT2SAS_INTEL_RMS2LL040_SSDID:
3561		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3562		- MPT2SAS_INTEL_RMS2LL040_BRANDING);
	4124	+ ioc_info(ioc, "%s\n",
	4125	+ MPT2SAS_INTEL_RMS2LL040_BRANDING);
3563	4126	break;
3564	4127	case MPT2SAS_INTEL_SSD910_SSDID:
3565		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3566		- MPT2SAS_INTEL_SSD910_BRANDING);
	4128	+ ioc_info(ioc, "%s\n",
	4129	+ MPT2SAS_INTEL_SSD910_BRANDING);
3567	4130	break;
3568	4131	default:
3569		- pr_info(MPT3SAS_FMT
3570		- "Intel(R) Controller: Subsystem ID: 0x%X\n",
3571		- ioc->name, ioc->pdev->subsystem_device);
	4132	+ ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
	4133	+ ioc->pdev->subsystem_device);
3572	4134	break;
3573	4135	}
	4136	+ break;
3574	4137	case MPI2_MFGPAGE_DEVID_SAS2308_2:
3575	4138	switch (ioc->pdev->subsystem_device) {
3576	4139	case MPT2SAS_INTEL_RS25GB008_SSDID:
3577		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3578		- MPT2SAS_INTEL_RS25GB008_BRANDING);
	4140	+ ioc_info(ioc, "%s\n",
	4141	+ MPT2SAS_INTEL_RS25GB008_BRANDING);
3579	4142	break;
3580	4143	case MPT2SAS_INTEL_RMS25JB080_SSDID:
3581		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3582		- MPT2SAS_INTEL_RMS25JB080_BRANDING);
	4144	+ ioc_info(ioc, "%s\n",
	4145	+ MPT2SAS_INTEL_RMS25JB080_BRANDING);
3583	4146	break;
3584	4147	case MPT2SAS_INTEL_RMS25JB040_SSDID:
3585		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3586		- MPT2SAS_INTEL_RMS25JB040_BRANDING);
	4148	+ ioc_info(ioc, "%s\n",
	4149	+ MPT2SAS_INTEL_RMS25JB040_BRANDING);
3587	4150	break;
3588	4151	case MPT2SAS_INTEL_RMS25KB080_SSDID:
3589		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3590		- MPT2SAS_INTEL_RMS25KB080_BRANDING);
	4152	+ ioc_info(ioc, "%s\n",
	4153	+ MPT2SAS_INTEL_RMS25KB080_BRANDING);
3591	4154	break;
3592	4155	case MPT2SAS_INTEL_RMS25KB040_SSDID:
3593		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3594		- MPT2SAS_INTEL_RMS25KB040_BRANDING);
	4156	+ ioc_info(ioc, "%s\n",
	4157	+ MPT2SAS_INTEL_RMS25KB040_BRANDING);
3595	4158	break;
3596	4159	case MPT2SAS_INTEL_RMS25LB040_SSDID:
3597		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3598		- MPT2SAS_INTEL_RMS25LB040_BRANDING);
	4160	+ ioc_info(ioc, "%s\n",
	4161	+ MPT2SAS_INTEL_RMS25LB040_BRANDING);
3599	4162	break;
3600	4163	case MPT2SAS_INTEL_RMS25LB080_SSDID:
3601		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3602		- MPT2SAS_INTEL_RMS25LB080_BRANDING);
	4164	+ ioc_info(ioc, "%s\n",
	4165	+ MPT2SAS_INTEL_RMS25LB080_BRANDING);
3603	4166	break;
3604	4167	default:
3605		- pr_info(MPT3SAS_FMT
3606		- "Intel(R) Controller: Subsystem ID: 0x%X\n",
3607		- ioc->name, ioc->pdev->subsystem_device);
	4168	+ ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
	4169	+ ioc->pdev->subsystem_device);
3608	4170	break;
3609	4171	}
	4172	+ break;
3610	4173	case MPI25_MFGPAGE_DEVID_SAS3008:
3611	4174	switch (ioc->pdev->subsystem_device) {
3612	4175	case MPT3SAS_INTEL_RMS3JC080_SSDID:
3613		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3614		- MPT3SAS_INTEL_RMS3JC080_BRANDING);
	4176	+ ioc_info(ioc, "%s\n",
	4177	+ MPT3SAS_INTEL_RMS3JC080_BRANDING);
3615	4178	break;
3616	4179
3617	4180	case MPT3SAS_INTEL_RS3GC008_SSDID:
3618		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3619		- MPT3SAS_INTEL_RS3GC008_BRANDING);
	4181	+ ioc_info(ioc, "%s\n",
	4182	+ MPT3SAS_INTEL_RS3GC008_BRANDING);
3620	4183	break;
3621	4184	case MPT3SAS_INTEL_RS3FC044_SSDID:
3622		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3623		- MPT3SAS_INTEL_RS3FC044_BRANDING);
	4185	+ ioc_info(ioc, "%s\n",
	4186	+ MPT3SAS_INTEL_RS3FC044_BRANDING);
3624	4187	break;
3625	4188	case MPT3SAS_INTEL_RS3UC080_SSDID:
3626		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3627		- MPT3SAS_INTEL_RS3UC080_BRANDING);
	4189	+ ioc_info(ioc, "%s\n",
	4190	+ MPT3SAS_INTEL_RS3UC080_BRANDING);
3628	4191	break;
3629	4192	default:
3630		- pr_info(MPT3SAS_FMT
3631		- "Intel(R) Controller: Subsystem ID: 0x%X\n",
3632		- ioc->name, ioc->pdev->subsystem_device);
	4193	+ ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
	4194	+ ioc->pdev->subsystem_device);
3633	4195	break;
3634	4196	}
3635	4197	break;
3636	4198	default:
3637		- pr_info(MPT3SAS_FMT
3638		- "Intel(R) Controller: Subsystem ID: 0x%X\n",
3639		- ioc->name, ioc->pdev->subsystem_device);
	4199	+ ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
	4200	+ ioc->pdev->subsystem_device);
3640	4201	break;
3641	4202	}
3642	4203	break;
..	..	@@ -3645,57 +4206,54 @@
3645	4206	case MPI2_MFGPAGE_DEVID_SAS2008:
3646	4207	switch (ioc->pdev->subsystem_device) {
3647	4208	case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
3648		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3649		- MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
	4209	+ ioc_info(ioc, "%s\n",
	4210	+ MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
3650	4211	break;
3651	4212	case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
3652		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3653		- MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
	4213	+ ioc_info(ioc, "%s\n",
	4214	+ MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
3654	4215	break;
3655	4216	case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
3656		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3657		- MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
	4217	+ ioc_info(ioc, "%s\n",
	4218	+ MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
3658	4219	break;
3659	4220	case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
3660		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3661		- MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
	4221	+ ioc_info(ioc, "%s\n",
	4222	+ MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);
3662	4223	break;
3663	4224	case MPT2SAS_DELL_PERC_H200_EMBEDDED_SSDID:
3664		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3665		- MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
	4225	+ ioc_info(ioc, "%s\n",
	4226	+ MPT2SAS_DELL_PERC_H200_EMBEDDED_BRANDING);
3666	4227	break;
3667	4228	case MPT2SAS_DELL_PERC_H200_SSDID:
3668		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3669		- MPT2SAS_DELL_PERC_H200_BRANDING);
	4229	+ ioc_info(ioc, "%s\n",
	4230	+ MPT2SAS_DELL_PERC_H200_BRANDING);
3670	4231	break;
3671	4232	case MPT2SAS_DELL_6GBPS_SAS_SSDID:
3672		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3673		- MPT2SAS_DELL_6GBPS_SAS_BRANDING);
	4233	+ ioc_info(ioc, "%s\n",
	4234	+ MPT2SAS_DELL_6GBPS_SAS_BRANDING);
3674	4235	break;
3675	4236	default:
3676		- pr_info(MPT3SAS_FMT
3677		- "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
3678		- ioc->name, ioc->pdev->subsystem_device);
	4237	+ ioc_info(ioc, "Dell 6Gbps HBA: Subsystem ID: 0x%X\n",
	4238	+ ioc->pdev->subsystem_device);
3679	4239	break;
3680	4240	}
3681	4241	break;
3682	4242	case MPI25_MFGPAGE_DEVID_SAS3008:
3683	4243	switch (ioc->pdev->subsystem_device) {
3684	4244	case MPT3SAS_DELL_12G_HBA_SSDID:
3685		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3686		- MPT3SAS_DELL_12G_HBA_BRANDING);
	4245	+ ioc_info(ioc, "%s\n",
	4246	+ MPT3SAS_DELL_12G_HBA_BRANDING);
3687	4247	break;
3688	4248	default:
3689		- pr_info(MPT3SAS_FMT
3690		- "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
3691		- ioc->name, ioc->pdev->subsystem_device);
	4249	+ ioc_info(ioc, "Dell 12Gbps HBA: Subsystem ID: 0x%X\n",
	4250	+ ioc->pdev->subsystem_device);
3692	4251	break;
3693	4252	}
3694	4253	break;
3695	4254	default:
3696		- pr_info(MPT3SAS_FMT
3697		- "Dell HBA: Subsystem ID: 0x%X\n", ioc->name,
3698		- ioc->pdev->subsystem_device);
	4255	+ ioc_info(ioc, "Dell HBA: Subsystem ID: 0x%X\n",
	4256	+ ioc->pdev->subsystem_device);
3699	4257	break;
3700	4258	}
3701	4259	break;
..	..	@@ -3704,46 +4262,42 @@
3704	4262	case MPI25_MFGPAGE_DEVID_SAS3008:
3705	4263	switch (ioc->pdev->subsystem_device) {
3706	4264	case MPT3SAS_CISCO_12G_8E_HBA_SSDID:
3707		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3708		- MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
	4265	+ ioc_info(ioc, "%s\n",
	4266	+ MPT3SAS_CISCO_12G_8E_HBA_BRANDING);
3709	4267	break;
3710	4268	case MPT3SAS_CISCO_12G_8I_HBA_SSDID:
3711		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3712		- MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
	4269	+ ioc_info(ioc, "%s\n",
	4270	+ MPT3SAS_CISCO_12G_8I_HBA_BRANDING);
3713	4271	break;
3714	4272	case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
3715		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3716		- MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
	4273	+ ioc_info(ioc, "%s\n",
	4274	+ MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
3717	4275	break;
3718	4276	default:
3719		- pr_info(MPT3SAS_FMT
3720		- "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
3721		- ioc->name, ioc->pdev->subsystem_device);
	4277	+ ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
	4278	+ ioc->pdev->subsystem_device);
3722	4279	break;
3723	4280	}
3724	4281	break;
3725	4282	case MPI25_MFGPAGE_DEVID_SAS3108_1:
3726	4283	switch (ioc->pdev->subsystem_device) {
3727	4284	case MPT3SAS_CISCO_12G_AVILA_HBA_SSDID:
3728		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3729		- MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
	4285	+ ioc_info(ioc, "%s\n",
	4286	+ MPT3SAS_CISCO_12G_AVILA_HBA_BRANDING);
3730	4287	break;
3731	4288	case MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_SSDID:
3732		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3733		- MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING
3734		- );
	4289	+ ioc_info(ioc, "%s\n",
	4290	+ MPT3SAS_CISCO_12G_COLUSA_MEZZANINE_HBA_BRANDING);
3735	4291	break;
3736	4292	default:
3737		- pr_info(MPT3SAS_FMT
3738		- "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
3739		- ioc->name, ioc->pdev->subsystem_device);
	4293	+ ioc_info(ioc, "Cisco 12Gbps SAS HBA: Subsystem ID: 0x%X\n",
	4294	+ ioc->pdev->subsystem_device);
3740	4295	break;
3741	4296	}
3742	4297	break;
3743	4298	default:
3744		- pr_info(MPT3SAS_FMT
3745		- "Cisco SAS HBA: Subsystem ID: 0x%X\n",
3746		- ioc->name, ioc->pdev->subsystem_device);
	4299	+ ioc_info(ioc, "Cisco SAS HBA: Subsystem ID: 0x%X\n",
	4300	+ ioc->pdev->subsystem_device);
3747	4301	break;
3748	4302	}
3749	4303	break;
..	..	@@ -3752,43 +4306,42 @@
3752	4306	case MPI2_MFGPAGE_DEVID_SAS2004:
3753	4307	switch (ioc->pdev->subsystem_device) {
3754	4308	case MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_SSDID:
3755		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3756		- MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
	4309	+ ioc_info(ioc, "%s\n",
	4310	+ MPT2SAS_HP_DAUGHTER_2_4_INTERNAL_BRANDING);
3757	4311	break;
3758	4312	default:
3759		- pr_info(MPT3SAS_FMT
3760		- "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
3761		- ioc->name, ioc->pdev->subsystem_device);
	4313	+ ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
	4314	+ ioc->pdev->subsystem_device);
3762	4315	break;
3763	4316	}
	4317	+ break;
3764	4318	case MPI2_MFGPAGE_DEVID_SAS2308_2:
3765	4319	switch (ioc->pdev->subsystem_device) {
3766	4320	case MPT2SAS_HP_2_4_INTERNAL_SSDID:
3767		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3768		- MPT2SAS_HP_2_4_INTERNAL_BRANDING);
	4321	+ ioc_info(ioc, "%s\n",
	4322	+ MPT2SAS_HP_2_4_INTERNAL_BRANDING);
3769	4323	break;
3770	4324	case MPT2SAS_HP_2_4_EXTERNAL_SSDID:
3771		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3772		- MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
	4325	+ ioc_info(ioc, "%s\n",
	4326	+ MPT2SAS_HP_2_4_EXTERNAL_BRANDING);
3773	4327	break;
3774	4328	case MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_SSDID:
3775		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3776		- MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
	4329	+ ioc_info(ioc, "%s\n",
	4330	+ MPT2SAS_HP_1_4_INTERNAL_1_4_EXTERNAL_BRANDING);
3777	4331	break;
3778	4332	case MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_SSDID:
3779		- pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3780		- MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
	4333	+ ioc_info(ioc, "%s\n",
	4334	+ MPT2SAS_HP_EMBEDDED_2_4_INTERNAL_BRANDING);
3781	4335	break;
3782	4336	default:
3783		- pr_info(MPT3SAS_FMT
3784		- "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
3785		- ioc->name, ioc->pdev->subsystem_device);
	4337	+ ioc_info(ioc, "HP 6Gbps SAS HBA: Subsystem ID: 0x%X\n",
	4338	+ ioc->pdev->subsystem_device);
3786	4339	break;
3787	4340	}
	4341	+ break;
3788	4342	default:
3789		- pr_info(MPT3SAS_FMT
3790		- "HP SAS HBA: Subsystem ID: 0x%X\n",
3791		- ioc->name, ioc->pdev->subsystem_device);
	4343	+ ioc_info(ioc, "HP SAS HBA: Subsystem ID: 0x%X\n",
	4344	+ ioc->pdev->subsystem_device);
3792	4345	break;
3793	4346	}
3794	4347	default:
..	..	@@ -3806,37 +4359,37 @@
3806	4359	static int
3807	4360	_base_display_fwpkg_version(struct MPT3SAS_ADAPTER *ioc)
3808	4361	{
3809		- Mpi2FWImageHeader_t *FWImgHdr;
	4362	+ Mpi2FWImageHeader_t *fw_img_hdr;
	4363	+ Mpi26ComponentImageHeader_t *cmp_img_hdr;
3810	4364	Mpi25FWUploadRequest_t *mpi_request;
3811	4365	Mpi2FWUploadReply_t mpi_reply;
3812	4366	int r = 0;
	4367	+ u32 package_version = 0;
3813	4368	void *fwpkg_data = NULL;
3814	4369	dma_addr_t fwpkg_data_dma;
3815	4370	u16 smid, ioc_status;
3816	4371	size_t data_length;
3817	4372
3818		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3819		- __func__));
	4373	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
3820	4374
3821	4375	if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
3822		- pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
3823		- ioc->name, __func__);
	4376	+ ioc_err(ioc, "%s: internal command already in use\n", __func__);
3824	4377	return -EAGAIN;
3825	4378	}
3826	4379
3827	4380	data_length = sizeof(Mpi2FWImageHeader_t);
3828		- fwpkg_data = pci_alloc_consistent(ioc->pdev, data_length,
3829		- &fwpkg_data_dma);
	4381	+ fwpkg_data = dma_alloc_coherent(&ioc->pdev->dev, data_length,
	4382	+ &fwpkg_data_dma, GFP_KERNEL);
3830	4383	if (!fwpkg_data) {
3831		- pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
3832		- ioc->name, __FILE__, __LINE__, __func__);
	4384	+ ioc_err(ioc,
	4385	+ "Memory allocation for fwpkg data failed at %s:%d/%s()!\n",
	4386	+ __FILE__, __LINE__, __func__);
3833	4387	return -ENOMEM;
3834	4388	}
3835	4389
3836	4390	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
3837	4391	if (!smid) {
3838		- pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3839		- ioc->name, __func__);
	4392	+ ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
3840	4393	r = -EAGAIN;
3841	4394	goto out;
3842	4395	}
..	..	@@ -3851,15 +4404,13 @@
3851	4404	ioc->build_sg(ioc, &mpi_request->SGL, 0, 0, fwpkg_data_dma,
3852	4405	data_length);
3853	4406	init_completion(&ioc->base_cmds.done);
3854		- mpt3sas_base_put_smid_default(ioc, smid);
	4407	+ ioc->put_smid_default(ioc, smid);
3855	4408	/* Wait for 15 seconds */
3856	4409	wait_for_completion_timeout(&ioc->base_cmds.done,
3857	4410	FW_IMG_HDR_READ_TIMEOUT*HZ);
3858		- pr_info(MPT3SAS_FMT "%s: complete\n",
3859		- ioc->name, __func__);
	4411	+ ioc_info(ioc, "%s: complete\n", __func__);
3860	4412	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
3861		- pr_err(MPT3SAS_FMT "%s: timeout\n",
3862		- ioc->name, __func__);
	4413	+ ioc_err(ioc, "%s: timeout\n", __func__);
3863	4414	_debug_dump_mf(mpi_request,
3864	4415	sizeof(Mpi25FWUploadRequest_t)/4);
3865	4416	r = -ETIME;
..	..	@@ -3871,16 +4422,26 @@
3871	4422	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
3872	4423	MPI2_IOCSTATUS_MASK;
3873	4424	if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
3874		- FWImgHdr = (Mpi2FWImageHeader_t *)fwpkg_data;
3875		- if (FWImgHdr->PackageVersion.Word) {
3876		- pr_info(MPT3SAS_FMT "FW Package Version"
3877		- "(%02d.%02d.%02d.%02d)\n",
3878		- ioc->name,
3879		- FWImgHdr->PackageVersion.Struct.Major,
3880		- FWImgHdr->PackageVersion.Struct.Minor,
3881		- FWImgHdr->PackageVersion.Struct.Unit,
3882		- FWImgHdr->PackageVersion.Struct.Dev);
3883		- }
	4425	+ fw_img_hdr = (Mpi2FWImageHeader_t *)fwpkg_data;
	4426	+ if (le32_to_cpu(fw_img_hdr->Signature) ==
	4427	+ MPI26_IMAGE_HEADER_SIGNATURE0_MPI26) {
	4428	+ cmp_img_hdr =
	4429	+ (Mpi26ComponentImageHeader_t *)
	4430	+ (fwpkg_data);
	4431	+ package_version =
	4432	+ le32_to_cpu(
	4433	+ cmp_img_hdr->ApplicationSpecific);
	4434	+ } else
	4435	+ package_version =
	4436	+ le32_to_cpu(
	4437	+ fw_img_hdr->PackageVersion.Word);
	4438	+ if (package_version)
	4439	+ ioc_info(ioc,
	4440	+ "FW Package Ver(%02d.%02d.%02d.%02d)\n",
	4441	+ ((package_version) & 0xFF000000) >> 24,
	4442	+ ((package_version) & 0x00FF0000) >> 16,
	4443	+ ((package_version) & 0x0000FF00) >> 8,
	4444	+ (package_version) & 0x000000FF);
3884	4445	} else {
3885	4446	_debug_dump_mf(&mpi_reply,
3886	4447	sizeof(Mpi2FWUploadReply_t)/4);
..	..	@@ -3890,7 +4451,7 @@
3890	4451	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3891	4452	out:
3892	4453	if (fwpkg_data)
3893		- pci_free_consistent(ioc->pdev, data_length, fwpkg_data,
	4454	+ dma_free_coherent(&ioc->pdev->dev, data_length, fwpkg_data,
3894	4455	fwpkg_data_dma);
3895	4456	return r;
3896	4457	}
..	..	@@ -3909,18 +4470,17 @@
3909	4470
3910	4471	bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
3911	4472	strncpy(desc, ioc->manu_pg0.ChipName, 16);
3912		- pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
3913		- "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
3914		- ioc->name, desc,
3915		- (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
3916		- (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
3917		- (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
3918		- ioc->facts.FWVersion.Word & 0x000000FF,
3919		- ioc->pdev->revision,
3920		- (bios_version & 0xFF000000) >> 24,
3921		- (bios_version & 0x00FF0000) >> 16,
3922		- (bios_version & 0x0000FF00) >> 8,
3923		- bios_version & 0x000000FF);
	4473	+ ioc_info(ioc, "%s: FWVersion(%02d.%02d.%02d.%02d), ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
	4474	+ desc,
	4475	+ (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
	4476	+ (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
	4477	+ (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
	4478	+ ioc->facts.FWVersion.Word & 0x000000FF,
	4479	+ ioc->pdev->revision,
	4480	+ (bios_version & 0xFF000000) >> 24,
	4481	+ (bios_version & 0x00FF0000) >> 16,
	4482	+ (bios_version & 0x0000FF00) >> 8,
	4483	+ bios_version & 0x000000FF);
3924	4484
3925	4485	_base_display_OEMs_branding(ioc);
3926	4486
..	..	@@ -3929,82 +4489,81 @@
3929	4489	i++;
3930	4490	}
3931	4491
3932		- pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
	4492	+ ioc_info(ioc, "Protocol=(");
3933	4493
3934	4494	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
3935		- pr_info("Initiator");
	4495	+ pr_cont("Initiator");
3936	4496	i++;
3937	4497	}
3938	4498
3939	4499	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
3940		- pr_info("%sTarget", i ? "," : "");
	4500	+ pr_cont("%sTarget", i ? "," : "");
3941	4501	i++;
3942	4502	}
3943	4503
3944	4504	i = 0;
3945		- pr_info("), ");
3946		- pr_info("Capabilities=(");
	4505	+ pr_cont("), Capabilities=(");
3947	4506
3948	4507	if (!ioc->hide_ir_msg) {
3949	4508	if (ioc->facts.IOCCapabilities &
3950	4509	MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
3951		- pr_info("Raid");
	4510	+ pr_cont("Raid");
3952	4511	i++;
3953	4512	}
3954	4513	}
3955	4514
3956	4515	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
3957		- pr_info("%sTLR", i ? "," : "");
	4516	+ pr_cont("%sTLR", i ? "," : "");
3958	4517	i++;
3959	4518	}
3960	4519
3961	4520	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
3962		- pr_info("%sMulticast", i ? "," : "");
	4521	+ pr_cont("%sMulticast", i ? "," : "");
3963	4522	i++;
3964	4523	}
3965	4524
3966	4525	if (ioc->facts.IOCCapabilities &
3967	4526	MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
3968		- pr_info("%sBIDI Target", i ? "," : "");
	4527	+ pr_cont("%sBIDI Target", i ? "," : "");
3969	4528	i++;
3970	4529	}
3971	4530
3972	4531	if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
3973		- pr_info("%sEEDP", i ? "," : "");
	4532	+ pr_cont("%sEEDP", i ? "," : "");
3974	4533	i++;
3975	4534	}
3976	4535
3977	4536	if (ioc->facts.IOCCapabilities &
3978	4537	MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
3979		- pr_info("%sSnapshot Buffer", i ? "," : "");
	4538	+ pr_cont("%sSnapshot Buffer", i ? "," : "");
3980	4539	i++;
3981	4540	}
3982	4541
3983	4542	if (ioc->facts.IOCCapabilities &
3984	4543	MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
3985		- pr_info("%sDiag Trace Buffer", i ? "," : "");
	4544	+ pr_cont("%sDiag Trace Buffer", i ? "," : "");
3986	4545	i++;
3987	4546	}
3988	4547
3989	4548	if (ioc->facts.IOCCapabilities &
3990	4549	MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
3991		- pr_info("%sDiag Extended Buffer", i ? "," : "");
	4550	+ pr_cont("%sDiag Extended Buffer", i ? "," : "");
3992	4551	i++;
3993	4552	}
3994	4553
3995	4554	if (ioc->facts.IOCCapabilities &
3996	4555	MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
3997		- pr_info("%sTask Set Full", i ? "," : "");
	4556	+ pr_cont("%sTask Set Full", i ? "," : "");
3998	4557	i++;
3999	4558	}
4000	4559
4001	4560	iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
4002	4561	if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
4003		- pr_info("%sNCQ", i ? "," : "");
	4562	+ pr_cont("%sNCQ", i ? "," : "");
4004	4563	i++;
4005	4564	}
4006	4565
4007		- pr_info(")\n");
	4566	+ pr_cont(")\n");
4008	4567	}
4009	4568
4010	4569	/**
..	..	@@ -4037,21 +4596,21 @@
4037	4596	sizeof(Mpi2SasIOUnit1PhyData_t));
4038	4597	sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
4039	4598	if (!sas_iounit_pg1) {
4040		- pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
4041		- ioc->name, __FILE__, __LINE__, __func__);
	4599	+ ioc_err(ioc, "failure at %s:%d/%s()!\n",
	4600	+ __FILE__, __LINE__, __func__);
4042	4601	goto out;
4043	4602	}
4044	4603	if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
4045	4604	sas_iounit_pg1, sz))) {
4046		- pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
4047		- ioc->name, __FILE__, __LINE__, __func__);
	4605	+ ioc_err(ioc, "failure at %s:%d/%s()!\n",
	4606	+ __FILE__, __LINE__, __func__);
4048	4607	goto out;
4049	4608	}
4050	4609	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
4051	4610	MPI2_IOCSTATUS_MASK;
4052	4611	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4053		- pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
4054		- ioc->name, __FILE__, __LINE__, __func__);
	4612	+ ioc_err(ioc, "failure at %s:%d/%s()!\n",
	4613	+ __FILE__, __LINE__, __func__);
4055	4614	goto out;
4056	4615	}
4057	4616
..	..	@@ -4083,17 +4642,82 @@
4083	4642	else
4084	4643	dmd_new =
4085	4644	dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
4086		- pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
4087		- ioc->name, dmd_orignal, dmd_new);
4088		- pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
4089		- ioc->name, io_missing_delay_original,
4090		- io_missing_delay);
	4645	+ ioc_info(ioc, "device_missing_delay: old(%d), new(%d)\n",
	4646	+ dmd_orignal, dmd_new);
	4647	+ ioc_info(ioc, "ioc_missing_delay: old(%d), new(%d)\n",
	4648	+ io_missing_delay_original,
	4649	+ io_missing_delay);
4091	4650	ioc->device_missing_delay = dmd_new;
4092	4651	ioc->io_missing_delay = io_missing_delay;
4093	4652	}
4094	4653
4095	4654	out:
4096	4655	kfree(sas_iounit_pg1);
	4656	+}
	4657	+
	4658	+/**
	4659	+ * _base_update_ioc_page1_inlinewith_perf_mode - Update IOC Page1 fields
	4660	+ * according to performance mode.
	4661	+ * @ioc : per adapter object
	4662	+ *
	4663	+ * Return nothing.
	4664	+ */
	4665	+static void
	4666	+_base_update_ioc_page1_inlinewith_perf_mode(struct MPT3SAS_ADAPTER *ioc)
	4667	+{
	4668	+ Mpi2IOCPage1_t ioc_pg1;
	4669	+ Mpi2ConfigReply_t mpi_reply;
	4670	+
	4671	+ mpt3sas_config_get_ioc_pg1(ioc, &mpi_reply, &ioc->ioc_pg1_copy);
	4672	+ memcpy(&ioc_pg1, &ioc->ioc_pg1_copy, sizeof(Mpi2IOCPage1_t));
	4673	+
	4674	+ switch (perf_mode) {
	4675	+ case MPT_PERF_MODE_DEFAULT:
	4676	+ case MPT_PERF_MODE_BALANCED:
	4677	+ if (ioc->high_iops_queues) {
	4678	+ ioc_info(ioc,
	4679	+ "Enable interrupt coalescing only for first\t"
	4680	+ "%d reply queues\n",
	4681	+ MPT3SAS_HIGH_IOPS_REPLY_QUEUES);
	4682	+ /*
	4683	+ * If 31st bit is zero then interrupt coalescing is
	4684	+ * enabled for all reply descriptor post queues.
	4685	+ * If 31st bit is set to one then user can
	4686	+ * enable/disable interrupt coalescing on per reply
	4687	+ * descriptor post queue group(8) basis. So to enable
	4688	+ * interrupt coalescing only on first reply descriptor
	4689	+ * post queue group 31st bit and zero th bit is enabled.
	4690	+ */
	4691	+ ioc_pg1.ProductSpecific = cpu_to_le32(0x80000000 \|
	4692	+ ((1 << MPT3SAS_HIGH_IOPS_REPLY_QUEUES/8) - 1));
	4693	+ mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
	4694	+ ioc_info(ioc, "performance mode: balanced\n");
	4695	+ return;
	4696	+ }
	4697	+ fallthrough;
	4698	+ case MPT_PERF_MODE_LATENCY:
	4699	+ /*
	4700	+ * Enable interrupt coalescing on all reply queues
	4701	+ * with timeout value 0xA
	4702	+ */
	4703	+ ioc_pg1.CoalescingTimeout = cpu_to_le32(0xa);
	4704	+ ioc_pg1.Flags \|= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING);
	4705	+ ioc_pg1.ProductSpecific = 0;
	4706	+ mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
	4707	+ ioc_info(ioc, "performance mode: latency\n");
	4708	+ break;
	4709	+ case MPT_PERF_MODE_IOPS:
	4710	+ /*
	4711	+ * Enable interrupt coalescing on all reply queues.
	4712	+ */
	4713	+ ioc_info(ioc,
	4714	+ "performance mode: iops with coalescing timeout: 0x%x\n",
	4715	+ le32_to_cpu(ioc_pg1.CoalescingTimeout));
	4716	+ ioc_pg1.Flags \|= cpu_to_le32(MPI2_IOCPAGE1_REPLY_COALESCING);
	4717	+ ioc_pg1.ProductSpecific = 0;
	4718	+ mpt3sas_config_set_ioc_pg1(ioc, &mpi_reply, &ioc_pg1);
	4719	+ break;
	4720	+ }
4097	4721	}
4098	4722
4099	4723	/**
..	..	@@ -4163,6 +4787,8 @@
4163	4787
4164	4788	if (ioc->iounit_pg8.NumSensors)
4165	4789	ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
	4790	+ if (ioc->is_aero_ioc)
	4791	+ _base_update_ioc_page1_inlinewith_perf_mode(ioc);
4166	4792	}
4167	4793
4168	4794	/**
..	..	@@ -4195,36 +4821,36 @@
4195	4821	{
4196	4822	int i = 0;
4197	4823	int j = 0;
	4824	+ int dma_alloc_count = 0;
4198	4825	struct chain_tracker *ct;
4199		- struct reply_post_struct *rps;
	4826	+ int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
4200	4827
4201		- dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4202		- __func__));
	4828	+ dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
4203	4829
4204	4830	if (ioc->request) {
4205		- pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
	4831	+ dma_free_coherent(&ioc->pdev->dev, ioc->request_dma_sz,
4206	4832	ioc->request, ioc->request_dma);
4207		- dexitprintk(ioc, pr_info(MPT3SAS_FMT
4208		- "request_pool(0x%p): free\n",
4209		- ioc->name, ioc->request));
	4833	+ dexitprintk(ioc,
	4834	+ ioc_info(ioc, "request_pool(0x%p): free\n",
	4835	+ ioc->request));
4210	4836	ioc->request = NULL;
4211	4837	}
4212	4838
4213	4839	if (ioc->sense) {
4214	4840	dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
4215	4841	dma_pool_destroy(ioc->sense_dma_pool);
4216		- dexitprintk(ioc, pr_info(MPT3SAS_FMT
4217		- "sense_pool(0x%p): free\n",
4218		- ioc->name, ioc->sense));
	4842	+ dexitprintk(ioc,
	4843	+ ioc_info(ioc, "sense_pool(0x%p): free\n",
	4844	+ ioc->sense));
4219	4845	ioc->sense = NULL;
4220	4846	}
4221	4847
4222	4848	if (ioc->reply) {
4223	4849	dma_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
4224	4850	dma_pool_destroy(ioc->reply_dma_pool);
4225		- dexitprintk(ioc, pr_info(MPT3SAS_FMT
4226		- "reply_pool(0x%p): free\n",
4227		- ioc->name, ioc->reply));
	4851	+ dexitprintk(ioc,
	4852	+ ioc_info(ioc, "reply_pool(0x%p): free\n",
	4853	+ ioc->reply));
4228	4854	ioc->reply = NULL;
4229	4855	}
4230	4856
..	..	@@ -4232,36 +4858,41 @@
4232	4858	dma_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
4233	4859	ioc->reply_free_dma);
4234	4860	dma_pool_destroy(ioc->reply_free_dma_pool);
4235		- dexitprintk(ioc, pr_info(MPT3SAS_FMT
4236		- "reply_free_pool(0x%p): free\n",
4237		- ioc->name, ioc->reply_free));
	4861	+ dexitprintk(ioc,
	4862	+ ioc_info(ioc, "reply_free_pool(0x%p): free\n",
	4863	+ ioc->reply_free));
4238	4864	ioc->reply_free = NULL;
4239	4865	}
4240	4866
4241	4867	if (ioc->reply_post) {
4242		- do {
4243		- rps = &ioc->reply_post[i];
4244		- if (rps->reply_post_free) {
4245		- dma_pool_free(
4246		- ioc->reply_post_free_dma_pool,
4247		- rps->reply_post_free,
4248		- rps->reply_post_free_dma);
4249		- dexitprintk(ioc, pr_info(MPT3SAS_FMT
4250		- "reply_post_free_pool(0x%p): free\n",
4251		- ioc->name, rps->reply_post_free));
4252		- rps->reply_post_free = NULL;
	4868	+ dma_alloc_count = DIV_ROUND_UP(count,
	4869	+ RDPQ_MAX_INDEX_IN_ONE_CHUNK);
	4870	+ for (i = 0; i < count; i++) {
	4871	+ if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0
	4872	+ && dma_alloc_count) {
	4873	+ if (ioc->reply_post[i].reply_post_free) {
	4874	+ dma_pool_free(
	4875	+ ioc->reply_post_free_dma_pool,
	4876	+ ioc->reply_post[i].reply_post_free,
	4877	+ ioc->reply_post[i].reply_post_free_dma);
	4878	+ dexitprintk(ioc, ioc_info(ioc,
	4879	+ "reply_post_free_pool(0x%p): free\n",
	4880	+ ioc->reply_post[i].reply_post_free));
	4881	+ ioc->reply_post[i].reply_post_free =
	4882	+ NULL;
	4883	+ }
	4884	+ --dma_alloc_count;
4253	4885	}
4254		- } while (ioc->rdpq_array_enable &&
4255		- (++i < ioc->reply_queue_count));
	4886	+ }
	4887	+ dma_pool_destroy(ioc->reply_post_free_dma_pool);
4256	4888	if (ioc->reply_post_free_array &&
4257	4889	ioc->rdpq_array_enable) {
4258	4890	dma_pool_free(ioc->reply_post_free_array_dma_pool,
4259		- ioc->reply_post_free_array,
4260		- ioc->reply_post_free_array_dma);
	4891	+ ioc->reply_post_free_array,
	4892	+ ioc->reply_post_free_array_dma);
4261	4893	ioc->reply_post_free_array = NULL;
4262	4894	}
4263	4895	dma_pool_destroy(ioc->reply_post_free_array_dma_pool);
4264		- dma_pool_destroy(ioc->reply_post_free_dma_pool);
4265	4896	kfree(ioc->reply_post);
4266	4897	}
4267	4898
..	..	@@ -4270,16 +4901,15 @@
4270	4901	dma_pool_free(ioc->pcie_sgl_dma_pool,
4271	4902	ioc->pcie_sg_lookup[i].pcie_sgl,
4272	4903	ioc->pcie_sg_lookup[i].pcie_sgl_dma);
	4904	+ ioc->pcie_sg_lookup[i].pcie_sgl = NULL;
4273	4905	}
4274		- if (ioc->pcie_sgl_dma_pool)
4275		- dma_pool_destroy(ioc->pcie_sgl_dma_pool);
	4906	+ dma_pool_destroy(ioc->pcie_sgl_dma_pool);
4276	4907	}
4277		-
4278	4908	if (ioc->config_page) {
4279		- dexitprintk(ioc, pr_info(MPT3SAS_FMT
4280		- "config_page(0x%p): free\n", ioc->name,
4281		- ioc->config_page));
4282		- pci_free_consistent(ioc->pdev, ioc->config_page_sz,
	4909	+ dexitprintk(ioc,
	4910	+ ioc_info(ioc, "config_page(0x%p): free\n",
	4911	+ ioc->config_page));
	4912	+ dma_free_coherent(&ioc->pdev->dev, ioc->config_page_sz,
4283	4913	ioc->config_page, ioc->config_page_dma);
4284	4914	}
4285	4915
..	..	@@ -4306,7 +4936,7 @@
4306	4936	}
4307	4937
4308	4938	/**
4309		- * is_MSB_are_same - checks whether all reply queues in a set are
	4939	+ * mpt3sas_check_same_4gb_region - checks whether all reply queues in a set are
4310	4940	* having same upper 32bits in their base memory address.
4311	4941	* @reply_pool_start_address: Base address of a reply queue set
4312	4942	* @pool_sz: Size of single Reply Descriptor Post Queues pool size
..	..	@@ -4316,7 +4946,7 @@
4316	4946	*/
4317	4947
4318	4948	static int
4319		-is_MSB_are_same(long reply_pool_start_address, u32 pool_sz)
	4949	+mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz)
4320	4950	{
4321	4951	long reply_pool_end_address;
4322	4952
..	..	@@ -4327,6 +4957,168 @@
4327	4957	return 1;
4328	4958	else
4329	4959	return 0;
	4960	+}
	4961	+
	4962	+/**
	4963	+ * _base_reduce_hba_queue_depth- Retry with reduced queue depth
	4964	+ * @ioc: Adapter object
	4965	+ *
	4966	+ * Return: 0 for success, non-zero for failure.
	4967	+ **/
	4968	+static inline int
	4969	+_base_reduce_hba_queue_depth(struct MPT3SAS_ADAPTER *ioc)
	4970	+{
	4971	+ int reduce_sz = 64;
	4972	+
	4973	+ if ((ioc->hba_queue_depth - reduce_sz) >
	4974	+ (ioc->internal_depth + INTERNAL_SCSIIO_CMDS_COUNT)) {
	4975	+ ioc->hba_queue_depth -= reduce_sz;
	4976	+ return 0;
	4977	+ } else
	4978	+ return -ENOMEM;
	4979	+}
	4980	+
	4981	+/**
	4982	+ * _base_allocate_pcie_sgl_pool - Allocating DMA'able memory
	4983	+ * for pcie sgl pools.
	4984	+ * @ioc: Adapter object
	4985	+ * @sz: DMA Pool size
	4986	+ * @ct: Chain tracker
	4987	+ * Return: 0 for success, non-zero for failure.
	4988	+ */
	4989	+
	4990	+static int
	4991	+_base_allocate_pcie_sgl_pool(struct MPT3SAS_ADAPTER *ioc, u32 sz)
	4992	+{
	4993	+ int i = 0, j = 0;
	4994	+ struct chain_tracker *ct;
	4995	+
	4996	+ ioc->pcie_sgl_dma_pool =
	4997	+ dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz,
	4998	+ ioc->page_size, 0);
	4999	+ if (!ioc->pcie_sgl_dma_pool) {
	5000	+ ioc_err(ioc, "PCIe SGL pool: dma_pool_create failed\n");
	5001	+ return -ENOMEM;
	5002	+ }
	5003	+
	5004	+ ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz;
	5005	+ ioc->chains_per_prp_buffer =
	5006	+ min(ioc->chains_per_prp_buffer, ioc->chains_needed_per_io);
	5007	+ for (i = 0; i < ioc->scsiio_depth; i++) {
	5008	+ ioc->pcie_sg_lookup[i].pcie_sgl =
	5009	+ dma_pool_alloc(ioc->pcie_sgl_dma_pool, GFP_KERNEL,
	5010	+ &ioc->pcie_sg_lookup[i].pcie_sgl_dma);
	5011	+ if (!ioc->pcie_sg_lookup[i].pcie_sgl) {
	5012	+ ioc_err(ioc, "PCIe SGL pool: dma_pool_alloc failed\n");
	5013	+ return -EAGAIN;
	5014	+ }
	5015	+
	5016	+ if (!mpt3sas_check_same_4gb_region(
	5017	+ (long)ioc->pcie_sg_lookup[i].pcie_sgl, sz)) {
	5018	+ ioc_err(ioc, "PCIE SGLs are not in same 4G !! pcie sgl (0x%p) dma = (0x%llx)\n",
	5019	+ ioc->pcie_sg_lookup[i].pcie_sgl,
	5020	+ (unsigned long long)
	5021	+ ioc->pcie_sg_lookup[i].pcie_sgl_dma);
	5022	+ ioc->use_32bit_dma = true;
	5023	+ return -EAGAIN;
	5024	+ }
	5025	+
	5026	+ for (j = 0; j < ioc->chains_per_prp_buffer; j++) {
	5027	+ ct = &ioc->chain_lookup[i].chains_per_smid[j];
	5028	+ ct->chain_buffer =
	5029	+ ioc->pcie_sg_lookup[i].pcie_sgl +
	5030	+ (j * ioc->chain_segment_sz);
	5031	+ ct->chain_buffer_dma =
	5032	+ ioc->pcie_sg_lookup[i].pcie_sgl_dma +
	5033	+ (j * ioc->chain_segment_sz);
	5034	+ }
	5035	+ }
	5036	+ dinitprintk(ioc, ioc_info(ioc,
	5037	+ "PCIe sgl pool depth(%d), element_size(%d), pool_size(%d kB)\n",
	5038	+ ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024));
	5039	+ dinitprintk(ioc, ioc_info(ioc,
	5040	+ "Number of chains can fit in a PRP page(%d)\n",
	5041	+ ioc->chains_per_prp_buffer));
	5042	+ return 0;
	5043	+}
	5044	+
	5045	+/**
	5046	+ * base_alloc_rdpq_dma_pool - Allocating DMA'able memory
	5047	+ * for reply queues.
	5048	+ * @ioc: per adapter object
	5049	+ * @sz: DMA Pool size
	5050	+ * Return: 0 for success, non-zero for failure.
	5051	+ */
	5052	+static int
	5053	+base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz)
	5054	+{
	5055	+ int i = 0;
	5056	+ u32 dma_alloc_count = 0;
	5057	+ int reply_post_free_sz = ioc->reply_post_queue_depth *
	5058	+ sizeof(Mpi2DefaultReplyDescriptor_t);
	5059	+ int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
	5060	+
	5061	+ ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct),
	5062	+ GFP_KERNEL);
	5063	+ if (!ioc->reply_post)
	5064	+ return -ENOMEM;
	5065	+ /*
	5066	+ * For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and
	5067	+ * VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should
	5068	+ * be within 4GB boundary i.e reply queues in a set must have same
	5069	+ * upper 32-bits in their memory address. so here driver is allocating
	5070	+ * the DMA'able memory for reply queues according.
	5071	+ * Driver uses limitation of
	5072	+ * VENTURA_SERIES to manage INVADER_SERIES as well.
	5073	+ */
	5074	+ dma_alloc_count = DIV_ROUND_UP(count,
	5075	+ RDPQ_MAX_INDEX_IN_ONE_CHUNK);
	5076	+ ioc->reply_post_free_dma_pool =
	5077	+ dma_pool_create("reply_post_free pool",
	5078	+ &ioc->pdev->dev, sz, 16, 0);
	5079	+ if (!ioc->reply_post_free_dma_pool)
	5080	+ return -ENOMEM;
	5081	+ for (i = 0; i < count; i++) {
	5082	+ if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) {
	5083	+ ioc->reply_post[i].reply_post_free =
	5084	+ dma_pool_zalloc(ioc->reply_post_free_dma_pool,
	5085	+ GFP_KERNEL,
	5086	+ &ioc->reply_post[i].reply_post_free_dma);
	5087	+ if (!ioc->reply_post[i].reply_post_free)
	5088	+ return -ENOMEM;
	5089	+ /*
	5090	+ * Each set of RDPQ pool must satisfy 4gb boundary
	5091	+ * restriction.
	5092	+ * 1) Check if allocated resources for RDPQ pool are in
	5093	+ * the same 4GB range.
	5094	+ * 2) If #1 is true, continue with 64 bit DMA.
	5095	+ * 3) If #1 is false, return 1. which means free all the
	5096	+ * resources and set DMA mask to 32 and allocate.
	5097	+ */
	5098	+ if (!mpt3sas_check_same_4gb_region(
	5099	+ (long)ioc->reply_post[i].reply_post_free, sz)) {
	5100	+ dinitprintk(ioc,
	5101	+ ioc_err(ioc, "bad Replypost free pool(0x%p)"
	5102	+ "reply_post_free_dma = (0x%llx)\n",
	5103	+ ioc->reply_post[i].reply_post_free,
	5104	+ (unsigned long long)
	5105	+ ioc->reply_post[i].reply_post_free_dma));
	5106	+ return -EAGAIN;
	5107	+ }
	5108	+ dma_alloc_count--;
	5109	+
	5110	+ } else {
	5111	+ ioc->reply_post[i].reply_post_free =
	5112	+ (Mpi2ReplyDescriptorsUnion_t *)
	5113	+ ((long)ioc->reply_post[i-1].reply_post_free
	5114	+ + reply_post_free_sz);
	5115	+ ioc->reply_post[i].reply_post_free_dma =
	5116	+ (dma_addr_t)
	5117	+ (ioc->reply_post[i-1].reply_post_free_dma +
	5118	+ reply_post_free_sz);
	5119	+ }
	5120	+ }
	5121	+ return 0;
4330	5122	}
4331	5123
4332	5124	/**
..	..	@@ -4343,14 +5135,15 @@
4343	5135	u16 chains_needed_per_io;
4344	5136	u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz;
4345	5137	u32 retry_sz;
	5138	+ u32 rdpq_sz = 0;
4346	5139	u16 max_request_credit, nvme_blocks_needed;
4347	5140	unsigned short sg_tablesize;
4348	5141	u16 sge_size;
4349	5142	int i, j;
	5143	+ int ret = 0, rc = 0;
4350	5144	struct chain_tracker *ct;
4351	5145
4352		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4353		- __func__));
	5146	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
4354	5147
4355	5148
4356	5149	retry_sz = 0;
..	..	@@ -4379,10 +5172,8 @@
4379	5172	else if (sg_tablesize > MPT_MAX_PHYS_SEGMENTS) {
4380	5173	sg_tablesize = min_t(unsigned short, sg_tablesize,
4381	5174	SG_MAX_SEGMENTS);
4382		- pr_warn(MPT3SAS_FMT
4383		- "sg_tablesize(%u) is bigger than kernel "
4384		- "defined SG_CHUNK_SIZE(%u)\n", ioc->name,
4385		- sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
	5175	+ ioc_warn(ioc, "sg_tablesize(%u) is bigger than kernel defined SG_CHUNK_SIZE(%u)\n",
	5176	+ sg_tablesize, MPT_MAX_PHYS_SEGMENTS);
4386	5177	}
4387	5178	ioc->shost->sg_tablesize = sg_tablesize;
4388	5179	}
..	..	@@ -4392,9 +5183,8 @@
4392	5183	if (ioc->internal_depth < INTERNAL_CMDS_COUNT) {
4393	5184	if (facts->RequestCredit <= (INTERNAL_CMDS_COUNT +
4394	5185	INTERNAL_SCSIIO_CMDS_COUNT)) {
4395		- pr_err(MPT3SAS_FMT "IOC doesn't have enough Request \
4396		- Credits, it has just %d number of credits\n",
4397		- ioc->name, facts->RequestCredit);
	5186	+ ioc_err(ioc, "IOC doesn't have enough Request Credits, it has just %d number of credits\n",
	5187	+ facts->RequestCredit);
4398	5188	return -ENOMEM;
4399	5189	}
4400	5190	ioc->internal_depth = 10;
..	..	@@ -4493,71 +5283,39 @@
4493	5283	ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
4494	5284	}
4495	5285
4496		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
4497		- "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
4498		- "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
4499		- ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
4500		- ioc->chains_needed_per_io));
	5286	+ ioc_info(ioc,
	5287	+ "scatter gather: sge_in_main_msg(%d), sge_per_chain(%d), "
	5288	+ "sge_per_io(%d), chains_per_io(%d)\n",
	5289	+ ioc->max_sges_in_main_message,
	5290	+ ioc->max_sges_in_chain_message,
	5291	+ ioc->shost->sg_tablesize,
	5292	+ ioc->chains_needed_per_io);
4501	5293
4502	5294	/* reply post queue, 16 byte align */
4503	5295	reply_post_free_sz = ioc->reply_post_queue_depth *
4504	5296	sizeof(Mpi2DefaultReplyDescriptor_t);
4505		-
4506		- sz = reply_post_free_sz;
	5297	+ rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK;
4507	5298	if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
4508		- sz *= ioc->reply_queue_count;
4509		-
4510		- ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
4511		- (ioc->reply_queue_count):1,
4512		- sizeof(struct reply_post_struct), GFP_KERNEL);
4513		-
4514		- if (!ioc->reply_post) {
4515		- pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
4516		- ioc->name);
4517		- goto out;
4518		- }
4519		- ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool",
4520		- &ioc->pdev->dev, sz, 16, 0);
4521		- if (!ioc->reply_post_free_dma_pool) {
4522		- pr_err(MPT3SAS_FMT
4523		- "reply_post_free pool: dma_pool_create failed\n",
4524		- ioc->name);
4525		- goto out;
4526		- }
4527		- i = 0;
4528		- do {
4529		- ioc->reply_post[i].reply_post_free =
4530		- dma_pool_alloc(ioc->reply_post_free_dma_pool,
4531		- GFP_KERNEL,
4532		- &ioc->reply_post[i].reply_post_free_dma);
4533		- if (!ioc->reply_post[i].reply_post_free) {
4534		- pr_err(MPT3SAS_FMT
4535		- "reply_post_free pool: dma_pool_alloc failed\n",
4536		- ioc->name);
4537		- goto out;
	5299	+ rdpq_sz = reply_post_free_sz * ioc->reply_queue_count;
	5300	+ ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz);
	5301	+ if (ret == -EAGAIN) {
	5302	+ /*
	5303	+ * Free allocated bad RDPQ memory pools.
	5304	+ * Change dma coherent mask to 32 bit and reallocate RDPQ
	5305	+ */
	5306	+ _base_release_memory_pools(ioc);
	5307	+ ioc->use_32bit_dma = true;
	5308	+ if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
	5309	+ ioc_err(ioc,
	5310	+ "32 DMA mask failed %s\n", pci_name(ioc->pdev));
	5311	+ return -ENODEV;
4538	5312	}
4539		- memset(ioc->reply_post[i].reply_post_free, 0, sz);
4540		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4541		- "reply post free pool (0x%p): depth(%d),"
4542		- "element_size(%d), pool_size(%d kB)\n", ioc->name,
4543		- ioc->reply_post[i].reply_post_free,
4544		- ioc->reply_post_queue_depth, 8, sz/1024));
4545		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4546		- "reply_post_free_dma = (0x%llx)\n", ioc->name,
4547		- (unsigned long long)
4548		- ioc->reply_post[i].reply_post_free_dma));
4549		- total_sz += sz;
4550		- } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
4551		-
4552		- if (ioc->dma_mask > 32) {
4553		- if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
4554		- pr_warn(MPT3SAS_FMT
4555		- "no suitable consistent DMA mask for %s\n",
4556		- ioc->name, pci_name(ioc->pdev));
4557		- goto out;
4558		- }
4559		- }
4560		-
	5313	+ if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz))
	5314	+ return -ENOMEM;
	5315	+ } else if (ret == -ENOMEM)
	5316	+ return -ENOMEM;
	5317	+ total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 :
	5318	+ DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK));
4561	5319	ioc->scsiio_depth = ioc->hba_queue_depth -
4562	5320	ioc->hi_priority_depth - ioc->internal_depth;
4563	5321
..	..	@@ -4565,10 +5323,9 @@
4565	5323	* with some internal commands that could be outstanding
4566	5324	*/
4567	5325	ioc->shost->can_queue = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT;
4568		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4569		- "scsi host: can_queue depth (%d)\n",
4570		- ioc->name, ioc->shost->can_queue));
4571		-
	5326	+ dinitprintk(ioc,
	5327	+ ioc_info(ioc, "scsi host: can_queue depth (%d)\n",
	5328	+ ioc->shost->can_queue));
4572	5329
4573	5330	/* contiguous pool for request and chains, 16 byte align, one extra "
4574	5331	* "frame for smid=0
..	..	@@ -4583,12 +5340,12 @@
4583	5340	sz += (ioc->internal_depth * ioc->request_sz);
4584	5341
4585	5342	ioc->request_dma_sz = sz;
4586		- ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
	5343	+ ioc->request = dma_alloc_coherent(&ioc->pdev->dev, sz,
	5344	+ &ioc->request_dma, GFP_KERNEL);
4587	5345	if (!ioc->request) {
4588		- pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
4589		- "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
4590		- "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
4591		- ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
	5346	+ ioc_err(ioc, "request pool: dma_alloc_coherent failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kB)\n",
	5347	+ ioc->hba_queue_depth, ioc->chains_needed_per_io,
	5348	+ ioc->request_sz, sz / 1024);
4592	5349	if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
4593	5350	goto out;
4594	5351	retry_sz = 64;
..	..	@@ -4598,10 +5355,9 @@
4598	5355	}
4599	5356
4600	5357	if (retry_sz)
4601		- pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
4602		- "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
4603		- "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
4604		- ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
	5358	+ ioc_err(ioc, "request pool: dma_alloc_coherent succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), total(%d kb)\n",
	5359	+ ioc->hba_queue_depth, ioc->chains_needed_per_io,
	5360	+ ioc->request_sz, sz / 1024);
4605	5361
4606	5362	/* hi-priority queue */
4607	5363	ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
..	..	@@ -4615,24 +5371,24 @@
4615	5371	ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
4616	5372	ioc->request_sz);
4617	5373
4618		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4619		- "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
4620		- ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
4621		- (ioc->hba_queue_depth * ioc->request_sz)/1024));
	5374	+ ioc_info(ioc,
	5375	+ "request pool(0x%p) - dma(0x%llx): "
	5376	+ "depth(%d), frame_size(%d), pool_size(%d kB)\n",
	5377	+ ioc->request, (unsigned long long) ioc->request_dma,
	5378	+ ioc->hba_queue_depth, ioc->request_sz,
	5379	+ (ioc->hba_queue_depth * ioc->request_sz) / 1024);
4622	5380
4623		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
4624		- ioc->name, (unsigned long long) ioc->request_dma));
4625	5381	total_sz += sz;
4626	5382
4627		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
4628		- ioc->name, ioc->request, ioc->scsiio_depth));
	5383	+ dinitprintk(ioc,
	5384	+ ioc_info(ioc, "scsiio(0x%p): depth(%d)\n",
	5385	+ ioc->request, ioc->scsiio_depth));
4629	5386
4630	5387	ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
4631	5388	sz = ioc->scsiio_depth * sizeof(struct chain_lookup);
4632	5389	ioc->chain_lookup = kzalloc(sz, GFP_KERNEL);
4633	5390	if (!ioc->chain_lookup) {
4634		- pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages "
4635		- "failed\n", ioc->name);
	5391	+ ioc_err(ioc, "chain_lookup: __get_free_pages failed\n");
4636	5392	goto out;
4637	5393	}
4638	5394
..	..	@@ -4640,8 +5396,7 @@
4640	5396	for (i = 0; i < ioc->scsiio_depth; i++) {
4641	5397	ioc->chain_lookup[i].chains_per_smid = kzalloc(sz, GFP_KERNEL);
4642	5398	if (!ioc->chain_lookup[i].chains_per_smid) {
4643		- pr_err(MPT3SAS_FMT "chain_lookup: "
4644		- " kzalloc failed\n", ioc->name);
	5399	+ ioc_err(ioc, "chain_lookup: kzalloc failed\n");
4645	5400	goto out;
4646	5401	}
4647	5402	}
..	..	@@ -4650,29 +5405,27 @@
4650	5405	ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
4651	5406	sizeof(struct request_tracker), GFP_KERNEL);
4652	5407	if (!ioc->hpr_lookup) {
4653		- pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
4654		- ioc->name);
	5408	+ ioc_err(ioc, "hpr_lookup: kcalloc failed\n");
4655	5409	goto out;
4656	5410	}
4657	5411	ioc->hi_priority_smid = ioc->scsiio_depth + 1;
4658		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4659		- "hi_priority(0x%p): depth(%d), start smid(%d)\n",
4660		- ioc->name, ioc->hi_priority,
4661		- ioc->hi_priority_depth, ioc->hi_priority_smid));
	5412	+ dinitprintk(ioc,
	5413	+ ioc_info(ioc, "hi_priority(0x%p): depth(%d), start smid(%d)\n",
	5414	+ ioc->hi_priority,
	5415	+ ioc->hi_priority_depth, ioc->hi_priority_smid));
4662	5416
4663	5417	/* initialize internal queue smid's */
4664	5418	ioc->internal_lookup = kcalloc(ioc->internal_depth,
4665	5419	sizeof(struct request_tracker), GFP_KERNEL);
4666	5420	if (!ioc->internal_lookup) {
4667		- pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
4668		- ioc->name);
	5421	+ ioc_err(ioc, "internal_lookup: kcalloc failed\n");
4669	5422	goto out;
4670	5423	}
4671	5424	ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
4672		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4673		- "internal(0x%p): depth(%d), start smid(%d)\n",
4674		- ioc->name, ioc->internal,
4675		- ioc->internal_depth, ioc->internal_smid));
	5425	+ dinitprintk(ioc,
	5426	+ ioc_info(ioc, "internal(0x%p): depth(%d), start smid(%d)\n",
	5427	+ ioc->internal,
	5428	+ ioc->internal_depth, ioc->internal_smid));
4676	5429	/*
4677	5430	* The number of NVMe page sized blocks needed is:
4678	5431	* (((sg_tablesize * 8) - 1) / (page_size - 8)) + 1
..	..	@@ -4686,6 +5439,7 @@
4686	5439	* be required for NVMe PRP's, only each set of NVMe blocks will be
4687	5440	* contiguous, so a new set is allocated for each possible I/O.
4688	5441	*/
	5442	+
4689	5443	ioc->chains_per_prp_buffer = 0;
4690	5444	if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES) {
4691	5445	nvme_blocks_needed =
..	..	@@ -4696,59 +5450,22 @@
4696	5450	sz = sizeof(struct pcie_sg_list) * ioc->scsiio_depth;
4697	5451	ioc->pcie_sg_lookup = kzalloc(sz, GFP_KERNEL);
4698	5452	if (!ioc->pcie_sg_lookup) {
4699		- pr_info(MPT3SAS_FMT
4700		- "PCIe SGL lookup: kzalloc failed\n", ioc->name);
	5453	+ ioc_info(ioc, "PCIe SGL lookup: kzalloc failed\n");
4701	5454	goto out;
4702	5455	}
4703	5456	sz = nvme_blocks_needed * ioc->page_size;
4704		- ioc->pcie_sgl_dma_pool =
4705		- dma_pool_create("PCIe SGL pool", &ioc->pdev->dev, sz, 16, 0);
4706		- if (!ioc->pcie_sgl_dma_pool) {
4707		- pr_info(MPT3SAS_FMT
4708		- "PCIe SGL pool: dma_pool_create failed\n",
4709		- ioc->name);
4710		- goto out;
4711		- }
4712		-
4713		- ioc->chains_per_prp_buffer = sz/ioc->chain_segment_sz;
4714		- ioc->chains_per_prp_buffer = min(ioc->chains_per_prp_buffer,
4715		- ioc->chains_needed_per_io);
4716		-
4717		- for (i = 0; i < ioc->scsiio_depth; i++) {
4718		- ioc->pcie_sg_lookup[i].pcie_sgl = dma_pool_alloc(
4719		- ioc->pcie_sgl_dma_pool, GFP_KERNEL,
4720		- &ioc->pcie_sg_lookup[i].pcie_sgl_dma);
4721		- if (!ioc->pcie_sg_lookup[i].pcie_sgl) {
4722		- pr_info(MPT3SAS_FMT
4723		- "PCIe SGL pool: dma_pool_alloc failed\n",
4724		- ioc->name);
4725		- goto out;
4726		- }
4727		- for (j = 0; j < ioc->chains_per_prp_buffer; j++) {
4728		- ct = &ioc->chain_lookup[i].chains_per_smid[j];
4729		- ct->chain_buffer =
4730		- ioc->pcie_sg_lookup[i].pcie_sgl +
4731		- (j * ioc->chain_segment_sz);
4732		- ct->chain_buffer_dma =
4733		- ioc->pcie_sg_lookup[i].pcie_sgl_dma +
4734		- (j * ioc->chain_segment_sz);
4735		- }
4736		- }
4737		-
4738		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "PCIe sgl pool depth(%d), "
4739		- "element_size(%d), pool_size(%d kB)\n", ioc->name,
4740		- ioc->scsiio_depth, sz, (sz * ioc->scsiio_depth)/1024));
4741		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "Number of chains can "
4742		- "fit in a PRP page(%d)\n", ioc->name,
4743		- ioc->chains_per_prp_buffer));
	5457	+ rc = _base_allocate_pcie_sgl_pool(ioc, sz);
	5458	+ if (rc == -ENOMEM)
	5459	+ return -ENOMEM;
	5460	+ else if (rc == -EAGAIN)
	5461	+ goto try_32bit_dma;
4744	5462	total_sz += sz * ioc->scsiio_depth;
4745	5463	}
4746	5464
4747	5465	ioc->chain_dma_pool = dma_pool_create("chain pool", &ioc->pdev->dev,
4748	5466	ioc->chain_segment_sz, 16, 0);
4749	5467	if (!ioc->chain_dma_pool) {
4750		- pr_err(MPT3SAS_FMT "chain_dma_pool: dma_pool_create failed\n",
4751		- ioc->name);
	5468	+ ioc_err(ioc, "chain_dma_pool: dma_pool_create failed\n");
4752	5469	goto out;
4753	5470	}
4754	5471	for (i = 0; i < ioc->scsiio_depth; i++) {
..	..	@@ -4759,34 +5476,30 @@
4759	5476	ioc->chain_dma_pool, GFP_KERNEL,
4760	5477	&ct->chain_buffer_dma);
4761	5478	if (!ct->chain_buffer) {
4762		- pr_err(MPT3SAS_FMT "chain_lookup: "
4763		- " pci_pool_alloc failed\n", ioc->name);
4764		- _base_release_memory_pools(ioc);
	5479	+ ioc_err(ioc, "chain_lookup: pci_pool_alloc failed\n");
4765	5480	goto out;
4766	5481	}
4767	5482	}
4768	5483	total_sz += ioc->chain_segment_sz;
4769	5484	}
4770	5485
4771		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4772		- "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
4773		- ioc->name, ioc->chain_depth, ioc->chain_segment_sz,
4774		- ((ioc->chain_depth * ioc->chain_segment_sz))/1024));
	5486	+ dinitprintk(ioc,
	5487	+ ioc_info(ioc, "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
	5488	+ ioc->chain_depth, ioc->chain_segment_sz,
	5489	+ (ioc->chain_depth * ioc->chain_segment_sz) / 1024));
4775	5490
4776	5491	/* sense buffers, 4 byte align */
4777	5492	sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
4778	5493	ioc->sense_dma_pool = dma_pool_create("sense pool", &ioc->pdev->dev, sz,
4779	5494	4, 0);
4780	5495	if (!ioc->sense_dma_pool) {
4781		- pr_err(MPT3SAS_FMT "sense pool: dma_pool_create failed\n",
4782		- ioc->name);
	5496	+ ioc_err(ioc, "sense pool: dma_pool_create failed\n");
4783	5497	goto out;
4784	5498	}
4785	5499	ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL,
4786	5500	&ioc->sense_dma);
4787	5501	if (!ioc->sense) {
4788		- pr_err(MPT3SAS_FMT "sense pool: dma_pool_alloc failed\n",
4789		- ioc->name);
	5502	+ ioc_err(ioc, "sense pool: dma_pool_alloc failed\n");
4790	5503	goto out;
4791	5504	}
4792	5505	/* sense buffer requires to be in same 4 gb region.
..	..	@@ -4798,7 +5511,7 @@
4798	5511	* Actual requirement is not alignment, but we need start and end of
4799	5512	* DMA address must have same upper 32 bit address.
4800	5513	*/
4801		- if (!is_MSB_are_same((long)ioc->sense, sz)) {
	5514	+ if (!mpt3sas_check_same_4gb_region((long)ioc->sense, sz)) {
4802	5515	//Release Sense pool & Reallocate
4803	5516	dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
4804	5517	dma_pool_destroy(ioc->sense_dma_pool);
..	..	@@ -4808,24 +5521,22 @@
4808	5521	dma_pool_create("sense pool", &ioc->pdev->dev, sz,
4809	5522	roundup_pow_of_two(sz), 0);
4810	5523	if (!ioc->sense_dma_pool) {
4811		- pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
4812		- ioc->name);
	5524	+ ioc_err(ioc, "sense pool: pci_pool_create failed\n");
4813	5525	goto out;
4814	5526	}
4815	5527	ioc->sense = dma_pool_alloc(ioc->sense_dma_pool, GFP_KERNEL,
4816	5528	&ioc->sense_dma);
4817	5529	if (!ioc->sense) {
4818		- pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
4819		- ioc->name);
	5530	+ ioc_err(ioc, "sense pool: pci_pool_alloc failed\n");
4820	5531	goto out;
4821	5532	}
4822	5533	}
4823		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4824		- "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
4825		- "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
4826		- SCSI_SENSE_BUFFERSIZE, sz/1024));
4827		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
4828		- ioc->name, (unsigned long long)ioc->sense_dma));
	5534	+ ioc_info(ioc,
	5535	+ "sense pool(0x%p)- dma(0x%llx): depth(%d),"
	5536	+ "element_size(%d), pool_size(%d kB)\n",
	5537	+ ioc->sense, (unsigned long long)ioc->sense_dma, ioc->scsiio_depth,
	5538	+ SCSI_SENSE_BUFFERSIZE, sz / 1024);
	5539	+
4829	5540	total_sz += sz;
4830	5541
4831	5542	/* reply pool, 4 byte align */
..	..	@@ -4833,25 +5544,24 @@
4833	5544	ioc->reply_dma_pool = dma_pool_create("reply pool", &ioc->pdev->dev, sz,
4834	5545	4, 0);
4835	5546	if (!ioc->reply_dma_pool) {
4836		- pr_err(MPT3SAS_FMT "reply pool: dma_pool_create failed\n",
4837		- ioc->name);
	5547	+ ioc_err(ioc, "reply pool: dma_pool_create failed\n");
4838	5548	goto out;
4839	5549	}
4840	5550	ioc->reply = dma_pool_alloc(ioc->reply_dma_pool, GFP_KERNEL,
4841	5551	&ioc->reply_dma);
4842	5552	if (!ioc->reply) {
4843		- pr_err(MPT3SAS_FMT "reply pool: dma_pool_alloc failed\n",
4844		- ioc->name);
	5553	+ ioc_err(ioc, "reply pool: dma_pool_alloc failed\n");
4845	5554	goto out;
4846	5555	}
4847	5556	ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
4848	5557	ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
4849		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4850		- "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
4851		- ioc->name, ioc->reply,
4852		- ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
4853		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
4854		- ioc->name, (unsigned long long)ioc->reply_dma));
	5558	+ dinitprintk(ioc,
	5559	+ ioc_info(ioc, "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
	5560	+ ioc->reply, ioc->reply_free_queue_depth,
	5561	+ ioc->reply_sz, sz / 1024));
	5562	+ dinitprintk(ioc,
	5563	+ ioc_info(ioc, "reply_dma(0x%llx)\n",
	5564	+ (unsigned long long)ioc->reply_dma));
4855	5565	total_sz += sz;
4856	5566
4857	5567	/* reply free queue, 16 byte align */
..	..	@@ -4859,24 +5569,22 @@
4859	5569	ioc->reply_free_dma_pool = dma_pool_create("reply_free pool",
4860	5570	&ioc->pdev->dev, sz, 16, 0);
4861	5571	if (!ioc->reply_free_dma_pool) {
4862		- pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_create failed\n",
4863		- ioc->name);
	5572	+ ioc_err(ioc, "reply_free pool: dma_pool_create failed\n");
4864	5573	goto out;
4865	5574	}
4866		- ioc->reply_free = dma_pool_alloc(ioc->reply_free_dma_pool, GFP_KERNEL,
	5575	+ ioc->reply_free = dma_pool_zalloc(ioc->reply_free_dma_pool, GFP_KERNEL,
4867	5576	&ioc->reply_free_dma);
4868	5577	if (!ioc->reply_free) {
4869		- pr_err(MPT3SAS_FMT "reply_free pool: dma_pool_alloc failed\n",
4870		- ioc->name);
	5578	+ ioc_err(ioc, "reply_free pool: dma_pool_alloc failed\n");
4871	5579	goto out;
4872	5580	}
4873		- memset(ioc->reply_free, 0, sz);
4874		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
4875		- "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
4876		- ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
4877		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4878		- "reply_free_dma (0x%llx)\n",
4879		- ioc->name, (unsigned long long)ioc->reply_free_dma));
	5581	+ dinitprintk(ioc,
	5582	+ ioc_info(ioc, "reply_free pool(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
	5583	+ ioc->reply_free, ioc->reply_free_queue_depth,
	5584	+ 4, sz / 1024));
	5585	+ dinitprintk(ioc,
	5586	+ ioc_info(ioc, "reply_free_dma (0x%llx)\n",
	5587	+ (unsigned long long)ioc->reply_free_dma));
4880	5588	total_sz += sz;
4881	5589
4882	5590	if (ioc->rdpq_array_enable) {
..	..	@@ -4887,8 +5595,7 @@
4887	5595	&ioc->pdev->dev, reply_post_free_array_sz, 16, 0);
4888	5596	if (!ioc->reply_post_free_array_dma_pool) {
4889	5597	dinitprintk(ioc,
4890		- pr_info(MPT3SAS_FMT "reply_post_free_array pool: "
4891		- "dma_pool_create failed\n", ioc->name));
	5598	+ ioc_info(ioc, "reply_post_free_array pool: dma_pool_create failed\n"));
4892	5599	goto out;
4893	5600	}
4894	5601	ioc->reply_post_free_array =
..	..	@@ -4896,35 +5603,43 @@
4896	5603	GFP_KERNEL, &ioc->reply_post_free_array_dma);
4897	5604	if (!ioc->reply_post_free_array) {
4898	5605	dinitprintk(ioc,
4899		- pr_info(MPT3SAS_FMT "reply_post_free_array pool: "
4900		- "dma_pool_alloc failed\n", ioc->name));
	5606	+ ioc_info(ioc, "reply_post_free_array pool: dma_pool_alloc failed\n"));
4901	5607	goto out;
4902	5608	}
4903	5609	}
4904	5610	ioc->config_page_sz = 512;
4905		- ioc->config_page = pci_alloc_consistent(ioc->pdev,
4906		- ioc->config_page_sz, &ioc->config_page_dma);
	5611	+ ioc->config_page = dma_alloc_coherent(&ioc->pdev->dev,
	5612	+ ioc->config_page_sz, &ioc->config_page_dma, GFP_KERNEL);
4907	5613	if (!ioc->config_page) {
4908		- pr_err(MPT3SAS_FMT
4909		- "config page: dma_pool_alloc failed\n",
4910		- ioc->name);
	5614	+ ioc_err(ioc, "config page: dma_pool_alloc failed\n");
4911	5615	goto out;
4912	5616	}
4913		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
4914		- "config page(0x%p): size(%d)\n",
4915		- ioc->name, ioc->config_page, ioc->config_page_sz));
4916		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
4917		- ioc->name, (unsigned long long)ioc->config_page_dma));
	5617	+
	5618	+ ioc_info(ioc, "config page(0x%p) - dma(0x%llx): size(%d)\n",
	5619	+ ioc->config_page, (unsigned long long)ioc->config_page_dma,
	5620	+ ioc->config_page_sz);
4918	5621	total_sz += ioc->config_page_sz;
4919	5622
4920		- pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
4921		- ioc->name, total_sz/1024);
4922		- pr_info(MPT3SAS_FMT
4923		- "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
4924		- ioc->name, ioc->shost->can_queue, facts->RequestCredit);
4925		- pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
4926		- ioc->name, ioc->shost->sg_tablesize);
	5623	+ ioc_info(ioc, "Allocated physical memory: size(%d kB)\n",
	5624	+ total_sz / 1024);
	5625	+ ioc_info(ioc, "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
	5626	+ ioc->shost->can_queue, facts->RequestCredit);
	5627	+ ioc_info(ioc, "Scatter Gather Elements per IO(%d)\n",
	5628	+ ioc->shost->sg_tablesize);
4927	5629	return 0;
	5630	+
	5631	+try_32bit_dma:
	5632	+ _base_release_memory_pools(ioc);
	5633	+ if (ioc->use_32bit_dma && (ioc->dma_mask > 32)) {
	5634	+ /* Change dma coherent mask to 32 bit and reallocate */
	5635	+ if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
	5636	+ pr_err("Setting 32 bit coherent DMA mask Failed %s\n",
	5637	+ pci_name(ioc->pdev));
	5638	+ return -ENODEV;
	5639	+ }
	5640	+ } else if (_base_reduce_hba_queue_depth(ioc) != 0)
	5641	+ return -ENOMEM;
	5642	+ goto retry_allocation;
4928	5643
4929	5644	out:
4930	5645	return -ENOMEM;
..	..	@@ -4943,7 +5658,7 @@
4943	5658	{
4944	5659	u32 s, sc;
4945	5660
4946		- s = readl(&ioc->chip->Doorbell);
	5661	+ s = ioc->base_readl(&ioc->chip->Doorbell);
4947	5662	sc = s & MPI2_IOC_STATE_MASK;
4948	5663	return cooked ? sc : s;
4949	5664	}
..	..	@@ -4970,6 +5685,8 @@
4970	5685	return 0;
4971	5686	if (count && current_state == MPI2_IOC_STATE_FAULT)
4972	5687	break;
	5688	+ if (count && current_state == MPI2_IOC_STATE_COREDUMP)
	5689	+ break;
4973	5690
4974	5691	usleep_range(1000, 1500);
4975	5692	count++;
..	..	@@ -4979,16 +5696,32 @@
4979	5696	}
4980	5697
4981	5698	/**
	5699	+ * _base_dump_reg_set - This function will print hexdump of register set.
	5700	+ * @ioc: per adapter object
	5701	+ *
	5702	+ * Returns nothing.
	5703	+ */
	5704	+static inline void
	5705	+_base_dump_reg_set(struct MPT3SAS_ADAPTER *ioc)
	5706	+{
	5707	+ unsigned int i, sz = 256;
	5708	+ u32 __iomem reg = (u32 __iomem )ioc->chip;
	5709	+
	5710	+ ioc_info(ioc, "System Register set:\n");
	5711	+ for (i = 0; i < (sz / sizeof(u32)); i++)
	5712	+ pr_info("%08x: %08x\n", (i * 4), readl(&reg[i]));
	5713	+}
	5714	+
	5715	+/**
4982	5716	* _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
4983	5717	* a write to the doorbell)
4984	5718	* @ioc: per adapter object
	5719	+ * @timeout: timeout in seconds
4985	5720	*
4986	5721	* Return: 0 for success, non-zero for failure.
4987	5722	*
4988	5723	* Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
4989	5724	*/
4990		-static int
4991		-_base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
4992	5725
4993	5726	static int
4994	5727	_base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout)
..	..	@@ -4999,11 +5732,11 @@
4999	5732	count = 0;
5000	5733	cntdn = 1000 * timeout;
5001	5734	do {
5002		- int_status = readl(&ioc->chip->HostInterruptStatus);
	5735	+ int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
5003	5736	if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
5004		- dhsprintk(ioc, pr_info(MPT3SAS_FMT
5005		- "%s: successful count(%d), timeout(%d)\n",
5006		- ioc->name, __func__, count, timeout));
	5737	+ dhsprintk(ioc,
	5738	+ ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
	5739	+ __func__, count, timeout));
5007	5740	return 0;
5008	5741	}
5009	5742
..	..	@@ -5011,9 +5744,8 @@
5011	5744	count++;
5012	5745	} while (--cntdn);
5013	5746
5014		- pr_err(MPT3SAS_FMT
5015		- "%s: failed due to timeout count(%d), int_status(%x)!\n",
5016		- ioc->name, __func__, count, int_status);
	5747	+ ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
	5748	+ __func__, count, int_status);
5017	5749	return -EFAULT;
5018	5750	}
5019	5751
..	..	@@ -5026,11 +5758,11 @@
5026	5758	count = 0;
5027	5759	cntdn = 2000 * timeout;
5028	5760	do {
5029		- int_status = readl(&ioc->chip->HostInterruptStatus);
	5761	+ int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
5030	5762	if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
5031		- dhsprintk(ioc, pr_info(MPT3SAS_FMT
5032		- "%s: successful count(%d), timeout(%d)\n",
5033		- ioc->name, __func__, count, timeout));
	5763	+ dhsprintk(ioc,
	5764	+ ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
	5765	+ __func__, count, timeout));
5034	5766	return 0;
5035	5767	}
5036	5768
..	..	@@ -5038,9 +5770,8 @@
5038	5770	count++;
5039	5771	} while (--cntdn);
5040	5772
5041		- pr_err(MPT3SAS_FMT
5042		- "%s: failed due to timeout count(%d), int_status(%x)!\n",
5043		- ioc->name, __func__, count, int_status);
	5773	+ ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
	5774	+ __func__, count, int_status);
5044	5775	return -EFAULT;
5045	5776
5046	5777	}
..	..	@@ -5065,17 +5796,22 @@
5065	5796	count = 0;
5066	5797	cntdn = 1000 * timeout;
5067	5798	do {
5068		- int_status = readl(&ioc->chip->HostInterruptStatus);
	5799	+ int_status = ioc->base_readl(&ioc->chip->HostInterruptStatus);
5069	5800	if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
5070		- dhsprintk(ioc, pr_info(MPT3SAS_FMT
5071		- "%s: successful count(%d), timeout(%d)\n",
5072		- ioc->name, __func__, count, timeout));
	5801	+ dhsprintk(ioc,
	5802	+ ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
	5803	+ __func__, count, timeout));
5073	5804	return 0;
5074	5805	} else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
5075		- doorbell = readl(&ioc->chip->Doorbell);
	5806	+ doorbell = ioc->base_readl(&ioc->chip->Doorbell);
5076	5807	if ((doorbell & MPI2_IOC_STATE_MASK) ==
5077	5808	MPI2_IOC_STATE_FAULT) {
5078		- mpt3sas_base_fault_info(ioc , doorbell);
	5809	+ mpt3sas_print_fault_code(ioc, doorbell);
	5810	+ return -EFAULT;
	5811	+ }
	5812	+ if ((doorbell & MPI2_IOC_STATE_MASK) ==
	5813	+ MPI2_IOC_STATE_COREDUMP) {
	5814	+ mpt3sas_print_coredump_info(ioc, doorbell);
5079	5815	return -EFAULT;
5080	5816	}
5081	5817	} else if (int_status == 0xFFFFFFFF)
..	..	@@ -5086,9 +5822,8 @@
5086	5822	} while (--cntdn);
5087	5823
5088	5824	out:
5089		- pr_err(MPT3SAS_FMT
5090		- "%s: failed due to timeout count(%d), int_status(%x)!\n",
5091		- ioc->name, __func__, count, int_status);
	5825	+ ioc_err(ioc, "%s: failed due to timeout count(%d), int_status(%x)!\n",
	5826	+ __func__, count, int_status);
5092	5827	return -EFAULT;
5093	5828	}
5094	5829
..	..	@@ -5108,11 +5843,11 @@
5108	5843	count = 0;
5109	5844	cntdn = 1000 * timeout;
5110	5845	do {
5111		- doorbell_reg = readl(&ioc->chip->Doorbell);
	5846	+ doorbell_reg = ioc->base_readl(&ioc->chip->Doorbell);
5112	5847	if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
5113		- dhsprintk(ioc, pr_info(MPT3SAS_FMT
5114		- "%s: successful count(%d), timeout(%d)\n",
5115		- ioc->name, __func__, count, timeout));
	5848	+ dhsprintk(ioc,
	5849	+ ioc_info(ioc, "%s: successful count(%d), timeout(%d)\n",
	5850	+ __func__, count, timeout));
5116	5851	return 0;
5117	5852	}
5118	5853
..	..	@@ -5120,9 +5855,8 @@
5120	5855	count++;
5121	5856	} while (--cntdn);
5122	5857
5123		- pr_err(MPT3SAS_FMT
5124		- "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
5125		- ioc->name, __func__, count, doorbell_reg);
	5858	+ ioc_err(ioc, "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
	5859	+ __func__, count, doorbell_reg);
5126	5860	return -EFAULT;
5127	5861	}
5128	5862
..	..	@@ -5139,10 +5873,10 @@
5139	5873	{
5140	5874	u32 ioc_state;
5141	5875	int r = 0;
	5876	+ unsigned long flags;
5142	5877
5143	5878	if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
5144		- pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
5145		- ioc->name, __func__);
	5879	+ ioc_err(ioc, "%s: unknown reset_type\n", __func__);
5146	5880	return -EFAULT;
5147	5881	}
5148	5882
..	..	@@ -5150,7 +5884,7 @@
5150	5884	MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
5151	5885	return -EFAULT;
5152	5886
5153		- pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
	5887	+ ioc_info(ioc, "sending message unit reset !!\n");
5154	5888
5155	5889	writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
5156	5890	&ioc->chip->Doorbell);
..	..	@@ -5158,18 +5892,71 @@
5158	5892	r = -EFAULT;
5159	5893	goto out;
5160	5894	}
	5895	+
5161	5896	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
5162	5897	if (ioc_state) {
5163		- pr_err(MPT3SAS_FMT
5164		- "%s: failed going to ready state (ioc_state=0x%x)\n",
5165		- ioc->name, __func__, ioc_state);
	5898	+ ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
	5899	+ __func__, ioc_state);
5166	5900	r = -EFAULT;
5167	5901	goto out;
5168	5902	}
5169	5903	out:
5170		- pr_info(MPT3SAS_FMT "message unit reset: %s\n",
5171		- ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
	5904	+ if (r != 0) {
	5905	+ ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
	5906	+ spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
	5907	+ /*
	5908	+ * Wait for IOC state CoreDump to clear only during
	5909	+ * HBA initialization & release time.
	5910	+ */
	5911	+ if ((ioc_state & MPI2_IOC_STATE_MASK) ==
	5912	+ MPI2_IOC_STATE_COREDUMP && (ioc->is_driver_loading == 1 \|\|
	5913	+ ioc->fault_reset_work_q == NULL)) {
	5914	+ spin_unlock_irqrestore(
	5915	+ &ioc->ioc_reset_in_progress_lock, flags);
	5916	+ mpt3sas_print_coredump_info(ioc, ioc_state);
	5917	+ mpt3sas_base_wait_for_coredump_completion(ioc,
	5918	+ __func__);
	5919	+ spin_lock_irqsave(
	5920	+ &ioc->ioc_reset_in_progress_lock, flags);
	5921	+ }
	5922	+ spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
	5923	+ }
	5924	+ ioc_info(ioc, "message unit reset: %s\n",
	5925	+ r == 0 ? "SUCCESS" : "FAILED");
5172	5926	return r;
	5927	+}
	5928	+
	5929	+/**
	5930	+ * mpt3sas_wait_for_ioc - IOC's operational state is checked here.
	5931	+ * @ioc: per adapter object
	5932	+ * @timeout: timeout in seconds
	5933	+ *
	5934	+ * Return: Waits up to timeout seconds for the IOC to
	5935	+ * become operational. Returns 0 if IOC is present
	5936	+ * and operational; otherwise returns -EFAULT.
	5937	+ */
	5938	+
	5939	+int
	5940	+mpt3sas_wait_for_ioc(struct MPT3SAS_ADAPTER *ioc, int timeout)
	5941	+{
	5942	+ int wait_state_count = 0;
	5943	+ u32 ioc_state;
	5944	+
	5945	+ do {
	5946	+ ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
	5947	+ if (ioc_state == MPI2_IOC_STATE_OPERATIONAL)
	5948	+ break;
	5949	+ ssleep(1);
	5950	+ ioc_info(ioc, "%s: waiting for operational state(count=%d)\n",
	5951	+ __func__, ++wait_state_count);
	5952	+ } while (--timeout);
	5953	+ if (!timeout) {
	5954	+ ioc_err(ioc, "%s: failed due to ioc not operational\n", __func__);
	5955	+ return -EFAULT;
	5956	+ }
	5957	+ if (wait_state_count)
	5958	+ ioc_info(ioc, "ioc is operational\n");
	5959	+ return 0;
5173	5960	}
5174	5961
5175	5962	/**
..	..	@@ -5193,15 +5980,13 @@
5193	5980	__le32 *mfp;
5194	5981
5195	5982	/* make sure doorbell is not in use */
5196		- if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
5197		- pr_err(MPT3SAS_FMT
5198		- "doorbell is in use (line=%d)\n",
5199		- ioc->name, __LINE__);
	5983	+ if ((ioc->base_readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
	5984	+ ioc_err(ioc, "doorbell is in use (line=%d)\n", __LINE__);
5200	5985	return -EFAULT;
5201	5986	}
5202	5987
5203	5988	/* clear pending doorbell interrupts from previous state changes */
5204		- if (readl(&ioc->chip->HostInterruptStatus) &
	5989	+ if (ioc->base_readl(&ioc->chip->HostInterruptStatus) &
5205	5990	MPI2_HIS_IOC2SYS_DB_STATUS)
5206	5991	writel(0, &ioc->chip->HostInterruptStatus);
5207	5992
..	..	@@ -5211,17 +5996,15 @@
5211	5996	&ioc->chip->Doorbell);
5212	5997
5213	5998	if ((_base_spin_on_doorbell_int(ioc, 5))) {
5214		- pr_err(MPT3SAS_FMT
5215		- "doorbell handshake int failed (line=%d)\n",
5216		- ioc->name, __LINE__);
	5999	+ ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
	6000	+ __LINE__);
5217	6001	return -EFAULT;
5218	6002	}
5219	6003	writel(0, &ioc->chip->HostInterruptStatus);
5220	6004
5221	6005	if ((_base_wait_for_doorbell_ack(ioc, 5))) {
5222		- pr_err(MPT3SAS_FMT
5223		- "doorbell handshake ack failed (line=%d)\n",
5224		- ioc->name, __LINE__);
	6006	+ ioc_err(ioc, "doorbell handshake ack failed (line=%d)\n",
	6007	+ __LINE__);
5225	6008	return -EFAULT;
5226	6009	}
5227	6010
..	..	@@ -5233,53 +6016,51 @@
5233	6016	}
5234	6017
5235	6018	if (failed) {
5236		- pr_err(MPT3SAS_FMT
5237		- "doorbell handshake sending request failed (line=%d)\n",
5238		- ioc->name, __LINE__);
	6019	+ ioc_err(ioc, "doorbell handshake sending request failed (line=%d)\n",
	6020	+ __LINE__);
5239	6021	return -EFAULT;
5240	6022	}
5241	6023
5242	6024	/* now wait for the reply */
5243	6025	if ((_base_wait_for_doorbell_int(ioc, timeout))) {
5244		- pr_err(MPT3SAS_FMT
5245		- "doorbell handshake int failed (line=%d)\n",
5246		- ioc->name, __LINE__);
	6026	+ ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
	6027	+ __LINE__);
5247	6028	return -EFAULT;
5248	6029	}
5249	6030
5250	6031	/* read the first two 16-bits, it gives the total length of the reply */
5251		- reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
	6032	+ reply[0] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell)
5252	6033	& MPI2_DOORBELL_DATA_MASK);
5253	6034	writel(0, &ioc->chip->HostInterruptStatus);
5254	6035	if ((_base_wait_for_doorbell_int(ioc, 5))) {
5255		- pr_err(MPT3SAS_FMT
5256		- "doorbell handshake int failed (line=%d)\n",
5257		- ioc->name, __LINE__);
	6036	+ ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
	6037	+ __LINE__);
5258	6038	return -EFAULT;
5259	6039	}
5260		- reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
	6040	+ reply[1] = le16_to_cpu(ioc->base_readl(&ioc->chip->Doorbell)
5261	6041	& MPI2_DOORBELL_DATA_MASK);
5262	6042	writel(0, &ioc->chip->HostInterruptStatus);
5263	6043
5264	6044	for (i = 2; i < default_reply->MsgLength * 2; i++) {
5265	6045	if ((_base_wait_for_doorbell_int(ioc, 5))) {
5266		- pr_err(MPT3SAS_FMT
5267		- "doorbell handshake int failed (line=%d)\n",
5268		- ioc->name, __LINE__);
	6046	+ ioc_err(ioc, "doorbell handshake int failed (line=%d)\n",
	6047	+ __LINE__);
5269	6048	return -EFAULT;
5270	6049	}
5271	6050	if (i >= reply_bytes/2) /* overflow case */
5272		- readl(&ioc->chip->Doorbell);
	6051	+ ioc->base_readl(&ioc->chip->Doorbell);
5273	6052	else
5274		- reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
	6053	+ reply[i] = le16_to_cpu(
	6054	+ ioc->base_readl(&ioc->chip->Doorbell)
5275	6055	& MPI2_DOORBELL_DATA_MASK);
5276	6056	writel(0, &ioc->chip->HostInterruptStatus);
5277	6057	}
5278	6058
5279	6059	_base_wait_for_doorbell_int(ioc, 5);
5280	6060	if (_base_wait_for_doorbell_not_used(ioc, 5) != 0) {
5281		- dhsprintk(ioc, pr_info(MPT3SAS_FMT
5282		- "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
	6061	+ dhsprintk(ioc,
	6062	+ ioc_info(ioc, "doorbell is in use (line=%d)\n",
	6063	+ __LINE__));
5283	6064	}
5284	6065	writel(0, &ioc->chip->HostInterruptStatus);
5285	6066
..	..	@@ -5287,7 +6068,7 @@
5287	6068	mfp = (__le32 *)reply;
5288	6069	pr_info("\toffset:data\n");
5289	6070	for (i = 0; i < reply_bytes/4; i++)
5290		- pr_info("\t[0x%02x]:%08x\n", i*4,
	6071	+ ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4,
5291	6072	le32_to_cpu(mfp[i]));
5292	6073	}
5293	6074	return 0;
..	..	@@ -5313,45 +6094,27 @@
5313	6094	Mpi2SasIoUnitControlRequest_t *mpi_request)
5314	6095	{
5315	6096	u16 smid;
5316		- u32 ioc_state;
5317	6097	u8 issue_reset = 0;
5318	6098	int rc;
5319	6099	void *request;
5320		- u16 wait_state_count;
5321	6100
5322		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5323		- __func__));
	6101	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5324	6102
5325	6103	mutex_lock(&ioc->base_cmds.mutex);
5326	6104
5327	6105	if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
5328		- pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
5329		- ioc->name, __func__);
	6106	+ ioc_err(ioc, "%s: base_cmd in use\n", __func__);
5330	6107	rc = -EAGAIN;
5331	6108	goto out;
5332	6109	}
5333	6110
5334		- wait_state_count = 0;
5335		- ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
5336		- while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
5337		- if (wait_state_count++ == 10) {
5338		- pr_err(MPT3SAS_FMT
5339		- "%s: failed due to ioc not operational\n",
5340		- ioc->name, __func__);
5341		- rc = -EFAULT;
5342		- goto out;
5343		- }
5344		- ssleep(1);
5345		- ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
5346		- pr_info(MPT3SAS_FMT
5347		- "%s: waiting for operational state(count=%d)\n",
5348		- ioc->name, __func__, wait_state_count);
5349		- }
	6111	+ rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
	6112	+ if (rc)
	6113	+ goto out;
5350	6114
5351	6115	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
5352	6116	if (!smid) {
5353		- pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
5354		- ioc->name, __func__);
	6117	+ ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
5355	6118	rc = -EAGAIN;
5356	6119	goto out;
5357	6120	}
..	..	@@ -5365,7 +6128,7 @@
5365	6128	mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
5366	6129	ioc->ioc_link_reset_in_progress = 1;
5367	6130	init_completion(&ioc->base_cmds.done);
5368		- mpt3sas_base_put_smid_default(ioc, smid);
	6131	+ ioc->put_smid_default(ioc, smid);
5369	6132	wait_for_completion_timeout(&ioc->base_cmds.done,
5370	6133	msecs_to_jiffies(10000));
5371	6134	if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET \|\|
..	..	@@ -5373,10 +6136,9 @@
5373	6136	ioc->ioc_link_reset_in_progress)
5374	6137	ioc->ioc_link_reset_in_progress = 0;
5375	6138	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
5376		- issue_reset =
5377		- mpt3sas_base_check_cmd_timeout(ioc,
5378		- ioc->base_cmds.status, mpi_request,
5379		- sizeof(Mpi2SasIoUnitControlRequest_t)/4);
	6139	+ mpt3sas_check_cmd_timeout(ioc, ioc->base_cmds.status,
	6140	+ mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t)/4,
	6141	+ issue_reset);
5380	6142	goto issue_host_reset;
5381	6143	}
5382	6144	if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
..	..	@@ -5413,46 +6175,27 @@
5413	6175	Mpi2SepReply_t mpi_reply, Mpi2SepRequest_t mpi_request)
5414	6176	{
5415	6177	u16 smid;
5416		- u32 ioc_state;
5417	6178	u8 issue_reset = 0;
5418	6179	int rc;
5419	6180	void *request;
5420		- u16 wait_state_count;
5421	6181
5422		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5423		- __func__));
	6182	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5424	6183
5425	6184	mutex_lock(&ioc->base_cmds.mutex);
5426	6185
5427	6186	if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
5428		- pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
5429		- ioc->name, __func__);
	6187	+ ioc_err(ioc, "%s: base_cmd in use\n", __func__);
5430	6188	rc = -EAGAIN;
5431	6189	goto out;
5432	6190	}
5433	6191
5434		- wait_state_count = 0;
5435		- ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
5436		- while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
5437		- if (wait_state_count++ == 10) {
5438		- pr_err(MPT3SAS_FMT
5439		- "%s: failed due to ioc not operational\n",
5440		- ioc->name, __func__);
5441		- rc = -EFAULT;
5442		- goto out;
5443		- }
5444		- ssleep(1);
5445		- ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
5446		- pr_info(MPT3SAS_FMT
5447		- "%s: waiting for operational state(count=%d)\n",
5448		- ioc->name,
5449		- __func__, wait_state_count);
5450		- }
	6192	+ rc = mpt3sas_wait_for_ioc(ioc, IOC_OPERATIONAL_WAIT_COUNT);
	6193	+ if (rc)
	6194	+ goto out;
5451	6195
5452	6196	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
5453	6197	if (!smid) {
5454		- pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
5455		- ioc->name, __func__);
	6198	+ ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
5456	6199	rc = -EAGAIN;
5457	6200	goto out;
5458	6201	}
..	..	@@ -5461,16 +6204,16 @@
5461	6204	ioc->base_cmds.status = MPT3_CMD_PENDING;
5462	6205	request = mpt3sas_base_get_msg_frame(ioc, smid);
5463	6206	ioc->base_cmds.smid = smid;
	6207	+ memset(request, 0, ioc->request_sz);
5464	6208	memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
5465	6209	init_completion(&ioc->base_cmds.done);
5466		- mpt3sas_base_put_smid_default(ioc, smid);
	6210	+ ioc->put_smid_default(ioc, smid);
5467	6211	wait_for_completion_timeout(&ioc->base_cmds.done,
5468	6212	msecs_to_jiffies(10000));
5469	6213	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
5470		- issue_reset =
5471		- mpt3sas_base_check_cmd_timeout(ioc,
5472		- ioc->base_cmds.status, mpi_request,
5473		- sizeof(Mpi2SepRequest_t)/4);
	6214	+ mpt3sas_check_cmd_timeout(ioc,
	6215	+ ioc->base_cmds.status, mpi_request,
	6216	+ sizeof(Mpi2SepRequest_t)/4, issue_reset);
5474	6217	goto issue_host_reset;
5475	6218	}
5476	6219	if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
..	..	@@ -5506,8 +6249,7 @@
5506	6249	struct mpt3sas_port_facts *pfacts;
5507	6250	int mpi_reply_sz, mpi_request_sz, r;
5508	6251
5509		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5510		- __func__));
	6252	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5511	6253
5512	6254	mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
5513	6255	mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
..	..	@@ -5518,8 +6260,7 @@
5518	6260	(u32 )&mpi_request, mpi_reply_sz, (u16 )&mpi_reply, 5);
5519	6261
5520	6262	if (r != 0) {
5521		- pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
5522		- ioc->name, __func__, r);
	6263	+ ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
5523	6264	return r;
5524	6265	}
5525	6266
..	..	@@ -5547,40 +6288,46 @@
5547	6288	u32 ioc_state;
5548	6289	int rc;
5549	6290
5550		- dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name,
5551		- __func__));
	6291	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5552	6292
5553	6293	if (ioc->pci_error_recovery) {
5554		- dfailprintk(ioc, printk(MPT3SAS_FMT
5555		- "%s: host in pci error recovery\n", ioc->name, __func__));
	6294	+ dfailprintk(ioc,
	6295	+ ioc_info(ioc, "%s: host in pci error recovery\n",
	6296	+ __func__));
5556	6297	return -EFAULT;
5557	6298	}
5558	6299
5559	6300	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5560		- dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
5561		- ioc->name, __func__, ioc_state));
	6301	+ dhsprintk(ioc,
	6302	+ ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
	6303	+ __func__, ioc_state));
5562	6304
5563	6305	if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) \|\|
5564	6306	(ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
5565	6307	return 0;
5566	6308
5567	6309	if (ioc_state & MPI2_DOORBELL_USED) {
5568		- dhsprintk(ioc, printk(MPT3SAS_FMT
5569		- "unexpected doorbell active!\n", ioc->name));
	6310	+ dhsprintk(ioc, ioc_info(ioc, "unexpected doorbell active!\n"));
5570	6311	goto issue_diag_reset;
5571	6312	}
5572	6313
5573	6314	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
5574		- mpt3sas_base_fault_info(ioc, ioc_state &
	6315	+ mpt3sas_print_fault_code(ioc, ioc_state &
5575	6316	MPI2_DOORBELL_DATA_MASK);
5576	6317	goto issue_diag_reset;
	6318	+ } else if ((ioc_state & MPI2_IOC_STATE_MASK) ==
	6319	+ MPI2_IOC_STATE_COREDUMP) {
	6320	+ ioc_info(ioc,
	6321	+ "%s: Skipping the diag reset here. (ioc_state=0x%x)\n",
	6322	+ __func__, ioc_state);
	6323	+ return -EFAULT;
5577	6324	}
5578	6325
5579	6326	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, timeout);
5580	6327	if (ioc_state) {
5581		- dfailprintk(ioc, printk(MPT3SAS_FMT
5582		- "%s: failed going to ready state (ioc_state=0x%x)\n",
5583		- ioc->name, __func__, ioc_state));
	6328	+ dfailprintk(ioc,
	6329	+ ioc_info(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
	6330	+ __func__, ioc_state));
5584	6331	return -EFAULT;
5585	6332	}
5586	6333
..	..	@@ -5603,14 +6350,13 @@
5603	6350	struct mpt3sas_facts *facts;
5604	6351	int mpi_reply_sz, mpi_request_sz, r;
5605	6352
5606		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5607		- __func__));
	6353	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5608	6354
5609	6355	r = _base_wait_for_iocstate(ioc, 10);
5610	6356	if (r) {
5611		- dfailprintk(ioc, printk(MPT3SAS_FMT
5612		- "%s: failed getting to correct state\n",
5613		- ioc->name, __func__));
	6357	+ dfailprintk(ioc,
	6358	+ ioc_info(ioc, "%s: failed getting to correct state\n",
	6359	+ __func__));
5614	6360	return r;
5615	6361	}
5616	6362	mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
..	..	@@ -5621,8 +6367,7 @@
5621	6367	(u32 )&mpi_request, mpi_reply_sz, (u16 )&mpi_reply, 5);
5622	6368
5623	6369	if (r != 0) {
5624		- pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
5625		- ioc->name, __func__, r);
	6370	+ ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
5626	6371	return r;
5627	6372	}
5628	6373
..	..	@@ -5650,6 +6395,9 @@
5650	6395	if ((facts->IOCCapabilities &
5651	6396	MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE) && (!reset_devices))
5652	6397	ioc->rdpq_array_capable = 1;
	6398	+ if ((facts->IOCCapabilities & MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ)
	6399	+ && ioc->is_aero_ioc)
	6400	+ ioc->atomic_desc_capable = 1;
5653	6401	facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
5654	6402	facts->IOCRequestFrameSize =
5655	6403	le16_to_cpu(mpi_reply.IOCRequestFrameSize);
..	..	@@ -5674,20 +6422,20 @@
5674	6422	*/
5675	6423	ioc->page_size = 1 << facts->CurrentHostPageSize;
5676	6424	if (ioc->page_size == 1) {
5677		- pr_info(MPT3SAS_FMT "CurrentHostPageSize is 0: Setting "
5678		- "default host page size to 4k\n", ioc->name);
	6425	+ ioc_info(ioc, "CurrentHostPageSize is 0: Setting default host page size to 4k\n");
5679	6426	ioc->page_size = 1 << MPT3SAS_HOST_PAGE_SIZE_4K;
5680	6427	}
5681		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "CurrentHostPageSize(%d)\n",
5682		- ioc->name, facts->CurrentHostPageSize));
	6428	+ dinitprintk(ioc,
	6429	+ ioc_info(ioc, "CurrentHostPageSize(%d)\n",
	6430	+ facts->CurrentHostPageSize));
5683	6431
5684		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
5685		- "hba queue depth(%d), max chains per io(%d)\n",
5686		- ioc->name, facts->RequestCredit,
5687		- facts->MaxChainDepth));
5688		- dinitprintk(ioc, pr_info(MPT3SAS_FMT
5689		- "request frame size(%d), reply frame size(%d)\n", ioc->name,
5690		- facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
	6432	+ dinitprintk(ioc,
	6433	+ ioc_info(ioc, "hba queue depth(%d), max chains per io(%d)\n",
	6434	+ facts->RequestCredit, facts->MaxChainDepth));
	6435	+ dinitprintk(ioc,
	6436	+ ioc_info(ioc, "request frame size(%d), reply frame size(%d)\n",
	6437	+ facts->IOCRequestFrameSize * 4,
	6438	+ facts->ReplyFrameSize * 4));
5691	6439	return 0;
5692	6440	}
5693	6441
..	..	@@ -5707,8 +6455,7 @@
5707	6455	u16 ioc_status;
5708	6456	u32 reply_post_free_array_sz = 0;
5709	6457
5710		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
5711		- __func__));
	6458	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
5712	6459
5713	6460	memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
5714	6461	mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
..	..	@@ -5752,6 +6499,12 @@
5752	6499	cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
5753	6500	}
5754	6501
	6502	+ /*
	6503	+ * Set the flag to enable CoreDump state feature in IOC firmware.
	6504	+ */
	6505	+ mpi_request.ConfigurationFlags \|=
	6506	+ cpu_to_le16(MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE);
	6507	+
5755	6508	/* This time stamp specifies number of milliseconds
5756	6509	* since epoch ~ midnight January 1, 1970.
5757	6510	*/
..	..	@@ -5763,9 +6516,9 @@
5763	6516	int i;
5764	6517
5765	6518	mfp = (__le32 *)&mpi_request;
5766		- pr_info("\toffset:data\n");
	6519	+ ioc_info(ioc, "\toffset:data\n");
5767	6520	for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
5768		- pr_info("\t[0x%02x]:%08x\n", i*4,
	6521	+ ioc_info(ioc, "\t[0x%02x]:%08x\n", i*4,
5769	6522	le32_to_cpu(mfp[i]));
5770	6523	}
5771	6524
..	..	@@ -5774,15 +6527,14 @@
5774	6527	sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 30);
5775	6528
5776	6529	if (r != 0) {
5777		- pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
5778		- ioc->name, __func__, r);
	6530	+ ioc_err(ioc, "%s: handshake failed (r=%d)\n", __func__, r);
5779	6531	return r;
5780	6532	}
5781	6533
5782	6534	ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
5783	6535	if (ioc_status != MPI2_IOCSTATUS_SUCCESS \|\|
5784	6536	mpi_reply.IOCLogInfo) {
5785		- pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
	6537	+ ioc_err(ioc, "%s: failed\n", __func__);
5786	6538	r = -EIO;
5787	6539	}
5788	6540
..	..	@@ -5853,18 +6605,16 @@
5853	6605	u16 smid;
5854	6606	u16 ioc_status;
5855	6607
5856		- pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
	6608	+ ioc_info(ioc, "sending port enable !!\n");
5857	6609
5858	6610	if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5859		- pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
5860		- ioc->name, __func__);
	6611	+ ioc_err(ioc, "%s: internal command already in use\n", __func__);
5861	6612	return -EAGAIN;
5862	6613	}
5863	6614
5864	6615	smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
5865	6616	if (!smid) {
5866		- pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
5867		- ioc->name, __func__);
	6617	+ ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
5868	6618	return -EAGAIN;
5869	6619	}
5870	6620
..	..	@@ -5875,11 +6625,10 @@
5875	6625	mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
5876	6626
5877	6627	init_completion(&ioc->port_enable_cmds.done);
5878		- mpt3sas_base_put_smid_default(ioc, smid);
	6628	+ ioc->put_smid_default(ioc, smid);
5879	6629	wait_for_completion_timeout(&ioc->port_enable_cmds.done, 300*HZ);
5880	6630	if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
5881		- pr_err(MPT3SAS_FMT "%s: timeout\n",
5882		- ioc->name, __func__);
	6631	+ ioc_err(ioc, "%s: timeout\n", __func__);
5883	6632	_debug_dump_mf(mpi_request,
5884	6633	sizeof(Mpi2PortEnableRequest_t)/4);
5885	6634	if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
..	..	@@ -5892,16 +6641,15 @@
5892	6641	mpi_reply = ioc->port_enable_cmds.reply;
5893	6642	ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
5894	6643	if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5895		- pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
5896		- ioc->name, __func__, ioc_status);
	6644	+ ioc_err(ioc, "%s: failed with (ioc_status=0x%08x)\n",
	6645	+ __func__, ioc_status);
5897	6646	r = -EFAULT;
5898	6647	goto out;
5899	6648	}
5900	6649
5901	6650	out:
5902	6651	ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
5903		- pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
5904		- "SUCCESS" : "FAILED"));
	6652	+ ioc_info(ioc, "port enable: %s\n", r == 0 ? "SUCCESS" : "FAILED");
5905	6653	return r;
5906	6654	}
5907	6655
..	..	@@ -5917,18 +6665,16 @@
5917	6665	Mpi2PortEnableRequest_t *mpi_request;
5918	6666	u16 smid;
5919	6667
5920		- pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
	6668	+ ioc_info(ioc, "sending port enable !!\n");
5921	6669
5922	6670	if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5923		- pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
5924		- ioc->name, __func__);
	6671	+ ioc_err(ioc, "%s: internal command already in use\n", __func__);
5925	6672	return -EAGAIN;
5926	6673	}
5927	6674
5928	6675	smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
5929	6676	if (!smid) {
5930		- pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
5931		- ioc->name, __func__);
	6677	+ ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
5932	6678	return -EAGAIN;
5933	6679	}
5934	6680
..	..	@@ -5938,7 +6684,7 @@
5938	6684	memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
5939	6685	mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
5940	6686
5941		- mpt3sas_base_put_smid_default(ioc, smid);
	6687	+ ioc->put_smid_default(ioc, smid);
5942	6688	return 0;
5943	6689	}
5944	6690
..	..	@@ -6031,19 +6777,16 @@
6031	6777	int r = 0;
6032	6778	int i;
6033	6779
6034		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
6035		- __func__));
	6780	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6036	6781
6037	6782	if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
6038		- pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
6039		- ioc->name, __func__);
	6783	+ ioc_err(ioc, "%s: internal command already in use\n", __func__);
6040	6784	return -EAGAIN;
6041	6785	}
6042	6786
6043	6787	smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
6044	6788	if (!smid) {
6045		- pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
6046		- ioc->name, __func__);
	6789	+ ioc_err(ioc, "%s: failed obtaining a smid\n", __func__);
6047	6790	return -EAGAIN;
6048	6791	}
6049	6792	ioc->base_cmds.status = MPT3_CMD_PENDING;
..	..	@@ -6057,11 +6800,10 @@
6057	6800	mpi_request->EventMasks[i] =
6058	6801	cpu_to_le32(ioc->event_masks[i]);
6059	6802	init_completion(&ioc->base_cmds.done);
6060		- mpt3sas_base_put_smid_default(ioc, smid);
	6803	+ ioc->put_smid_default(ioc, smid);
6061	6804	wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
6062	6805	if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
6063		- pr_err(MPT3SAS_FMT "%s: timeout\n",
6064		- ioc->name, __func__);
	6806	+ ioc_err(ioc, "%s: timeout\n", __func__);
6065	6807	_debug_dump_mf(mpi_request,
6066	6808	sizeof(Mpi2EventNotificationRequest_t)/4);
6067	6809	if (ioc->base_cmds.status & MPT3_CMD_RESET)
..	..	@@ -6069,8 +6811,7 @@
6069	6811	else
6070	6812	r = -ETIME;
6071	6813	} else
6072		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
6073		- ioc->name, __func__));
	6814	+ dinitprintk(ioc, ioc_info(ioc, "%s: complete\n", __func__));
6074	6815	ioc->base_cmds.status = MPT3_CMD_NOT_USED;
6075	6816	return r;
6076	6817	}
..	..	@@ -6126,18 +6867,18 @@
6126	6867	u32 count;
6127	6868	u32 hcb_size;
6128	6869
6129		- pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
	6870	+ ioc_info(ioc, "sending diag reset !!\n");
6130	6871
6131		- drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
6132		- ioc->name));
	6872	+ pci_cfg_access_lock(ioc->pdev);
	6873	+
	6874	+ drsprintk(ioc, ioc_info(ioc, "clear interrupts\n"));
6133	6875
6134	6876	count = 0;
6135	6877	do {
6136	6878	/* Write magic sequence to WriteSequence register
6137	6879	* Loop until in diagnostic mode
6138	6880	*/
6139		- drsprintk(ioc, pr_info(MPT3SAS_FMT
6140		- "write magic sequence\n", ioc->name));
	6881	+ drsprintk(ioc, ioc_info(ioc, "write magic sequence\n"));
6141	6882	writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
6142	6883	writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
6143	6884	writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
..	..	@@ -6149,20 +6890,23 @@
6149	6890	/* wait 100 msec */
6150	6891	msleep(100);
6151	6892
6152		- if (count++ > 20)
	6893	+ if (count++ > 20) {
	6894	+ ioc_info(ioc,
	6895	+ "Stop writing magic sequence after 20 retries\n");
	6896	+ _base_dump_reg_set(ioc);
6153	6897	goto out;
	6898	+ }
6154	6899
6155		- host_diagnostic = readl(&ioc->chip->HostDiagnostic);
6156		- drsprintk(ioc, pr_info(MPT3SAS_FMT
6157		- "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
6158		- ioc->name, count, host_diagnostic));
	6900	+ host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
	6901	+ drsprintk(ioc,
	6902	+ ioc_info(ioc, "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
	6903	+ count, host_diagnostic));
6159	6904
6160	6905	} while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
6161	6906
6162		- hcb_size = readl(&ioc->chip->HCBSize);
	6907	+ hcb_size = ioc->base_readl(&ioc->chip->HCBSize);
6163	6908
6164		- drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
6165		- ioc->name));
	6909	+ drsprintk(ioc, ioc_info(ioc, "diag reset: issued\n"));
6166	6910	writel(host_diagnostic \| MPI2_DIAG_RESET_ADAPTER,
6167	6911	&ioc->chip->HostDiagnostic);
6168	6912
..	..	@@ -6173,10 +6917,14 @@
6173	6917	for (count = 0; count < (300000000 /
6174	6918	MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
6175	6919
6176		- host_diagnostic = readl(&ioc->chip->HostDiagnostic);
	6920	+ host_diagnostic = ioc->base_readl(&ioc->chip->HostDiagnostic);
6177	6921
6178		- if (host_diagnostic == 0xFFFFFFFF)
	6922	+ if (host_diagnostic == 0xFFFFFFFF) {
	6923	+ ioc_info(ioc,
	6924	+ "Invalid host diagnostic register value\n");
	6925	+ _base_dump_reg_set(ioc);
6179	6926	goto out;
	6927	+ }
6180	6928	if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
6181	6929	break;
6182	6930
..	..	@@ -6185,43 +6933,41 @@
6185	6933
6186	6934	if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
6187	6935
6188		- drsprintk(ioc, pr_info(MPT3SAS_FMT
6189		- "restart the adapter assuming the HCB Address points to good F/W\n",
6190		- ioc->name));
	6936	+ drsprintk(ioc,
	6937	+ ioc_info(ioc, "restart the adapter assuming the HCB Address points to good F/W\n"));
6191	6938	host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
6192	6939	host_diagnostic \|= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
6193	6940	writel(host_diagnostic, &ioc->chip->HostDiagnostic);
6194	6941
6195		- drsprintk(ioc, pr_info(MPT3SAS_FMT
6196		- "re-enable the HCDW\n", ioc->name));
	6942	+ drsprintk(ioc, ioc_info(ioc, "re-enable the HCDW\n"));
6197	6943	writel(hcb_size \| MPI2_HCB_SIZE_HCB_ENABLE,
6198	6944	&ioc->chip->HCBSize);
6199	6945	}
6200	6946
6201		- drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
6202		- ioc->name));
	6947	+ drsprintk(ioc, ioc_info(ioc, "restart the adapter\n"));
6203	6948	writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
6204	6949	&ioc->chip->HostDiagnostic);
6205	6950
6206		- drsprintk(ioc, pr_info(MPT3SAS_FMT
6207		- "disable writes to the diagnostic register\n", ioc->name));
	6951	+ drsprintk(ioc,
	6952	+ ioc_info(ioc, "disable writes to the diagnostic register\n"));
6208	6953	writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
6209	6954
6210		- drsprintk(ioc, pr_info(MPT3SAS_FMT
6211		- "Wait for FW to go to the READY state\n", ioc->name));
	6955	+ drsprintk(ioc, ioc_info(ioc, "Wait for FW to go to the READY state\n"));
6212	6956	ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20);
6213	6957	if (ioc_state) {
6214		- pr_err(MPT3SAS_FMT
6215		- "%s: failed going to ready state (ioc_state=0x%x)\n",
6216		- ioc->name, __func__, ioc_state);
	6958	+ ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
	6959	+ __func__, ioc_state);
	6960	+ _base_dump_reg_set(ioc);
6217	6961	goto out;
6218	6962	}
6219	6963
6220		- pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
	6964	+ pci_cfg_access_unlock(ioc->pdev);
	6965	+ ioc_info(ioc, "diag reset: SUCCESS\n");
6221	6966	return 0;
6222	6967
6223	6968	out:
6224		- pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
	6969	+ pci_cfg_access_unlock(ioc->pdev);
	6970	+ ioc_err(ioc, "diag reset: FAILED\n");
6225	6971	return -EFAULT;
6226	6972	}
6227	6973
..	..	@@ -6239,15 +6985,15 @@
6239	6985	int rc;
6240	6986	int count;
6241	6987
6242		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
6243		- __func__));
	6988	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6244	6989
6245	6990	if (ioc->pci_error_recovery)
6246	6991	return 0;
6247	6992
6248	6993	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
6249		- dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
6250		- ioc->name, __func__, ioc_state));
	6994	+ dhsprintk(ioc,
	6995	+ ioc_info(ioc, "%s: ioc_state(0x%08x)\n",
	6996	+ __func__, ioc_state));
6251	6997
6252	6998	/* if in RESET state, it should move to READY state shortly */
6253	6999	count = 0;
..	..	@@ -6255,9 +7001,8 @@
6255	7001	while ((ioc_state & MPI2_IOC_STATE_MASK) !=
6256	7002	MPI2_IOC_STATE_READY) {
6257	7003	if (count++ == 10) {
6258		- pr_err(MPT3SAS_FMT
6259		- "%s: failed going to ready state (ioc_state=0x%x)\n",
6260		- ioc->name, __func__, ioc_state);
	7004	+ ioc_err(ioc, "%s: failed going to ready state (ioc_state=0x%x)\n",
	7005	+ __func__, ioc_state);
6261	7006	return -EFAULT;
6262	7007	}
6263	7008	ssleep(1);
..	..	@@ -6269,15 +7014,30 @@
6269	7014	return 0;
6270	7015
6271	7016	if (ioc_state & MPI2_DOORBELL_USED) {
6272		- dhsprintk(ioc, pr_info(MPT3SAS_FMT
6273		- "unexpected doorbell active!\n",
6274		- ioc->name));
	7017	+ ioc_info(ioc, "unexpected doorbell active!\n");
6275	7018	goto issue_diag_reset;
6276	7019	}
6277	7020
6278	7021	if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
6279		- mpt3sas_base_fault_info(ioc, ioc_state &
	7022	+ mpt3sas_print_fault_code(ioc, ioc_state &
6280	7023	MPI2_DOORBELL_DATA_MASK);
	7024	+ goto issue_diag_reset;
	7025	+ }
	7026	+
	7027	+ if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) {
	7028	+ /*
	7029	+ * if host reset is invoked while watch dog thread is waiting
	7030	+ * for IOC state to be changed to Fault state then driver has
	7031	+ * to wait here for CoreDump state to clear otherwise reset
	7032	+ * will be issued to the FW and FW move the IOC state to
	7033	+ * reset state without copying the FW logs to coredump region.
	7034	+ */
	7035	+ if (ioc->ioc_coredump_loop != MPT3SAS_COREDUMP_LOOP_DONE) {
	7036	+ mpt3sas_print_coredump_info(ioc, ioc_state &
	7037	+ MPI2_DOORBELL_DATA_MASK);
	7038	+ mpt3sas_base_wait_for_coredump_completion(ioc,
	7039	+ __func__);
	7040	+ }
6281	7041	goto issue_diag_reset;
6282	7042	}
6283	7043
..	..	@@ -6304,7 +7064,7 @@
6304	7064	static int
6305	7065	_base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc)
6306	7066	{
6307		- int r, i, index;
	7067	+ int r, i, index, rc;
6308	7068	unsigned long flags;
6309	7069	u32 reply_address;
6310	7070	u16 smid;
..	..	@@ -6315,8 +7075,7 @@
6315	7075	struct adapter_reply_queue *reply_q;
6316	7076	Mpi2ReplyDescriptorsUnion_t *reply_post_free_contig;
6317	7077
6318		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
6319		- __func__));
	7078	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6320	7079
6321	7080	/* clean the delayed target reset list */
6322	7081	list_for_each_entry_safe(delayed_tr, delayed_tr_next,
..	..	@@ -6408,8 +7167,19 @@
6408	7167	skip_init_reply_post_free_queue:
6409	7168
6410	7169	r = _base_send_ioc_init(ioc);
6411		- if (r)
6412		- return r;
	7170	+ if (r) {
	7171	+ /*
	7172	+ * No need to check IOC state for fault state & issue
	7173	+ * diag reset during host reset. This check is need
	7174	+ * only during driver load time.
	7175	+ */
	7176	+ if (!ioc->is_driver_loading)
	7177	+ return r;
	7178	+
	7179	+ rc = _base_check_for_fault_and_issue_reset(ioc);
	7180	+ if (rc \|\| (_base_send_ioc_init(ioc)))
	7181	+ return r;
	7182	+ }
6413	7183
6414	7184	/* initialize reply free host index */
6415	7185	ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
..	..	@@ -6432,7 +7202,7 @@
6432	7202
6433	7203	skip_init_reply_post_host_index:
6434	7204
6435		- _base_unmask_interrupts(ioc);
	7205	+ mpt3sas_base_unmask_interrupts(ioc);
6436	7206
6437	7207	if (ioc->hba_mpi_version_belonged != MPI2_VERSION) {
6438	7208	r = _base_display_fwpkg_version(ioc);
..	..	@@ -6476,13 +7246,12 @@
6476	7246	void
6477	7247	mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
6478	7248	{
6479		- dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
6480		- __func__));
	7249	+ dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6481	7250
6482	7251	/* synchronizing freeing resource with pci_access_mutex lock */
6483	7252	mutex_lock(&ioc->pci_access_mutex);
6484	7253	if (ioc->chip_phys && ioc->chip) {
6485		- _base_mask_interrupts(ioc);
	7254	+ mpt3sas_base_mask_interrupts(ioc);
6486	7255	ioc->shost_recovery = 1;
6487	7256	_base_make_ioc_ready(ioc, SOFT_RESET);
6488	7257	ioc->shost_recovery = 0;
..	..	@@ -6502,11 +7271,10 @@
6502	7271	int
6503	7272	mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
6504	7273	{
6505		- int r, i;
	7274	+ int r, i, rc;
6506	7275	int cpu_id, last_cpu_id = 0;
6507	7276
6508		- dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
6509		- __func__));
	7277	+ dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6510	7278
6511	7279	/* setup cpu_msix_table */
6512	7280	ioc->cpu_count = num_online_cpus();
..	..	@@ -6516,9 +7284,7 @@
6516	7284	ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
6517	7285	ioc->reply_queue_count = 1;
6518	7286	if (!ioc->cpu_msix_table) {
6519		- dfailprintk(ioc, pr_info(MPT3SAS_FMT
6520		- "allocation for cpu_msix_table failed!!!\n",
6521		- ioc->name));
	7287	+ ioc_info(ioc, "Allocation for cpu_msix_table failed!!!\n");
6522	7288	r = -ENOMEM;
6523	7289	goto out_free_resources;
6524	7290	}
..	..	@@ -6527,30 +7293,39 @@
6527	7293	ioc->reply_post_host_index = kcalloc(ioc->cpu_msix_table_sz,
6528	7294	sizeof(resource_size_t *), GFP_KERNEL);
6529	7295	if (!ioc->reply_post_host_index) {
6530		- dfailprintk(ioc, pr_info(MPT3SAS_FMT "allocation "
6531		- "for reply_post_host_index failed!!!\n",
6532		- ioc->name));
	7296	+ ioc_info(ioc, "Allocation for reply_post_host_index failed!!!\n");
6533	7297	r = -ENOMEM;
6534	7298	goto out_free_resources;
6535	7299	}
6536	7300	}
6537	7301
	7302	+ ioc->smp_affinity_enable = smp_affinity_enable;
	7303	+
6538	7304	ioc->rdpq_array_enable_assigned = 0;
6539		- ioc->dma_mask = 0;
	7305	+ ioc->use_32bit_dma = false;
	7306	+ ioc->dma_mask = 64;
	7307	+ if (ioc->is_aero_ioc)
	7308	+ ioc->base_readl = &_base_readl_aero;
	7309	+ else
	7310	+ ioc->base_readl = &_base_readl;
6540	7311	r = mpt3sas_base_map_resources(ioc);
6541	7312	if (r)
6542	7313	goto out_free_resources;
6543	7314
6544	7315	pci_set_drvdata(ioc->pdev, ioc->shost);
6545	7316	r = _base_get_ioc_facts(ioc);
6546		- if (r)
6547		- goto out_free_resources;
	7317	+ if (r) {
	7318	+ rc = _base_check_for_fault_and_issue_reset(ioc);
	7319	+ if (rc \|\| (_base_get_ioc_facts(ioc)))
	7320	+ goto out_free_resources;
	7321	+ }
6548	7322
6549	7323	switch (ioc->hba_mpi_version_belonged) {
6550	7324	case MPI2_VERSION:
6551	7325	ioc->build_sg_scmd = &_base_build_sg_scmd;
6552	7326	ioc->build_sg = &_base_build_sg;
6553	7327	ioc->build_zero_len_sge = &_base_build_zero_len_sge;
	7328	+ ioc->get_msix_index_for_smlio = &_base_get_msix_index;
6554	7329	break;
6555	7330	case MPI25_VERSION:
6556	7331	case MPI26_VERSION:
..	..	@@ -6565,15 +7340,30 @@
6565	7340	ioc->build_nvme_prp = &_base_build_nvme_prp;
6566	7341	ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
6567	7342	ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
6568		-
	7343	+ if (ioc->high_iops_queues)
	7344	+ ioc->get_msix_index_for_smlio =
	7345	+ &_base_get_high_iops_msix_index;
	7346	+ else
	7347	+ ioc->get_msix_index_for_smlio = &_base_get_msix_index;
6569	7348	break;
6570	7349	}
6571		-
6572		- if (ioc->is_mcpu_endpoint)
6573		- ioc->put_smid_scsi_io = &_base_put_smid_mpi_ep_scsi_io;
6574		- else
6575		- ioc->put_smid_scsi_io = &_base_put_smid_scsi_io;
6576		-
	7350	+ if (ioc->atomic_desc_capable) {
	7351	+ ioc->put_smid_default = &_base_put_smid_default_atomic;
	7352	+ ioc->put_smid_scsi_io = &_base_put_smid_scsi_io_atomic;
	7353	+ ioc->put_smid_fast_path =
	7354	+ &_base_put_smid_fast_path_atomic;
	7355	+ ioc->put_smid_hi_priority =
	7356	+ &_base_put_smid_hi_priority_atomic;
	7357	+ } else {
	7358	+ ioc->put_smid_default = &_base_put_smid_default;
	7359	+ ioc->put_smid_fast_path = &_base_put_smid_fast_path;
	7360	+ ioc->put_smid_hi_priority = &_base_put_smid_hi_priority;
	7361	+ if (ioc->is_mcpu_endpoint)
	7362	+ ioc->put_smid_scsi_io =
	7363	+ &_base_put_smid_mpi_ep_scsi_io;
	7364	+ else
	7365	+ ioc->put_smid_scsi_io = &_base_put_smid_scsi_io;
	7366	+ }
6577	7367	/*
6578	7368	* These function pointers for other requests that don't
6579	7369	* the require IEEE scatter gather elements.
..	..	@@ -6596,14 +7386,23 @@
6596	7386
6597	7387	for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
6598	7388	r = _base_get_port_facts(ioc, i);
6599		- if (r)
6600		- goto out_free_resources;
	7389	+ if (r) {
	7390	+ rc = _base_check_for_fault_and_issue_reset(ioc);
	7391	+ if (rc \|\| (_base_get_port_facts(ioc, i)))
	7392	+ goto out_free_resources;
	7393	+ }
6601	7394	}
6602	7395
6603	7396	r = _base_allocate_memory_pools(ioc);
6604	7397	if (r)
6605	7398	goto out_free_resources;
6606	7399
	7400	+ if (irqpoll_weight > 0)
	7401	+ ioc->thresh_hold = irqpoll_weight;
	7402	+ else
	7403	+ ioc->thresh_hold = ioc->hba_queue_depth/4;
	7404	+
	7405	+ _base_init_irqpolls(ioc);
6607	7406	init_waitqueue_head(&ioc->reset_wq);
6608	7407
6609	7408	/* allocate memory pd handle bitmask list */
..	..	@@ -6717,7 +7516,15 @@
6717	7516	if (r)
6718	7517	goto out_free_resources;
6719	7518
	7519	+ /*
	7520	+ * Copy current copy of IOCFacts in prev_fw_facts
	7521	+ * and it will be used during online firmware upgrade.
	7522	+ */
	7523	+ memcpy(&ioc->prev_fw_facts, &ioc->facts,
	7524	+ sizeof(struct mpt3sas_facts));
	7525	+
6720	7526	ioc->non_operational_loop = 0;
	7527	+ ioc->ioc_coredump_loop = 0;
6721	7528	ioc->got_task_abort_from_ioctl = 0;
6722	7529	return 0;
6723	7530
..	..	@@ -6762,8 +7569,7 @@
6762	7569	void
6763	7570	mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
6764	7571	{
6765		- dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
6766		- __func__));
	7572	+ dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
6767	7573
6768	7574	mpt3sas_base_stop_watchdog(ioc);
6769	7575	mpt3sas_base_free_resources(ioc);
..	..	@@ -6796,20 +7602,18 @@
6796	7602	{
6797	7603	mpt3sas_scsih_pre_reset_handler(ioc);
6798	7604	mpt3sas_ctl_pre_reset_handler(ioc);
6799		- dtmprintk(ioc, pr_info(MPT3SAS_FMT
6800		- "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
	7605	+ dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_PRE_RESET\n", __func__));
6801	7606	}
6802	7607
6803	7608	/**
6804		- * _base_after_reset_handler - after reset handler
	7609	+ * _base_clear_outstanding_mpt_commands - clears outstanding mpt commands
6805	7610	* @ioc: per adapter object
6806	7611	*/
6807		-static void _base_after_reset_handler(struct MPT3SAS_ADAPTER *ioc)
	7612	+static void
	7613	+_base_clear_outstanding_mpt_commands(struct MPT3SAS_ADAPTER *ioc)
6808	7614	{
6809		- mpt3sas_scsih_after_reset_handler(ioc);
6810		- mpt3sas_ctl_after_reset_handler(ioc);
6811		- dtmprintk(ioc, pr_info(MPT3SAS_FMT
6812		- "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
	7615	+ dtmprintk(ioc,
	7616	+ ioc_info(ioc, "%s: clear outstanding mpt cmds\n", __func__));
6813	7617	if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
6814	7618	ioc->transport_cmds.status \|= MPT3_CMD_RESET;
6815	7619	mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
..	..	@@ -6843,6 +7647,17 @@
6843	7647	}
6844	7648
6845	7649	/**
	7650	+ * _base_clear_outstanding_commands - clear all outstanding commands
	7651	+ * @ioc: per adapter object
	7652	+ */
	7653	+static void _base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc)
	7654	+{
	7655	+ mpt3sas_scsih_clear_outstanding_scsi_tm_commands(ioc);
	7656	+ mpt3sas_ctl_clear_outstanding_ioctls(ioc);
	7657	+ _base_clear_outstanding_mpt_commands(ioc);
	7658	+}
	7659	+
	7660	+/**
6846	7661	* _base_reset_done_handler - reset done handler
6847	7662	* @ioc: per adapter object
6848	7663	*/
..	..	@@ -6850,8 +7665,7 @@
6850	7665	{
6851	7666	mpt3sas_scsih_reset_done_handler(ioc);
6852	7667	mpt3sas_ctl_reset_done_handler(ioc);
6853		- dtmprintk(ioc, pr_info(MPT3SAS_FMT
6854		- "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
	7668	+ dtmprintk(ioc, ioc_info(ioc, "%s: MPT3_IOC_DONE_RESET\n", __func__));
6855	7669	}
6856	7670
6857	7671	/**
..	..	@@ -6883,6 +7697,85 @@
6883	7697	}
6884	7698
6885	7699	/**
	7700	+ * _base_check_ioc_facts_changes - Look for increase/decrease of IOCFacts
	7701	+ * attributes during online firmware upgrade and update the corresponding
	7702	+ * IOC variables accordingly.
	7703	+ *
	7704	+ * @ioc: Pointer to MPT_ADAPTER structure
	7705	+ */
	7706	+static int
	7707	+_base_check_ioc_facts_changes(struct MPT3SAS_ADAPTER *ioc)
	7708	+{
	7709	+ u16 pd_handles_sz;
	7710	+ void pd_handles = NULL, blocking_handles = NULL;
	7711	+ void pend_os_device_add = NULL, device_remove_in_progress = NULL;
	7712	+ struct mpt3sas_facts *old_facts = &ioc->prev_fw_facts;
	7713	+
	7714	+ if (ioc->facts.MaxDevHandle > old_facts->MaxDevHandle) {
	7715	+ pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
	7716	+ if (ioc->facts.MaxDevHandle % 8)
	7717	+ pd_handles_sz++;
	7718	+
	7719	+ pd_handles = krealloc(ioc->pd_handles, pd_handles_sz,
	7720	+ GFP_KERNEL);
	7721	+ if (!pd_handles) {
	7722	+ ioc_info(ioc,
	7723	+ "Unable to allocate the memory for pd_handles of sz: %d\n",
	7724	+ pd_handles_sz);
	7725	+ return -ENOMEM;
	7726	+ }
	7727	+ memset(pd_handles + ioc->pd_handles_sz, 0,
	7728	+ (pd_handles_sz - ioc->pd_handles_sz));
	7729	+ ioc->pd_handles = pd_handles;
	7730	+
	7731	+ blocking_handles = krealloc(ioc->blocking_handles,
	7732	+ pd_handles_sz, GFP_KERNEL);
	7733	+ if (!blocking_handles) {
	7734	+ ioc_info(ioc,
	7735	+ "Unable to allocate the memory for "
	7736	+ "blocking_handles of sz: %d\n",
	7737	+ pd_handles_sz);
	7738	+ return -ENOMEM;
	7739	+ }
	7740	+ memset(blocking_handles + ioc->pd_handles_sz, 0,
	7741	+ (pd_handles_sz - ioc->pd_handles_sz));
	7742	+ ioc->blocking_handles = blocking_handles;
	7743	+ ioc->pd_handles_sz = pd_handles_sz;
	7744	+
	7745	+ pend_os_device_add = krealloc(ioc->pend_os_device_add,
	7746	+ pd_handles_sz, GFP_KERNEL);
	7747	+ if (!pend_os_device_add) {
	7748	+ ioc_info(ioc,
	7749	+ "Unable to allocate the memory for pend_os_device_add of sz: %d\n",
	7750	+ pd_handles_sz);
	7751	+ return -ENOMEM;
	7752	+ }
	7753	+ memset(pend_os_device_add + ioc->pend_os_device_add_sz, 0,
	7754	+ (pd_handles_sz - ioc->pend_os_device_add_sz));
	7755	+ ioc->pend_os_device_add = pend_os_device_add;
	7756	+ ioc->pend_os_device_add_sz = pd_handles_sz;
	7757	+
	7758	+ device_remove_in_progress = krealloc(
	7759	+ ioc->device_remove_in_progress, pd_handles_sz, GFP_KERNEL);
	7760	+ if (!device_remove_in_progress) {
	7761	+ ioc_info(ioc,
	7762	+ "Unable to allocate the memory for "
	7763	+ "device_remove_in_progress of sz: %d\n "
	7764	+ , pd_handles_sz);
	7765	+ return -ENOMEM;
	7766	+ }
	7767	+ memset(device_remove_in_progress +
	7768	+ ioc->device_remove_in_progress_sz, 0,
	7769	+ (pd_handles_sz - ioc->device_remove_in_progress_sz));
	7770	+ ioc->device_remove_in_progress = device_remove_in_progress;
	7771	+ ioc->device_remove_in_progress_sz = pd_handles_sz;
	7772	+ }
	7773	+
	7774	+ memcpy(&ioc->prev_fw_facts, &ioc->facts, sizeof(struct mpt3sas_facts));
	7775	+ return 0;
	7776	+}
	7777	+
	7778	+/**
6886	7779	* mpt3sas_base_hard_reset_handler - reset controller
6887	7780	* @ioc: Pointer to MPT_ADAPTER structure
6888	7781	* @type: FORCE_BIG_HAMMER or SOFT_RESET
..	..	@@ -6898,12 +7791,10 @@
6898	7791	u32 ioc_state;
6899	7792	u8 is_fault = 0, is_trigger = 0;
6900	7793
6901		- dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
6902		- __func__));
	7794	+ dtmprintk(ioc, ioc_info(ioc, "%s: enter\n", __func__));
6903	7795
6904	7796	if (ioc->pci_error_recovery) {
6905		- pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
6906		- ioc->name, __func__);
	7797	+ ioc_err(ioc, "%s: pci error recovery reset\n", __func__);
6907	7798	r = 0;
6908	7799	goto out_unlocked;
6909	7800	}
..	..	@@ -6924,16 +7815,18 @@
6924	7815	MPT3_DIAG_BUFFER_IS_RELEASED))) {
6925	7816	is_trigger = 1;
6926	7817	ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
6927		- if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
	7818	+ if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT \|\|
	7819	+ (ioc_state & MPI2_IOC_STATE_MASK) ==
	7820	+ MPI2_IOC_STATE_COREDUMP)
6928	7821	is_fault = 1;
6929	7822	}
6930	7823	_base_pre_reset_handler(ioc);
6931	7824	mpt3sas_wait_for_commands_to_complete(ioc);
6932		- _base_mask_interrupts(ioc);
	7825	+ mpt3sas_base_mask_interrupts(ioc);
6933	7826	r = _base_make_ioc_ready(ioc, type);
6934	7827	if (r)
6935	7828	goto out;
6936		- _base_after_reset_handler(ioc);
	7829	+ _base_clear_outstanding_commands(ioc);
6937	7830
6938	7831	/* If this hard reset is called while port enable is active, then
6939	7832	* there is no reason to call make_ioc_operational
..	..	@@ -6947,6 +7840,13 @@
6947	7840	if (r)
6948	7841	goto out;
6949	7842
	7843	+ r = _base_check_ioc_facts_changes(ioc);
	7844	+ if (r) {
	7845	+ ioc_info(ioc,
	7846	+ "Some of the parameters got changed in this new firmware"
	7847	+ " image and it requires system reboot\n");
	7848	+ goto out;
	7849	+ }
6950	7850	if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
6951	7851	panic("%s: Issue occurred with flashing controller firmware."
6952	7852	"Please reboot the system and ensure that the correct"
..	..	@@ -6957,8 +7857,7 @@
6957	7857	_base_reset_done_handler(ioc);
6958	7858
6959	7859	out:
6960		- dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
6961		- ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
	7860	+ ioc_info(ioc, "%s: %s\n", __func__, r == 0 ? "SUCCESS" : "FAILED");
6962	7861
6963	7862	spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
6964	7863	ioc->shost_recovery = 0;
..	..	@@ -6974,7 +7873,6 @@
6974	7873	mpt3sas_trigger_master(ioc,
6975	7874	MASTER_TRIGGER_ADAPTER_RESET);
6976	7875	}
6977		- dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
6978		- __func__));
	7876	+ dtmprintk(ioc, ioc_info(ioc, "%s: exit\n", __func__));
6979	7877	return r;
6980	7878	}