.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * axp288_charger.c - X-power AXP288 PMIC Charger driver |
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3 | 4 | * |
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4 | 5 | * Copyright (C) 2016-2017 Hans de Goede <hdegoede@redhat.com> |
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5 | 6 | * Copyright (C) 2014 Intel Corporation |
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6 | 7 | * Author: Ramakrishna Pallala <ramakrishna.pallala@intel.com> |
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7 | | - * |
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8 | | - * This program is free software; you can redistribute it and/or modify |
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9 | | - * it under the terms of the GNU General Public License version 2 as |
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10 | | - * published by the Free Software Foundation. |
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11 | | - * |
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12 | | - * This program is distributed in the hope that it will be useful, |
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13 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 | | - * GNU General Public License for more details. |
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16 | 8 | */ |
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17 | 9 | |
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18 | 10 | #include <linux/acpi.h> |
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| 11 | +#include <linux/bitops.h> |
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19 | 12 | #include <linux/module.h> |
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20 | 13 | #include <linux/device.h> |
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21 | 14 | #include <linux/regmap.h> |
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.. | .. |
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30 | 23 | #include <linux/extcon.h> |
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31 | 24 | #include <linux/dmi.h> |
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32 | 25 | |
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33 | | -#define PS_STAT_VBUS_TRIGGER (1 << 0) |
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34 | | -#define PS_STAT_BAT_CHRG_DIR (1 << 2) |
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35 | | -#define PS_STAT_VBAT_ABOVE_VHOLD (1 << 3) |
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36 | | -#define PS_STAT_VBUS_VALID (1 << 4) |
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37 | | -#define PS_STAT_VBUS_PRESENT (1 << 5) |
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| 26 | +#define PS_STAT_VBUS_TRIGGER BIT(0) |
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| 27 | +#define PS_STAT_BAT_CHRG_DIR BIT(2) |
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| 28 | +#define PS_STAT_VBAT_ABOVE_VHOLD BIT(3) |
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| 29 | +#define PS_STAT_VBUS_VALID BIT(4) |
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| 30 | +#define PS_STAT_VBUS_PRESENT BIT(5) |
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38 | 31 | |
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39 | | -#define CHRG_STAT_BAT_SAFE_MODE (1 << 3) |
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40 | | -#define CHRG_STAT_BAT_VALID (1 << 4) |
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41 | | -#define CHRG_STAT_BAT_PRESENT (1 << 5) |
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42 | | -#define CHRG_STAT_CHARGING (1 << 6) |
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43 | | -#define CHRG_STAT_PMIC_OTP (1 << 7) |
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| 32 | +#define CHRG_STAT_BAT_SAFE_MODE BIT(3) |
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| 33 | +#define CHRG_STAT_BAT_VALID BIT(4) |
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| 34 | +#define CHRG_STAT_BAT_PRESENT BIT(5) |
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| 35 | +#define CHRG_STAT_CHARGING BIT(6) |
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| 36 | +#define CHRG_STAT_PMIC_OTP BIT(7) |
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44 | 37 | |
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45 | 38 | #define VBUS_ISPOUT_CUR_LIM_MASK 0x03 |
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46 | 39 | #define VBUS_ISPOUT_CUR_LIM_BIT_POS 0 |
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.. | .. |
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48 | 41 | #define VBUS_ISPOUT_CUR_LIM_1500MA 0x1 /* 1500mA */ |
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49 | 42 | #define VBUS_ISPOUT_CUR_LIM_2000MA 0x2 /* 2000mA */ |
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50 | 43 | #define VBUS_ISPOUT_CUR_NO_LIM 0x3 /* 2500mA */ |
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51 | | -#define VBUS_ISPOUT_VHOLD_SET_MASK 0x31 |
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| 44 | +#define VBUS_ISPOUT_VHOLD_SET_MASK 0x38 |
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52 | 45 | #define VBUS_ISPOUT_VHOLD_SET_BIT_POS 0x3 |
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53 | 46 | #define VBUS_ISPOUT_VHOLD_SET_OFFSET 4000 /* 4000mV */ |
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54 | 47 | #define VBUS_ISPOUT_VHOLD_SET_LSB_RES 100 /* 100mV */ |
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55 | | -#define VBUS_ISPOUT_VHOLD_SET_4300MV 0x3 /* 4300mV */ |
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56 | | -#define VBUS_ISPOUT_VBUS_PATH_DIS (1 << 7) |
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| 48 | +#define VBUS_ISPOUT_VHOLD_SET_4400MV 0x4 /* 4400mV */ |
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| 49 | +#define VBUS_ISPOUT_VBUS_PATH_DIS BIT(7) |
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57 | 50 | |
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58 | 51 | #define CHRG_CCCV_CC_MASK 0xf /* 4 bits */ |
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59 | 52 | #define CHRG_CCCV_CC_BIT_POS 0 |
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60 | 53 | #define CHRG_CCCV_CC_OFFSET 200 /* 200mA */ |
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61 | 54 | #define CHRG_CCCV_CC_LSB_RES 200 /* 200mA */ |
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62 | | -#define CHRG_CCCV_ITERM_20P (1 << 4) /* 20% of CC */ |
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| 55 | +#define CHRG_CCCV_ITERM_20P BIT(4) /* 20% of CC */ |
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63 | 56 | #define CHRG_CCCV_CV_MASK 0x60 /* 2 bits */ |
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64 | 57 | #define CHRG_CCCV_CV_BIT_POS 5 |
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65 | 58 | #define CHRG_CCCV_CV_4100MV 0x0 /* 4.10V */ |
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66 | 59 | #define CHRG_CCCV_CV_4150MV 0x1 /* 4.15V */ |
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67 | 60 | #define CHRG_CCCV_CV_4200MV 0x2 /* 4.20V */ |
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68 | 61 | #define CHRG_CCCV_CV_4350MV 0x3 /* 4.35V */ |
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69 | | -#define CHRG_CCCV_CHG_EN (1 << 7) |
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| 62 | +#define CHRG_CCCV_CHG_EN BIT(7) |
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70 | 63 | |
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71 | 64 | #define CNTL2_CC_TIMEOUT_MASK 0x3 /* 2 bits */ |
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72 | 65 | #define CNTL2_CC_TIMEOUT_OFFSET 6 /* 6 Hrs */ |
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73 | 66 | #define CNTL2_CC_TIMEOUT_LSB_RES 2 /* 2 Hrs */ |
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74 | 67 | #define CNTL2_CC_TIMEOUT_12HRS 0x3 /* 12 Hrs */ |
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75 | | -#define CNTL2_CHGLED_TYPEB (1 << 4) |
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76 | | -#define CNTL2_CHG_OUT_TURNON (1 << 5) |
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| 68 | +#define CNTL2_CHGLED_TYPEB BIT(4) |
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| 69 | +#define CNTL2_CHG_OUT_TURNON BIT(5) |
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77 | 70 | #define CNTL2_PC_TIMEOUT_MASK 0xC0 |
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78 | 71 | #define CNTL2_PC_TIMEOUT_OFFSET 40 /* 40 mins */ |
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79 | 72 | #define CNTL2_PC_TIMEOUT_LSB_RES 10 /* 10 mins */ |
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80 | 73 | #define CNTL2_PC_TIMEOUT_70MINS 0x3 |
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81 | 74 | |
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82 | | -#define CHRG_ILIM_TEMP_LOOP_EN (1 << 3) |
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| 75 | +#define CHRG_ILIM_TEMP_LOOP_EN BIT(3) |
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83 | 76 | #define CHRG_VBUS_ILIM_MASK 0xf0 |
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84 | 77 | #define CHRG_VBUS_ILIM_BIT_POS 4 |
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85 | 78 | #define CHRG_VBUS_ILIM_100MA 0x0 /* 100mA */ |
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.. | .. |
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95 | 88 | #define CHRG_VLTFC_0C 0xA5 /* 0 DegC */ |
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96 | 89 | #define CHRG_VHTFC_45C 0x1F /* 45 DegC */ |
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97 | 90 | |
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98 | | -#define FG_CNTL_OCV_ADJ_EN (1 << 3) |
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| 91 | +#define FG_CNTL_OCV_ADJ_EN BIT(3) |
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99 | 92 | |
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100 | 93 | #define CV_4100MV 4100 /* 4100mV */ |
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101 | 94 | #define CV_4150MV 4150 /* 4150mV */ |
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.. | .. |
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751 | 744 | ret = axp288_charger_vbus_path_select(info, true); |
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752 | 745 | if (ret < 0) |
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753 | 746 | return ret; |
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| 747 | + } else { |
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| 748 | + /* Set Vhold to the factory default / recommended 4.4V */ |
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| 749 | + val = VBUS_ISPOUT_VHOLD_SET_4400MV << VBUS_ISPOUT_VHOLD_SET_BIT_POS; |
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| 750 | + ret = regmap_update_bits(info->regmap, AXP20X_VBUS_IPSOUT_MGMT, |
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| 751 | + VBUS_ISPOUT_VHOLD_SET_MASK, val); |
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| 752 | + if (ret < 0) { |
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| 753 | + dev_err(&info->pdev->dev, "register(%x) write error(%d)\n", |
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| 754 | + AXP20X_VBUS_IPSOUT_MGMT, ret); |
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| 755 | + return ret; |
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| 756 | + } |
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754 | 757 | } |
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755 | 758 | |
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756 | 759 | /* Read current charge voltage and current limit */ |
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.. | .. |
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893 | 896 | /* Register charger interrupts */ |
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894 | 897 | for (i = 0; i < CHRG_INTR_END; i++) { |
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895 | 898 | pirq = platform_get_irq(info->pdev, i); |
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896 | | - if (pirq < 0) { |
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897 | | - dev_err(&pdev->dev, "Failed to get IRQ: %d\n", pirq); |
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| 899 | + if (pirq < 0) |
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898 | 900 | return pirq; |
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899 | | - } |
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| 901 | + |
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900 | 902 | info->irq[i] = regmap_irq_get_virq(info->regmap_irqc, pirq); |
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901 | 903 | if (info->irq[i] < 0) { |
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902 | 904 | dev_warn(&info->pdev->dev, |
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