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hc
2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/power/reset/at91-reset.c
....@@ -35,6 +35,7 @@
3535 
3636 #define AT91_RSTC_MR	0x08		/* Reset Controller Mode Register */
3737 #define AT91_RSTC_URSTEN	BIT(0)		/* User Reset Enable */
38
+#define AT91_RSTC_URSTASYNC	BIT(2)		/* User Reset Asynchronous Control */
3839 #define AT91_RSTC_URSTIEN	BIT(4)		/* User Reset Interrupt Enable */
3940 #define AT91_RSTC_ERSTL		GENMASK(11, 8)	/* External Reset Length */
4041 
....@@ -44,109 +45,68 @@
4445 	RESET_TYPE_WATCHDOG	= 2,
4546 	RESET_TYPE_SOFTWARE	= 3,
4647 	RESET_TYPE_USER		= 4,
48
+	RESET_TYPE_CPU_FAIL	= 6,
49
+	RESET_TYPE_XTAL_FAIL	= 7,
50
+	RESET_TYPE_ULP2		= 8,
4751 };
4852 
49
-static void __iomem *at91_ramc_base[2], *at91_rstc_base;
50
-static struct clk *sclk;
53
+struct at91_reset {
54
+	void __iomem *rstc_base;
55
+	void __iomem *ramc_base[2];
56
+	struct clk *sclk;
57
+	struct notifier_block nb;
58
+	u32 args;
59
+	u32 ramc_lpr;
60
+};
5161 
5262 /*
5363 * unless the SDRAM is cleanly shutdown before we hit the
5464 * reset register it can be left driving the data bus and
5565 * killing the chance of a subsequent boot from NAND
5666 */
57
-static int at91sam9260_restart(struct notifier_block *this, unsigned long mode,
58
-			       void *cmd)
67
+static int at91_reset(struct notifier_block *this, unsigned long mode,
68
+		      void *cmd)
5969 {
70
+	struct at91_reset *reset = container_of(this, struct at91_reset, nb);
71
+
6072 	asm volatile(
61
-		/* Align to cache lines */
62
-		".balign 32\n\t"
63
-
64
-		/* Disable SDRAM accesses */
65
-		"str	%2, [%0, #" __stringify(AT91_SDRAMC_TR) "]\n\t"
66
-
67
-		/* Power down SDRAM */
68
-		"str	%3, [%0, #" __stringify(AT91_SDRAMC_LPR) "]\n\t"
69
-
70
-		/* Reset CPU */
71
-		"str	%4, [%1, #" __stringify(AT91_RSTC_CR) "]\n\t"
72
-
73
-		"b	.\n\t"
74
-		:
75
-		: "r" (at91_ramc_base[0]),
76
-		  "r" (at91_rstc_base),
77
-		  "r" (1),
78
-		  "r" cpu_to_le32(AT91_SDRAMC_LPCB_POWER_DOWN),
79
-		  "r" cpu_to_le32(AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST));
80
-
81
-	return NOTIFY_DONE;
82
-}
83
-
84
-static int at91sam9g45_restart(struct notifier_block *this, unsigned long mode,
85
-			       void *cmd)
86
-{
87
-	asm volatile(
88
-		/*
89
-		 * Test wether we have a second RAM controller to care
90
-		 * about.
91
-		 *
92
-		 * First, test that we can dereference the virtual address.
93
-		 */
94
-		"cmp	%1, #0\n\t"
95
-		"beq	1f\n\t"
96
-
97
-		/* Then, test that the RAM controller is enabled */
98
-		"ldr	r0, [%1]\n\t"
99
-		"cmp	r0, #0\n\t"
100
-
10173 		/* Align to cache lines */
10274 		".balign 32\n\t"
10375 
10476 		/* Disable SDRAM0 accesses */
105
-		"1:	str	%3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
77
+		"	tst	%0, #0\n\t"
78
+		"	beq	1f\n\t"
79
+		"	str	%3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
10680 		/* Power down SDRAM0 */
107
-		"	str	%4, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
81
+		"	str	%4, [%0, %6]\n\t"
10882 		/* Disable SDRAM1 accesses */
83
+		"1:	tst	%1, #0\n\t"
84
+		"	beq	2f\n\t"
10985 		"	strne	%3, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t"
11086 		/* Power down SDRAM1 */
111
-		"	strne	%4, [%1, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
87
+		"	strne	%4, [%1, %6]\n\t"
11288 		/* Reset CPU */
113
-		"	str	%5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t"
89
+		"2:	str	%5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t"
11490 
11591 		"	b	.\n\t"
11692 		:
117
-		: "r" (at91_ramc_base[0]),
118
-		  "r" (at91_ramc_base[1]),
119
-		  "r" (at91_rstc_base),
93
+		: "r" (reset->ramc_base[0]),
94
+		  "r" (reset->ramc_base[1]),
95
+		  "r" (reset->rstc_base),
12096 		  "r" (1),
12197 		  "r" cpu_to_le32(AT91_DDRSDRC_LPCB_POWER_DOWN),
122
-		  "r" cpu_to_le32(AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST)
123
-		: "r0");
98
+		  "r" (reset->args),
99
+		  "r" (reset->ramc_lpr)
100
+		: "r4");
124101 
125102 	return NOTIFY_DONE;
126103 }
127104 
128
-static int sama5d3_restart(struct notifier_block *this, unsigned long mode,
129
-			   void *cmd)
130
-{
131
-	writel(cpu_to_le32(AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST),
132
-	       at91_rstc_base);
133
-
134
-	return NOTIFY_DONE;
135
-}
136
-
137
-static int samx7_restart(struct notifier_block *this, unsigned long mode,
138
-			 void *cmd)
139
-{
140
-	writel(cpu_to_le32(AT91_RSTC_KEY | AT91_RSTC_PROCRST),
141
-	       at91_rstc_base);
142
-
143
-	return NOTIFY_DONE;
144
-}
145
-
146
-static void __init at91_reset_status(struct platform_device *pdev)
105
+static void __init at91_reset_status(struct platform_device *pdev,
106
+				     void __iomem *base)
147107 {
148108 	const char *reason;
149
-	u32 reg = readl(at91_rstc_base + AT91_RSTC_SR);
109
+	u32 reg = readl(base + AT91_RSTC_SR);
150110 
151111 	switch ((reg & AT91_RSTC_RSTTYP) >> 8) {
152112 	case RESET_TYPE_GENERAL:
....@@ -164,6 +124,15 @@
164124 	case RESET_TYPE_USER:
165125 		reason = "user reset";
166126 		break;
127
+	case RESET_TYPE_CPU_FAIL:
128
+		reason = "CPU clock failure detection";
129
+		break;
130
+	case RESET_TYPE_XTAL_FAIL:
131
+		reason = "32.768 kHz crystal failure detection";
132
+		break;
133
+	case RESET_TYPE_ULP2:
134
+		reason = "ULP2 reset";
135
+		break;
167136 	default:
168137 		reason = "unknown reset";
169138 		break;
....@@ -173,41 +142,68 @@
173142 }
174143 
175144 static const struct of_device_id at91_ramc_of_match[] = {
176
-	{ .compatible = "atmel,at91sam9260-sdramc", },
177
-	{ .compatible = "atmel,at91sam9g45-ddramc", },
145
+	{
146
+		.compatible = "atmel,at91sam9260-sdramc",
147
+		.data = (void *)AT91_SDRAMC_LPR,
148
+	},
149
+	{
150
+		.compatible = "atmel,at91sam9g45-ddramc",
151
+		.data = (void *)AT91_DDRSDRC_LPR,
152
+	},
178153 	{ /* sentinel */ }
179154 };
180155 
181156 static const struct of_device_id at91_reset_of_match[] = {
182
-	{ .compatible = "atmel,at91sam9260-rstc", .data = at91sam9260_restart },
183
-	{ .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
184
-	{ .compatible = "atmel,sama5d3-rstc", .data = sama5d3_restart },
185
-	{ .compatible = "atmel,samx7-rstc", .data = samx7_restart },
157
+	{
158
+		.compatible = "atmel,at91sam9260-rstc",
159
+		.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST |
160
+				 AT91_RSTC_PROCRST),
161
+	},
162
+	{
163
+		.compatible = "atmel,at91sam9g45-rstc",
164
+		.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST |
165
+				 AT91_RSTC_PROCRST)
166
+	},
167
+	{
168
+		.compatible = "atmel,sama5d3-rstc",
169
+		.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PERRST |
170
+				 AT91_RSTC_PROCRST)
171
+	},
172
+	{
173
+		.compatible = "atmel,samx7-rstc",
174
+		.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST)
175
+	},
176
+	{
177
+		.compatible = "microchip,sam9x60-rstc",
178
+		.data = (void *)(AT91_RSTC_KEY | AT91_RSTC_PROCRST)
179
+	},
186180 	{ /* sentinel */ }
187181 };
188182 MODULE_DEVICE_TABLE(of, at91_reset_of_match);
189183 
190
-static struct notifier_block at91_restart_nb = {
191
-	.priority = 192,
192
-};
193
-
194184 static int __init at91_reset_probe(struct platform_device *pdev)
195185 {
196186 	const struct of_device_id *match;
187
+	struct at91_reset *reset;
197188 	struct device_node *np;
198189 	int ret, idx = 0;
199190 
200
-	at91_rstc_base = of_iomap(pdev->dev.of_node, 0);
201
-	if (!at91_rstc_base) {
191
+	reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
192
+	if (!reset)
193
+		return -ENOMEM;
194
+
195
+	reset->rstc_base = of_iomap(pdev->dev.of_node, 0);
196
+	if (!reset->rstc_base) {
202197 		dev_err(&pdev->dev, "Could not map reset controller address\n");
203198 		return -ENODEV;
204199 	}
205200 
206201 	if (!of_device_is_compatible(pdev->dev.of_node, "atmel,sama5d3-rstc")) {
207202 		/* we need to shutdown the ddr controller, so get ramc base */
208
-		for_each_matching_node(np, at91_ramc_of_match) {
209
-			at91_ramc_base[idx] = of_iomap(np, 0);
210
-			if (!at91_ramc_base[idx]) {
203
+		for_each_matching_node_and_match(np, at91_ramc_of_match, &match) {
204
+			reset->ramc_lpr = (u32)match->data;
205
+			reset->ramc_base[idx] = of_iomap(np, 0);
206
+			if (!reset->ramc_base[idx]) {
211207 				dev_err(&pdev->dev, "Could not map ram controller address\n");
212208 				of_node_put(np);
213209 				return -ENODEV;
....@@ -217,33 +213,46 @@
217213 	}
218214 
219215 	match = of_match_node(at91_reset_of_match, pdev->dev.of_node);
220
-	at91_restart_nb.notifier_call = match->data;
216
+	reset->nb.notifier_call = at91_reset;
217
+	reset->nb.priority = 192;
218
+	reset->args = (u32)match->data;
221219 
222
-	sclk = devm_clk_get(&pdev->dev, NULL);
223
-	if (IS_ERR(sclk))
224
-		return PTR_ERR(sclk);
220
+	reset->sclk = devm_clk_get(&pdev->dev, NULL);
221
+	if (IS_ERR(reset->sclk))
222
+		return PTR_ERR(reset->sclk);
225223 
226
-	ret = clk_prepare_enable(sclk);
224
+	ret = clk_prepare_enable(reset->sclk);
227225 	if (ret) {
228226 		dev_err(&pdev->dev, "Could not enable slow clock\n");
229227 		return ret;
230228 	}
231229 
232
-	ret = register_restart_handler(&at91_restart_nb);
230
+	platform_set_drvdata(pdev, reset);
231
+
232
+	if (of_device_is_compatible(pdev->dev.of_node, "microchip,sam9x60-rstc")) {
233
+		u32 val = readl(reset->rstc_base + AT91_RSTC_MR);
234
+
235
+		writel(AT91_RSTC_KEY | AT91_RSTC_URSTASYNC | val,
236
+		       reset->rstc_base + AT91_RSTC_MR);
237
+	}
238
+
239
+	ret = register_restart_handler(&reset->nb);
233240 	if (ret) {
234
-		clk_disable_unprepare(sclk);
241
+		clk_disable_unprepare(reset->sclk);
235242 		return ret;
236243 	}
237244 
238
-	at91_reset_status(pdev);
245
+	at91_reset_status(pdev, reset->rstc_base);
239246 
240247 	return 0;
241248 }
242249 
243250 static int __exit at91_reset_remove(struct platform_device *pdev)
244251 {
245
-	unregister_restart_handler(&at91_restart_nb);
246
-	clk_disable_unprepare(sclk);
252
+	struct at91_reset *reset = platform_get_drvdata(pdev);
253
+
254
+	unregister_restart_handler(&reset->nb);
255
+	clk_disable_unprepare(reset->sclk);
247256 
248257 	return 0;
249258 }