forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/platform/x86/intel_scu_ipc.c
....@@ -1,13 +1,9 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
2
- * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
3
+ * Driver for the Intel SCU IPC mechanism
34  *
45  * (C) Copyright 2008-2010,2015 Intel Corporation
56  * Author: Sreedhara DS (sreedhara.ds@intel.com)
6
- *
7
- * This program is free software; you can redistribute it and/or
8
- * modify it under the terms of the GNU General Public License
9
- * as published by the Free Software Foundation; version 2
10
- * of the License.
117  *
128  * SCU running in ARC processor communicates with other entity running in IA
139  * core through IPC mechanism which in turn messaging between IA core ad SCU.
....@@ -16,23 +12,20 @@
1612  * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
1713  * along with other APIs.
1814  */
15
+
1916 #include <linux/delay.h>
17
+#include <linux/device.h>
2018 #include <linux/errno.h>
2119 #include <linux/init.h>
22
-#include <linux/device.h>
23
-#include <linux/pm.h>
24
-#include <linux/pci.h>
2520 #include <linux/interrupt.h>
26
-#include <linux/sfi.h>
27
-#include <asm/intel-mid.h>
21
+#include <linux/io.h>
22
+#include <linux/module.h>
23
+#include <linux/slab.h>
24
+
2825 #include <asm/intel_scu_ipc.h>
2926 
3027 /* IPC defines the following message types */
31
-#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
32
-#define IPCMSG_BATTERY        0xEF /* Coulomb Counter Accumulator */
33
-#define IPCMSG_FW_UPDATE      0xFE /* Firmware update */
34
-#define IPCMSG_PCNTRL         0xFF /* Power controller unit read/write */
35
-#define IPCMSG_FW_REVISION    0xF4 /* Get firmware revision */
28
+#define IPCMSG_PCNTRL         0xff /* Power controller unit read/write */
3629 
3730 /* Command id associated with message IPCMSG_PCNTRL */
3831 #define IPC_CMD_PCNTRL_W      0 /* Register write */
....@@ -60,57 +53,133 @@
6053 #define IPC_RWBUF_SIZE    20		/* IPC Read buffer Size */
6154 #define IPC_IOC	          0x100		/* IPC command register IOC bit */
6255 
63
-#define PCI_DEVICE_ID_LINCROFT		0x082a
64
-#define PCI_DEVICE_ID_PENWELL		0x080e
65
-#define PCI_DEVICE_ID_CLOVERVIEW	0x08ea
66
-#define PCI_DEVICE_ID_TANGIER		0x11a0
67
-
68
-/* intel scu ipc driver data */
69
-struct intel_scu_ipc_pdata_t {
70
-	u32 i2c_base;
71
-	u32 i2c_len;
72
-};
73
-
74
-static const struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata = {
75
-	.i2c_base = 0xff12b000,
76
-	.i2c_len = 0x10,
77
-};
78
-
79
-/* Penwell and Cloverview */
80
-static const struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata = {
81
-	.i2c_base = 0xff12b000,
82
-	.i2c_len = 0x10,
83
-};
84
-
85
-static const struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {
86
-	.i2c_base  = 0xff00d000,
87
-	.i2c_len = 0x10,
88
-};
89
-
9056 struct intel_scu_ipc_dev {
91
-	struct device *dev;
57
+	struct device dev;
58
+	struct resource mem;
59
+	struct module *owner;
60
+	int irq;
9261 	void __iomem *ipc_base;
93
-	void __iomem *i2c_base;
9462 	struct completion cmd_complete;
95
-	u8 irq_mode;
9663 };
97
-
98
-static struct intel_scu_ipc_dev  ipcdev; /* Only one for now */
9964 
10065 #define IPC_STATUS		0x04
10166 #define IPC_STATUS_IRQ		BIT(2)
67
+#define IPC_STATUS_ERR		BIT(1)
68
+#define IPC_STATUS_BUSY		BIT(0)
10269 
10370 /*
104
- * IPC Read Buffer (Read Only):
105
- * 16 byte buffer for receiving data from SCU, if IPC command
106
- * processing results in response data
71
+ * IPC Write/Read Buffers:
72
+ * 16 byte buffer for sending and receiving data to and from SCU.
10773  */
74
+#define IPC_WRITE_BUFFER	0x80
10875 #define IPC_READ_BUFFER		0x90
10976 
110
-#define IPC_I2C_CNTRL_ADDR	0
111
-#define I2C_DATA_ADDR		0x04
77
+/* Timeout in jiffies */
78
+#define IPC_TIMEOUT		(3 * HZ)
11279 
80
+static struct intel_scu_ipc_dev *ipcdev; /* Only one for now */
11381 static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
82
+
83
+static struct class intel_scu_ipc_class = {
84
+	.name = "intel_scu_ipc",
85
+	.owner = THIS_MODULE,
86
+};
87
+
88
+/**
89
+ * intel_scu_ipc_dev_get() - Get SCU IPC instance
90
+ *
91
+ * The recommended new API takes SCU IPC instance as parameter and this
92
+ * function can be called by driver to get the instance. This also makes
93
+ * sure the driver providing the IPC functionality cannot be unloaded
94
+ * while the caller has the instance.
95
+ *
96
+ * Call intel_scu_ipc_dev_put() to release the instance.
97
+ *
98
+ * Returns %NULL if SCU IPC is not currently available.
99
+ */
100
+struct intel_scu_ipc_dev *intel_scu_ipc_dev_get(void)
101
+{
102
+	struct intel_scu_ipc_dev *scu = NULL;
103
+
104
+	mutex_lock(&ipclock);
105
+	if (ipcdev) {
106
+		get_device(&ipcdev->dev);
107
+		/*
108
+		 * Prevent the IPC provider from being unloaded while it
109
+		 * is being used.
110
+		 */
111
+		if (!try_module_get(ipcdev->owner))
112
+			put_device(&ipcdev->dev);
113
+		else
114
+			scu = ipcdev;
115
+	}
116
+
117
+	mutex_unlock(&ipclock);
118
+	return scu;
119
+}
120
+EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_get);
121
+
122
+/**
123
+ * intel_scu_ipc_dev_put() - Put SCU IPC instance
124
+ * @scu: SCU IPC instance
125
+ *
126
+ * This function releases the SCU IPC instance retrieved from
127
+ * intel_scu_ipc_dev_get() and allows the driver providing IPC to be
128
+ * unloaded.
129
+ */
130
+void intel_scu_ipc_dev_put(struct intel_scu_ipc_dev *scu)
131
+{
132
+	if (scu) {
133
+		module_put(scu->owner);
134
+		put_device(&scu->dev);
135
+	}
136
+}
137
+EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_put);
138
+
139
+struct intel_scu_ipc_devres {
140
+	struct intel_scu_ipc_dev *scu;
141
+};
142
+
143
+static void devm_intel_scu_ipc_dev_release(struct device *dev, void *res)
144
+{
145
+	struct intel_scu_ipc_devres *dr = res;
146
+	struct intel_scu_ipc_dev *scu = dr->scu;
147
+
148
+	intel_scu_ipc_dev_put(scu);
149
+}
150
+
151
+/**
152
+ * devm_intel_scu_ipc_dev_get() - Allocate managed SCU IPC device
153
+ * @dev: Device requesting the SCU IPC device
154
+ *
155
+ * The recommended new API takes SCU IPC instance as parameter and this
156
+ * function can be called by driver to get the instance. This also makes
157
+ * sure the driver providing the IPC functionality cannot be unloaded
158
+ * while the caller has the instance.
159
+ *
160
+ * Returns %NULL if SCU IPC is not currently available.
161
+ */
162
+struct intel_scu_ipc_dev *devm_intel_scu_ipc_dev_get(struct device *dev)
163
+{
164
+	struct intel_scu_ipc_devres *dr;
165
+	struct intel_scu_ipc_dev *scu;
166
+
167
+	dr = devres_alloc(devm_intel_scu_ipc_dev_release, sizeof(*dr), GFP_KERNEL);
168
+	if (!dr)
169
+		return NULL;
170
+
171
+	scu = intel_scu_ipc_dev_get();
172
+	if (!scu) {
173
+		devres_free(dr);
174
+		return NULL;
175
+	}
176
+
177
+	dr->scu = scu;
178
+	devres_add(dev, dr);
179
+
180
+	return scu;
181
+}
182
+EXPORT_SYMBOL_GPL(devm_intel_scu_ipc_dev_get);
114183 
115184 /*
116185  * Send ipc command
....@@ -133,7 +202,7 @@
133202  */
134203 static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
135204 {
136
-	writel(data, scu->ipc_base + 0x80 + offset);
205
+	writel(data, scu->ipc_base + IPC_WRITE_BUFFER + offset);
137206 }
138207 
139208 /*
....@@ -145,7 +214,7 @@
145214  */
146215 static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
147216 {
148
-	return __raw_readl(scu->ipc_base + 0x04);
217
+	return __raw_readl(scu->ipc_base + IPC_STATUS);
149218 }
150219 
151220 /* Read ipc byte data */
....@@ -163,24 +232,19 @@
163232 /* Wait till scu status is busy */
164233 static inline int busy_loop(struct intel_scu_ipc_dev *scu)
165234 {
166
-	u32 status = ipc_read_status(scu);
167
-	u32 loop_count = 100000;
235
+	unsigned long end = jiffies + IPC_TIMEOUT;
168236 
169
-	/* break if scu doesn't reset busy bit after huge retry */
170
-	while ((status & BIT(0)) && --loop_count) {
171
-		udelay(1); /* scu processing time is in few u secods */
237
+	do {
238
+		u32 status;
239
+
172240 		status = ipc_read_status(scu);
173
-	}
241
+		if (!(status & IPC_STATUS_BUSY))
242
+			return (status & IPC_STATUS_ERR) ? -EIO : 0;
174243 
175
-	if (status & BIT(0)) {
176
-		dev_err(scu->dev, "IPC timed out");
177
-		return -ETIMEDOUT;
178
-	}
244
+		usleep_range(50, 100);
245
+	} while (time_before(jiffies, end));
179246 
180
-	if (status & BIT(1))
181
-		return -EIO;
182
-
183
-	return 0;
247
+	return -ETIMEDOUT;
184248 }
185249 
186250 /* Wait till ipc ioc interrupt is received or timeout in 10 HZ */
....@@ -188,13 +252,11 @@
188252 {
189253 	int status;
190254 
191
-	if (!wait_for_completion_timeout(&scu->cmd_complete, 3 * HZ)) {
192
-		dev_err(scu->dev, "IPC timed out\n");
255
+	if (!wait_for_completion_timeout(&scu->cmd_complete, IPC_TIMEOUT))
193256 		return -ETIMEDOUT;
194
-	}
195257 
196258 	status = ipc_read_status(scu);
197
-	if (status & BIT(1))
259
+	if (status & IPC_STATUS_ERR)
198260 		return -EIO;
199261 
200262 	return 0;
....@@ -202,13 +264,13 @@
202264 
203265 static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
204266 {
205
-	return scu->irq_mode ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
267
+	return scu->irq > 0 ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
206268 }
207269 
208270 /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
209
-static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
271
+static int pwr_reg_rdwr(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
272
+			u32 count, u32 op, u32 id)
210273 {
211
-	struct intel_scu_ipc_dev *scu = &ipcdev;
212274 	int nc;
213275 	u32 offset = 0;
214276 	int err;
....@@ -218,8 +280,9 @@
218280 	memset(cbuf, 0, sizeof(cbuf));
219281 
220282 	mutex_lock(&ipclock);
221
-
222
-	if (scu->dev == NULL) {
283
+	if (!scu)
284
+		scu = ipcdev;
285
+	if (!scu) {
223286 		mutex_unlock(&ipclock);
224287 		return -ENODEV;
225288 	}
....@@ -258,345 +321,200 @@
258321 }
259322 
260323 /**
261
- *	intel_scu_ipc_ioread8		-	read a word via the SCU
262
- *	@addr: register on SCU
263
- *	@data: return pointer for read byte
324
+ * intel_scu_ipc_dev_ioread8() - Read a byte via the SCU
325
+ * @scu: Optional SCU IPC instance
326
+ * @addr: Register on SCU
327
+ * @data: Return pointer for read byte
264328  *
265
- *	Read a single register. Returns 0 on success or an error code. All
266
- *	locking between SCU accesses is handled for the caller.
329
+ * Read a single register. Returns %0 on success or an error code. All
330
+ * locking between SCU accesses is handled for the caller.
267331  *
268
- *	This function may sleep.
332
+ * This function may sleep.
269333  */
270
-int intel_scu_ipc_ioread8(u16 addr, u8 *data)
334
+int intel_scu_ipc_dev_ioread8(struct intel_scu_ipc_dev *scu, u16 addr, u8 *data)
271335 {
272
-	return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
336
+	return pwr_reg_rdwr(scu, &addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
273337 }
274
-EXPORT_SYMBOL(intel_scu_ipc_ioread8);
338
+EXPORT_SYMBOL(intel_scu_ipc_dev_ioread8);
275339 
276340 /**
277
- *	intel_scu_ipc_ioread16		-	read a word via the SCU
278
- *	@addr: register on SCU
279
- *	@data: return pointer for read word
341
+ * intel_scu_ipc_dev_iowrite8() - Write a byte via the SCU
342
+ * @scu: Optional SCU IPC instance
343
+ * @addr: Register on SCU
344
+ * @data: Byte to write
280345  *
281
- *	Read a register pair. Returns 0 on success or an error code. All
282
- *	locking between SCU accesses is handled for the caller.
346
+ * Write a single register. Returns %0 on success or an error code. All
347
+ * locking between SCU accesses is handled for the caller.
283348  *
284
- *	This function may sleep.
349
+ * This function may sleep.
285350  */
286
-int intel_scu_ipc_ioread16(u16 addr, u16 *data)
351
+int intel_scu_ipc_dev_iowrite8(struct intel_scu_ipc_dev *scu, u16 addr, u8 data)
287352 {
288
-	u16 x[2] = {addr, addr + 1};
289
-	return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
353
+	return pwr_reg_rdwr(scu, &addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
290354 }
291
-EXPORT_SYMBOL(intel_scu_ipc_ioread16);
355
+EXPORT_SYMBOL(intel_scu_ipc_dev_iowrite8);
292356 
293357 /**
294
- *	intel_scu_ipc_ioread32		-	read a dword via the SCU
295
- *	@addr: register on SCU
296
- *	@data: return pointer for read dword
358
+ * intel_scu_ipc_dev_readv() - Read a set of registers
359
+ * @scu: Optional SCU IPC instance
360
+ * @addr: Register list
361
+ * @data: Bytes to return
362
+ * @len: Length of array
297363  *
298
- *	Read four registers. Returns 0 on success or an error code. All
299
- *	locking between SCU accesses is handled for the caller.
364
+ * Read registers. Returns %0 on success or an error code. All locking
365
+ * between SCU accesses is handled for the caller.
300366  *
301
- *	This function may sleep.
367
+ * The largest array length permitted by the hardware is 5 items.
368
+ *
369
+ * This function may sleep.
302370  */
303
-int intel_scu_ipc_ioread32(u16 addr, u32 *data)
371
+int intel_scu_ipc_dev_readv(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
372
+			    size_t len)
304373 {
305
-	u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
306
-	return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
374
+	return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
307375 }
308
-EXPORT_SYMBOL(intel_scu_ipc_ioread32);
376
+EXPORT_SYMBOL(intel_scu_ipc_dev_readv);
309377 
310378 /**
311
- *	intel_scu_ipc_iowrite8		-	write a byte via the SCU
312
- *	@addr: register on SCU
313
- *	@data: byte to write
379
+ * intel_scu_ipc_dev_writev() - Write a set of registers
380
+ * @scu: Optional SCU IPC instance
381
+ * @addr: Register list
382
+ * @data: Bytes to write
383
+ * @len: Length of array
314384  *
315
- *	Write a single register. Returns 0 on success or an error code. All
316
- *	locking between SCU accesses is handled for the caller.
385
+ * Write registers. Returns %0 on success or an error code. All locking
386
+ * between SCU accesses is handled for the caller.
317387  *
318
- *	This function may sleep.
388
+ * The largest array length permitted by the hardware is 5 items.
389
+ *
390
+ * This function may sleep.
319391  */
320
-int intel_scu_ipc_iowrite8(u16 addr, u8 data)
392
+int intel_scu_ipc_dev_writev(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
393
+			     size_t len)
321394 {
322
-	return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
395
+	return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
323396 }
324
-EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
397
+EXPORT_SYMBOL(intel_scu_ipc_dev_writev);
325398 
326399 /**
327
- *	intel_scu_ipc_iowrite16		-	write a word via the SCU
328
- *	@addr: register on SCU
329
- *	@data: word to write
400
+ * intel_scu_ipc_dev_update() - Update a register
401
+ * @scu: Optional SCU IPC instance
402
+ * @addr: Register address
403
+ * @data: Bits to update
404
+ * @mask: Mask of bits to update
330405  *
331
- *	Write two registers. Returns 0 on success or an error code. All
332
- *	locking between SCU accesses is handled for the caller.
406
+ * Read-modify-write power control unit register. The first data argument
407
+ * must be register value and second is mask value mask is a bitmap that
408
+ * indicates which bits to update. %0 = masked. Don't modify this bit, %1 =
409
+ * modify this bit. returns %0 on success or an error code.
333410  *
334
- *	This function may sleep.
411
+ * This function may sleep. Locking between SCU accesses is handled
412
+ * for the caller.
335413  */
336
-int intel_scu_ipc_iowrite16(u16 addr, u16 data)
414
+int intel_scu_ipc_dev_update(struct intel_scu_ipc_dev *scu, u16 addr, u8 data,
415
+			     u8 mask)
337416 {
338
-	u16 x[2] = {addr, addr + 1};
339
-	return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
417
+	u8 tmp[2] = { data, mask };
418
+	return pwr_reg_rdwr(scu, &addr, tmp, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
340419 }
341
-EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
420
+EXPORT_SYMBOL(intel_scu_ipc_dev_update);
342421 
343422 /**
344
- *	intel_scu_ipc_iowrite32		-	write a dword via the SCU
345
- *	@addr: register on SCU
346
- *	@data: dword to write
423
+ * intel_scu_ipc_dev_simple_command() - Send a simple command
424
+ * @scu: Optional SCU IPC instance
425
+ * @cmd: Command
426
+ * @sub: Sub type
347427  *
348
- *	Write four registers. Returns 0 on success or an error code. All
349
- *	locking between SCU accesses is handled for the caller.
428
+ * Issue a simple command to the SCU. Do not use this interface if you must
429
+ * then access data as any data values may be overwritten by another SCU
430
+ * access by the time this function returns.
350431  *
351
- *	This function may sleep.
432
+ * This function may sleep. Locking for SCU accesses is handled for the
433
+ * caller.
352434  */
353
-int intel_scu_ipc_iowrite32(u16 addr, u32 data)
435
+int intel_scu_ipc_dev_simple_command(struct intel_scu_ipc_dev *scu, int cmd,
436
+				     int sub)
354437 {
355
-	u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
356
-	return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
357
-}
358
-EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
359
-
360
-/**
361
- *	intel_scu_ipc_readvv		-	read a set of registers
362
- *	@addr: register list
363
- *	@data: bytes to return
364
- *	@len: length of array
365
- *
366
- *	Read registers. Returns 0 on success or an error code. All
367
- *	locking between SCU accesses is handled for the caller.
368
- *
369
- *	The largest array length permitted by the hardware is 5 items.
370
- *
371
- *	This function may sleep.
372
- */
373
-int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
374
-{
375
-	return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
376
-}
377
-EXPORT_SYMBOL(intel_scu_ipc_readv);
378
-
379
-/**
380
- *	intel_scu_ipc_writev		-	write a set of registers
381
- *	@addr: register list
382
- *	@data: bytes to write
383
- *	@len: length of array
384
- *
385
- *	Write registers. Returns 0 on success or an error code. All
386
- *	locking between SCU accesses is handled for the caller.
387
- *
388
- *	The largest array length permitted by the hardware is 5 items.
389
- *
390
- *	This function may sleep.
391
- *
392
- */
393
-int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
394
-{
395
-	return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
396
-}
397
-EXPORT_SYMBOL(intel_scu_ipc_writev);
398
-
399
-/**
400
- *	intel_scu_ipc_update_register	-	r/m/w a register
401
- *	@addr: register address
402
- *	@bits: bits to update
403
- *	@mask: mask of bits to update
404
- *
405
- *	Read-modify-write power control unit register. The first data argument
406
- *	must be register value and second is mask value
407
- *	mask is a bitmap that indicates which bits to update.
408
- *	0 = masked. Don't modify this bit, 1 = modify this bit.
409
- *	returns 0 on success or an error code.
410
- *
411
- *	This function may sleep. Locking between SCU accesses is handled
412
- *	for the caller.
413
- */
414
-int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
415
-{
416
-	u8 data[2] = { bits, mask };
417
-	return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
418
-}
419
-EXPORT_SYMBOL(intel_scu_ipc_update_register);
420
-
421
-/**
422
- *	intel_scu_ipc_simple_command	-	send a simple command
423
- *	@cmd: command
424
- *	@sub: sub type
425
- *
426
- *	Issue a simple command to the SCU. Do not use this interface if
427
- *	you must then access data as any data values may be overwritten
428
- *	by another SCU access by the time this function returns.
429
- *
430
- *	This function may sleep. Locking for SCU accesses is handled for
431
- *	the caller.
432
- */
433
-int intel_scu_ipc_simple_command(int cmd, int sub)
434
-{
435
-	struct intel_scu_ipc_dev *scu = &ipcdev;
438
+	u32 cmdval;
436439 	int err;
437440 
438441 	mutex_lock(&ipclock);
439
-	if (scu->dev == NULL) {
442
+	if (!scu)
443
+		scu = ipcdev;
444
+	if (!scu) {
440445 		mutex_unlock(&ipclock);
441446 		return -ENODEV;
442447 	}
443
-	ipc_command(scu, sub << 12 | cmd);
448
+	scu = ipcdev;
449
+	cmdval = sub << 12 | cmd;
450
+	ipc_command(scu, cmdval);
444451 	err = intel_scu_ipc_check_status(scu);
445452 	mutex_unlock(&ipclock);
453
+	if (err)
454
+		dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
446455 	return err;
447456 }
448
-EXPORT_SYMBOL(intel_scu_ipc_simple_command);
457
+EXPORT_SYMBOL(intel_scu_ipc_dev_simple_command);
449458 
450459 /**
451
- *	intel_scu_ipc_command	-	command with data
452
- *	@cmd: command
453
- *	@sub: sub type
454
- *	@in: input data
455
- *	@inlen: input length in dwords
456
- *	@out: output data
457
- *	@outlein: output length in dwords
460
+ * intel_scu_ipc_command_with_size() - Command with data
461
+ * @scu: Optional SCU IPC instance
462
+ * @cmd: Command
463
+ * @sub: Sub type
464
+ * @in: Input data
465
+ * @inlen: Input length in bytes
466
+ * @size: Input size written to the IPC command register in whatever
467
+ *	  units (dword, byte) the particular firmware requires. Normally
468
+ *	  should be the same as @inlen.
469
+ * @out: Output data
470
+ * @outlen: Output length in bytes
458471  *
459
- *	Issue a command to the SCU which involves data transfers. Do the
460
- *	data copies under the lock but leave it for the caller to interpret
472
+ * Issue a command to the SCU which involves data transfers. Do the
473
+ * data copies under the lock but leave it for the caller to interpret.
461474  */
462
-int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
463
-			  u32 *out, int outlen)
475
+int intel_scu_ipc_dev_command_with_size(struct intel_scu_ipc_dev *scu, int cmd,
476
+					int sub, const void *in, size_t inlen,
477
+					size_t size, void *out, size_t outlen)
464478 {
465
-	struct intel_scu_ipc_dev *scu = &ipcdev;
479
+	size_t outbuflen = DIV_ROUND_UP(outlen, sizeof(u32));
480
+	size_t inbuflen = DIV_ROUND_UP(inlen, sizeof(u32));
481
+	u32 cmdval, inbuf[4] = {};
466482 	int i, err;
467483 
468
-	mutex_lock(&ipclock);
469
-	if (scu->dev == NULL) {
470
-		mutex_unlock(&ipclock);
471
-		return -ENODEV;
472
-	}
473
-
474
-	for (i = 0; i < inlen; i++)
475
-		ipc_data_writel(scu, *in++, 4 * i);
476
-
477
-	ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
478
-	err = intel_scu_ipc_check_status(scu);
479
-
480
-	if (!err) {
481
-		for (i = 0; i < outlen; i++)
482
-			*out++ = ipc_data_readl(scu, 4 * i);
483
-	}
484
-
485
-	mutex_unlock(&ipclock);
486
-	return err;
487
-}
488
-EXPORT_SYMBOL(intel_scu_ipc_command);
489
-
490
-#define IPC_SPTR		0x08
491
-#define IPC_DPTR		0x0C
492
-
493
-/**
494
- * intel_scu_ipc_raw_command() - IPC command with data and pointers
495
- * @cmd:	IPC command code.
496
- * @sub:	IPC command sub type.
497
- * @in:		input data of this IPC command.
498
- * @inlen:	input data length in dwords.
499
- * @out:	output data of this IPC command.
500
- * @outlen:	output data length in dwords.
501
- * @sptr:	data writing to SPTR register.
502
- * @dptr:	data writing to DPTR register.
503
- *
504
- * Send an IPC command to SCU with input/output data and source/dest pointers.
505
- *
506
- * Return:	an IPC error code or 0 on success.
507
- */
508
-int intel_scu_ipc_raw_command(int cmd, int sub, u8 *in, int inlen,
509
-			      u32 *out, int outlen, u32 dptr, u32 sptr)
510
-{
511
-	struct intel_scu_ipc_dev *scu = &ipcdev;
512
-	int inbuflen = DIV_ROUND_UP(inlen, 4);
513
-	u32 inbuf[4];
514
-	int i, err;
515
-
516
-	/* Up to 16 bytes */
517
-	if (inbuflen > 4)
484
+	if (inbuflen > 4 || outbuflen > 4)
518485 		return -EINVAL;
519486 
520487 	mutex_lock(&ipclock);
521
-	if (scu->dev == NULL) {
488
+	if (!scu)
489
+		scu = ipcdev;
490
+	if (!scu) {
522491 		mutex_unlock(&ipclock);
523492 		return -ENODEV;
524493 	}
525494 
526
-	writel(dptr, scu->ipc_base + IPC_DPTR);
527
-	writel(sptr, scu->ipc_base + IPC_SPTR);
528
-
529
-	/*
530
-	 * SRAM controller doesn't support 8-bit writes, it only
531
-	 * supports 32-bit writes, so we have to copy input data into
532
-	 * the temporary buffer, and SCU FW will use the inlen to
533
-	 * determine the actual input data length in the temporary
534
-	 * buffer.
535
-	 */
536495 	memcpy(inbuf, in, inlen);
537
-
538496 	for (i = 0; i < inbuflen; i++)
539497 		ipc_data_writel(scu, inbuf[i], 4 * i);
540498 
541
-	ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
499
+	cmdval = (size << 16) | (sub << 12) | cmd;
500
+	ipc_command(scu, cmdval);
542501 	err = intel_scu_ipc_check_status(scu);
502
+
543503 	if (!err) {
544
-		for (i = 0; i < outlen; i++)
545
-			*out++ = ipc_data_readl(scu, 4 * i);
504
+		u32 outbuf[4] = {};
505
+
506
+		for (i = 0; i < outbuflen; i++)
507
+			outbuf[i] = ipc_data_readl(scu, 4 * i);
508
+
509
+		memcpy(out, outbuf, outlen);
546510 	}
547511 
548512 	mutex_unlock(&ipclock);
513
+	if (err)
514
+		dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
549515 	return err;
550516 }
551
-EXPORT_SYMBOL_GPL(intel_scu_ipc_raw_command);
552
-
553
-/* I2C commands */
554
-#define IPC_I2C_WRITE 1 /* I2C Write command */
555
-#define IPC_I2C_READ  2 /* I2C Read command */
556
-
557
-/**
558
- *	intel_scu_ipc_i2c_cntrl		-	I2C read/write operations
559
- *	@addr: I2C address + command bits
560
- *	@data: data to read/write
561
- *
562
- *	Perform an an I2C read/write operation via the SCU. All locking is
563
- *	handled for the caller. This function may sleep.
564
- *
565
- *	Returns an error code or 0 on success.
566
- *
567
- *	This has to be in the IPC driver for the locking.
568
- */
569
-int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
570
-{
571
-	struct intel_scu_ipc_dev *scu = &ipcdev;
572
-	u32 cmd = 0;
573
-
574
-	mutex_lock(&ipclock);
575
-	if (scu->dev == NULL) {
576
-		mutex_unlock(&ipclock);
577
-		return -ENODEV;
578
-	}
579
-	cmd = (addr >> 24) & 0xFF;
580
-	if (cmd == IPC_I2C_READ) {
581
-		writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
582
-		/* Write not getting updated without delay */
583
-		usleep_range(1000, 2000);
584
-		*data = readl(scu->i2c_base + I2C_DATA_ADDR);
585
-	} else if (cmd == IPC_I2C_WRITE) {
586
-		writel(*data, scu->i2c_base + I2C_DATA_ADDR);
587
-		usleep_range(1000, 2000);
588
-		writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
589
-	} else {
590
-		dev_err(scu->dev,
591
-			"intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
592
-
593
-		mutex_unlock(&ipclock);
594
-		return -EIO;
595
-	}
596
-	mutex_unlock(&ipclock);
597
-	return 0;
598
-}
599
-EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
517
+EXPORT_SYMBOL(intel_scu_ipc_dev_command_with_size);
600518 
601519 /*
602520  * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
....@@ -616,73 +534,179 @@
616534 	return IRQ_HANDLED;
617535 }
618536 
619
-/**
620
- *	ipc_probe	-	probe an Intel SCU IPC
621
- *	@pdev: the PCI device matching
622
- *	@id: entry in the match table
623
- *
624
- *	Enable and install an intel SCU IPC. This appears in the PCI space
625
- *	but uses some hard coded addresses as well.
626
- */
627
-static int ipc_probe(struct pci_dev *pdev, const struct pci_device_id *id)
537
+static void intel_scu_ipc_release(struct device *dev)
628538 {
629
-	int err;
630
-	struct intel_scu_ipc_dev *scu = &ipcdev;
631
-	struct intel_scu_ipc_pdata_t *pdata;
539
+	struct intel_scu_ipc_dev *scu;
632540 
633
-	if (scu->dev)		/* We support only one SCU */
634
-		return -EBUSY;
635
-
636
-	pdata = (struct intel_scu_ipc_pdata_t *)id->driver_data;
637
-	if (!pdata)
638
-		return -ENODEV;
639
-
640
-	err = pcim_enable_device(pdev);
641
-	if (err)
642
-		return err;
643
-
644
-	err = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
645
-	if (err)
646
-		return err;
647
-
648
-	init_completion(&scu->cmd_complete);
649
-
650
-	scu->ipc_base = pcim_iomap_table(pdev)[0];
651
-
652
-	scu->i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);
653
-	if (!scu->i2c_base)
654
-		return -ENOMEM;
655
-
656
-	err = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_scu_ipc",
657
-			       scu);
658
-	if (err)
659
-		return err;
660
-
661
-	/* Assign device at last */
662
-	scu->dev = &pdev->dev;
663
-
664
-	intel_scu_devices_create();
665
-
666
-	pci_set_drvdata(pdev, scu);
667
-	return 0;
541
+	scu = container_of(dev, struct intel_scu_ipc_dev, dev);
542
+	if (scu->irq > 0)
543
+		free_irq(scu->irq, scu);
544
+	iounmap(scu->ipc_base);
545
+	release_mem_region(scu->mem.start, resource_size(&scu->mem));
546
+	kfree(scu);
668547 }
669548 
670
-#define SCU_DEVICE(id, pdata)	{PCI_VDEVICE(INTEL, id), (kernel_ulong_t)&pdata}
549
+/**
550
+ * __intel_scu_ipc_register() - Register SCU IPC device
551
+ * @parent: Parent device
552
+ * @scu_data: Data used to configure SCU IPC
553
+ * @owner: Module registering the SCU IPC device
554
+ *
555
+ * Call this function to register SCU IPC mechanism under @parent.
556
+ * Returns pointer to the new SCU IPC device or ERR_PTR() in case of
557
+ * failure. The caller may use the returned instance if it needs to do
558
+ * SCU IPC calls itself.
559
+ */
560
+struct intel_scu_ipc_dev *
561
+__intel_scu_ipc_register(struct device *parent,
562
+			 const struct intel_scu_ipc_data *scu_data,
563
+			 struct module *owner)
564
+{
565
+	int err;
566
+	struct intel_scu_ipc_dev *scu;
567
+	void __iomem *ipc_base;
671568 
672
-static const struct pci_device_id pci_ids[] = {
673
-	SCU_DEVICE(PCI_DEVICE_ID_LINCROFT,	intel_scu_ipc_lincroft_pdata),
674
-	SCU_DEVICE(PCI_DEVICE_ID_PENWELL,	intel_scu_ipc_penwell_pdata),
675
-	SCU_DEVICE(PCI_DEVICE_ID_CLOVERVIEW,	intel_scu_ipc_penwell_pdata),
676
-	SCU_DEVICE(PCI_DEVICE_ID_TANGIER,	intel_scu_ipc_tangier_pdata),
677
-	{}
678
-};
569
+	mutex_lock(&ipclock);
570
+	/* We support only one IPC */
571
+	if (ipcdev) {
572
+		err = -EBUSY;
573
+		goto err_unlock;
574
+	}
679575 
680
-static struct pci_driver ipc_driver = {
681
-	.driver = {
682
-		.suppress_bind_attrs = true,
683
-	},
684
-	.name = "intel_scu_ipc",
685
-	.id_table = pci_ids,
686
-	.probe = ipc_probe,
687
-};
688
-builtin_pci_driver(ipc_driver);
576
+	scu = kzalloc(sizeof(*scu), GFP_KERNEL);
577
+	if (!scu) {
578
+		err = -ENOMEM;
579
+		goto err_unlock;
580
+	}
581
+
582
+	scu->owner = owner;
583
+	scu->dev.parent = parent;
584
+	scu->dev.class = &intel_scu_ipc_class;
585
+	scu->dev.release = intel_scu_ipc_release;
586
+	dev_set_name(&scu->dev, "intel_scu_ipc");
587
+
588
+	if (!request_mem_region(scu_data->mem.start, resource_size(&scu_data->mem),
589
+				"intel_scu_ipc")) {
590
+		err = -EBUSY;
591
+		goto err_free;
592
+	}
593
+
594
+	ipc_base = ioremap(scu_data->mem.start, resource_size(&scu_data->mem));
595
+	if (!ipc_base) {
596
+		err = -ENOMEM;
597
+		goto err_release;
598
+	}
599
+
600
+	scu->ipc_base = ipc_base;
601
+	scu->mem = scu_data->mem;
602
+	scu->irq = scu_data->irq;
603
+	init_completion(&scu->cmd_complete);
604
+
605
+	if (scu->irq > 0) {
606
+		err = request_irq(scu->irq, ioc, 0, "intel_scu_ipc", scu);
607
+		if (err)
608
+			goto err_unmap;
609
+	}
610
+
611
+	/*
612
+	 * After this point intel_scu_ipc_release() takes care of
613
+	 * releasing the SCU IPC resources once refcount drops to zero.
614
+	 */
615
+	err = device_register(&scu->dev);
616
+	if (err) {
617
+		put_device(&scu->dev);
618
+		goto err_unlock;
619
+	}
620
+
621
+	/* Assign device at last */
622
+	ipcdev = scu;
623
+	mutex_unlock(&ipclock);
624
+
625
+	return scu;
626
+
627
+err_unmap:
628
+	iounmap(ipc_base);
629
+err_release:
630
+	release_mem_region(scu_data->mem.start, resource_size(&scu_data->mem));
631
+err_free:
632
+	kfree(scu);
633
+err_unlock:
634
+	mutex_unlock(&ipclock);
635
+
636
+	return ERR_PTR(err);
637
+}
638
+EXPORT_SYMBOL_GPL(__intel_scu_ipc_register);
639
+
640
+/**
641
+ * intel_scu_ipc_unregister() - Unregister SCU IPC
642
+ * @scu: SCU IPC handle
643
+ *
644
+ * This unregisters the SCU IPC device and releases the acquired
645
+ * resources once the refcount goes to zero.
646
+ */
647
+void intel_scu_ipc_unregister(struct intel_scu_ipc_dev *scu)
648
+{
649
+	mutex_lock(&ipclock);
650
+	if (!WARN_ON(!ipcdev)) {
651
+		ipcdev = NULL;
652
+		device_unregister(&scu->dev);
653
+	}
654
+	mutex_unlock(&ipclock);
655
+}
656
+EXPORT_SYMBOL_GPL(intel_scu_ipc_unregister);
657
+
658
+static void devm_intel_scu_ipc_unregister(struct device *dev, void *res)
659
+{
660
+	struct intel_scu_ipc_devres *dr = res;
661
+	struct intel_scu_ipc_dev *scu = dr->scu;
662
+
663
+	intel_scu_ipc_unregister(scu);
664
+}
665
+
666
+/**
667
+ * __devm_intel_scu_ipc_register() - Register managed SCU IPC device
668
+ * @parent: Parent device
669
+ * @scu_data: Data used to configure SCU IPC
670
+ * @owner: Module registering the SCU IPC device
671
+ *
672
+ * Call this function to register managed SCU IPC mechanism under
673
+ * @parent. Returns pointer to the new SCU IPC device or ERR_PTR() in
674
+ * case of failure. The caller may use the returned instance if it needs
675
+ * to do SCU IPC calls itself.
676
+ */
677
+struct intel_scu_ipc_dev *
678
+__devm_intel_scu_ipc_register(struct device *parent,
679
+			      const struct intel_scu_ipc_data *scu_data,
680
+			      struct module *owner)
681
+{
682
+	struct intel_scu_ipc_devres *dr;
683
+	struct intel_scu_ipc_dev *scu;
684
+
685
+	dr = devres_alloc(devm_intel_scu_ipc_unregister, sizeof(*dr), GFP_KERNEL);
686
+	if (!dr)
687
+		return NULL;
688
+
689
+	scu = __intel_scu_ipc_register(parent, scu_data, owner);
690
+	if (IS_ERR(scu)) {
691
+		devres_free(dr);
692
+		return scu;
693
+	}
694
+
695
+	dr->scu = scu;
696
+	devres_add(parent, dr);
697
+
698
+	return scu;
699
+}
700
+EXPORT_SYMBOL_GPL(__devm_intel_scu_ipc_register);
701
+
702
+static int __init intel_scu_ipc_init(void)
703
+{
704
+	return class_register(&intel_scu_ipc_class);
705
+}
706
+subsys_initcall(intel_scu_ipc_init);
707
+
708
+static void __exit intel_scu_ipc_exit(void)
709
+{
710
+	class_unregister(&intel_scu_ipc_class);
711
+}
712
+module_exit(intel_scu_ipc_exit);