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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/pinctrl/freescale/pinctrl-imx.c
..
..
@@ -11,6 +11,7 @@
11
11
 #include <linux/init.h>
12
12
 #include <linux/io.h>
13
13
 #include <linux/mfd/syscon.h>
14
+#include <linux/module.h>
14
15
 #include <linux/of.h>
15
16
 #include <linux/of_device.h>
16
17
 #include <linux/of_address.h>
..
..
@@ -57,9 +58,11 @@
57
58
 			struct pinctrl_map **map, unsigned *num_maps)
58
59
 {
59
60
 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
61
+	const struct imx_pinctrl_soc_info *info = ipctl->info;
60
62
 	const struct group_desc *grp;
61
63
 	struct pinctrl_map *new_map;
62
64
 	struct device_node *parent;
65
+	struct imx_pin *pin;
63
66
 	int map_num = 1;
64
67
 	int i, j;
65
68
 
..
..
@@ -69,16 +72,18 @@
69
72
 	 */
70
73
 	grp = imx_pinctrl_find_group_by_name(pctldev, np->name);
71
74
 	if (!grp) {
72
-		dev_err(ipctl->dev, "unable to find group for node %s\n",
73
-			np->name);
75
+		dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np);
74
76
 		return -EINVAL;
75
77
 	}
76
78
 
77
-	for (i = 0; i < grp->num_pins; i++) {
78
-		struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
79
-
80
-		if (!(pin->config & IMX_NO_PAD_CTL))
81
-			map_num++;
79
+	if (info->flags & IMX_USE_SCU) {
80
+		map_num += grp->num_pins;
81
+	} else {
82
+		for (i = 0; i < grp->num_pins; i++) {
83
+			pin = &((struct imx_pin *)(grp->data))[i];
84
+			if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL))
85
+				map_num++;
86
+		}
82
87
 	}
83
88
 
84
89
 	new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
..
..
@@ -103,16 +108,35 @@
103
108
 	/* create config map */
104
109
 	new_map++;
105
110
 	for (i = j = 0; i < grp->num_pins; i++) {
106
-		struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
111
+		pin = &((struct imx_pin *)(grp->data))[i];
107
112
 
108
-		if (!(pin->config & IMX_NO_PAD_CTL)) {
109
-			new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
110
-			new_map[j].data.configs.group_or_pin =
113
+		/*
114
+		 * We only create config maps for SCU pads or MMIO pads that
115
+		 * are not using the default config(a.k.a IMX_NO_PAD_CTL)
116
+		 */
117
+		if (!(info->flags & IMX_USE_SCU) &&
118
+		    (pin->conf.mmio.config & IMX_NO_PAD_CTL))
119
+			continue;
120
+
121
+		new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
122
+		new_map[j].data.configs.group_or_pin =
111
123
 					pin_get_name(pctldev, pin->pin);
112
-			new_map[j].data.configs.configs = &pin->config;
124
+
125
+		if (info->flags & IMX_USE_SCU) {
126
+			/*
127
+			 * For SCU case, we set mux and conf together
128
+			 * in one IPC call
129
+			 */
130
+			new_map[j].data.configs.configs =
131
+					(unsigned long *)&pin->conf.scu;
132
+			new_map[j].data.configs.num_configs = 2;
133
+		} else {
134
+			new_map[j].data.configs.configs =
135
+					&pin->conf.mmio.config;
113
136
 			new_map[j].data.configs.num_configs = 1;
114
-			j++;
115
137
 		}
138
+
139
+		j++;
116
140
 	}
117
141
 
118
142
 	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
..
..
@@ -134,19 +158,96 @@
134
158
 	.pin_dbg_show = imx_pin_dbg_show,
135
159
 	.dt_node_to_map = imx_dt_node_to_map,
136
160
 	.dt_free_map = imx_dt_free_map,
137
-
138
161
 };
162
+
163
+static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl,
164
+				    struct imx_pin *pin)
165
+{
166
+	const struct imx_pinctrl_soc_info *info = ipctl->info;
167
+	struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
168
+	const struct imx_pin_reg *pin_reg;
169
+	unsigned int pin_id;
170
+
171
+	pin_id = pin->pin;
172
+	pin_reg = &ipctl->pin_regs[pin_id];
173
+
174
+	if (pin_reg->mux_reg == -1) {
175
+		dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
176
+			info->pins[pin_id].name);
177
+		return 0;
178
+	}
179
+
180
+	if (info->flags & SHARE_MUX_CONF_REG) {
181
+		u32 reg;
182
+
183
+		reg = readl(ipctl->base + pin_reg->mux_reg);
184
+		reg &= ~info->mux_mask;
185
+		reg |= (pin_mmio->mux_mode << info->mux_shift);
186
+		writel(reg, ipctl->base + pin_reg->mux_reg);
187
+		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
188
+			pin_reg->mux_reg, reg);
189
+	} else {
190
+		writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg);
191
+		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
192
+			pin_reg->mux_reg, pin_mmio->mux_mode);
193
+	}
194
+
195
+	/*
196
+	 * If the select input value begins with 0xff, it's a quirky
197
+	 * select input and the value should be interpreted as below.
198
+	 *     31     23      15      7        0
199
+	 *     | 0xff | shift | width | select |
200
+	 * It's used to work around the problem that the select
201
+	 * input for some pin is not implemented in the select
202
+	 * input register but in some general purpose register.
203
+	 * We encode the select input value, width and shift of
204
+	 * the bit field into input_val cell of pin function ID
205
+	 * in device tree, and then decode them here for setting
206
+	 * up the select input bits in general purpose register.
207
+	 */
208
+	if (pin_mmio->input_val >> 24 == 0xff) {
209
+		u32 val = pin_mmio->input_val;
210
+		u8 select = val & 0xff;
211
+		u8 width = (val >> 8) & 0xff;
212
+		u8 shift = (val >> 16) & 0xff;
213
+		u32 mask = ((1 << width) - 1) << shift;
214
+		/*
215
+		 * The input_reg[i] here is actually some IOMUXC general
216
+		 * purpose register, not regular select input register.
217
+		 */
218
+		val = readl(ipctl->base + pin_mmio->input_reg);
219
+		val &= ~mask;
220
+		val |= select << shift;
221
+		writel(val, ipctl->base + pin_mmio->input_reg);
222
+	} else if (pin_mmio->input_reg) {
223
+		/*
224
+		 * Regular select input register can never be at offset
225
+		 * 0, and we only print register value for regular case.
226
+		 */
227
+		if (ipctl->input_sel_base)
228
+			writel(pin_mmio->input_val, ipctl->input_sel_base +
229
+					pin_mmio->input_reg);
230
+		else
231
+			writel(pin_mmio->input_val, ipctl->base +
232
+					pin_mmio->input_reg);
233
+		dev_dbg(ipctl->dev,
234
+			"==>select_input: offset 0x%x val 0x%x\n",
235
+			pin_mmio->input_reg, pin_mmio->input_val);
236
+	}
237
+
238
+	return 0;
239
+}
139
240
 
140
241
 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
141
242
 		       unsigned group)
142
243
 {
143
244
 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
144
245
 	const struct imx_pinctrl_soc_info *info = ipctl->info;
145
-	const struct imx_pin_reg *pin_reg;
146
-	unsigned int npins, pin_id;
147
-	int i;
148
-	struct group_desc *grp = NULL;
149
-	struct function_desc *func = NULL;
246
+	struct function_desc *func;
247
+	struct group_desc *grp;
248
+	struct imx_pin *pin;
249
+	unsigned int npins;
250
+	int i, err;
150
251
 
151
252
 	/*
152
253
 	 * Configure the mux mode for each pin in the group for a specific
..
..
@@ -166,72 +267,16 @@
166
267
 		func->name, grp->name);
167
268
 
168
269
 	for (i = 0; i < npins; i++) {
169
-		struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
170
-
171
-		pin_id = pin->pin;
172
-		pin_reg = &ipctl->pin_regs[pin_id];
173
-
174
-		if (pin_reg->mux_reg == -1) {
175
-			dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
176
-				info->pins[pin_id].name);
177
-			continue;
178
-		}
179
-
180
-		if (info->flags & SHARE_MUX_CONF_REG) {
181
-			u32 reg;
182
-			reg = readl(ipctl->base + pin_reg->mux_reg);
183
-			reg &= ~info->mux_mask;
184
-			reg |= (pin->mux_mode << info->mux_shift);
185
-			writel(reg, ipctl->base + pin_reg->mux_reg);
186
-			dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
187
-				pin_reg->mux_reg, reg);
188
-		} else {
189
-			writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
190
-			dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
191
-				pin_reg->mux_reg, pin->mux_mode);
192
-		}
193
-
194
270
 		/*
195
-		 * If the select input value begins with 0xff, it's a quirky
196
-		 * select input and the value should be interpreted as below.
197
-		 *     31     23      15      7        0
198
-		 *     | 0xff | shift | width | select |
199
-		 * It's used to work around the problem that the select
200
-		 * input for some pin is not implemented in the select
201
-		 * input register but in some general purpose register.
202
-		 * We encode the select input value, width and shift of
203
-		 * the bit field into input_val cell of pin function ID
204
-		 * in device tree, and then decode them here for setting
205
-		 * up the select input bits in general purpose register.
271
+		 * For IMX_USE_SCU case, we postpone the mux setting
272
+		 * until config is set as we can set them together
273
+		 * in one IPC call
206
274
 		 */
207
-		if (pin->input_val >> 24 == 0xff) {
208
-			u32 val = pin->input_val;
209
-			u8 select = val & 0xff;
210
-			u8 width = (val >> 8) & 0xff;
211
-			u8 shift = (val >> 16) & 0xff;
212
-			u32 mask = ((1 << width) - 1) << shift;
213
-			/*
214
-			 * The input_reg[i] here is actually some IOMUXC general
215
-			 * purpose register, not regular select input register.
216
-			 */
217
-			val = readl(ipctl->base + pin->input_reg);
218
-			val &= ~mask;
219
-			val |= select << shift;
220
-			writel(val, ipctl->base + pin->input_reg);
221
-		} else if (pin->input_reg) {
222
-			/*
223
-			 * Regular select input register can never be at offset
224
-			 * 0, and we only print register value for regular case.
225
-			 */
226
-			if (ipctl->input_sel_base)
227
-				writel(pin->input_val, ipctl->input_sel_base +
228
-						pin->input_reg);
229
-			else
230
-				writel(pin->input_val, ipctl->base +
231
-						pin->input_reg);
232
-			dev_dbg(ipctl->dev,
233
-				"==>select_input: offset 0x%x val 0x%x\n",
234
-				pin->input_reg, pin->input_val);
275
+		pin = &((struct imx_pin *)(grp->data))[i];
276
+		if (!(info->flags & IMX_USE_SCU)) {
277
+			err = imx_pmx_set_one_pin_mmio(ipctl, pin);
278
+			if (err)
279
+				return err;
235
280
 		}
236
281
 	}
237
282
 
..
..
@@ -301,8 +346,8 @@
301
346
 	return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
302
347
 }
303
348
 
304
-static int imx_pinconf_get(struct pinctrl_dev *pctldev,
305
-			     unsigned pin_id, unsigned long *config)
349
+static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id,
350
+				unsigned long *config)
306
351
 {
307
352
 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
308
353
 	const struct imx_pinctrl_soc_info *info = ipctl->info;
..
..
@@ -322,9 +367,21 @@
322
367
 	return 0;
323
368
 }
324
369
 
325
-static int imx_pinconf_set(struct pinctrl_dev *pctldev,
326
-			     unsigned pin_id, unsigned long *configs,
327
-			     unsigned num_configs)
370
+static int imx_pinconf_get(struct pinctrl_dev *pctldev,
371
+			   unsigned pin_id, unsigned long *config)
372
+{
373
+	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
374
+	const struct imx_pinctrl_soc_info *info = ipctl->info;
375
+
376
+	if (info->flags & IMX_USE_SCU)
377
+		return info->imx_pinconf_get(pctldev, pin_id, config);
378
+	else
379
+		return imx_pinconf_get_mmio(pctldev, pin_id, config);
380
+}
381
+
382
+static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev,
383
+				unsigned pin_id, unsigned long *configs,
384
+				unsigned num_configs)
328
385
 {
329
386
 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
330
387
 	const struct imx_pinctrl_soc_info *info = ipctl->info;
..
..
@@ -359,19 +416,48 @@
359
416
 	return 0;
360
417
 }
361
418
 
419
+static int imx_pinconf_set(struct pinctrl_dev *pctldev,
420
+			   unsigned pin_id, unsigned long *configs,
421
+			   unsigned num_configs)
422
+{
423
+	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
424
+	const struct imx_pinctrl_soc_info *info = ipctl->info;
425
+
426
+	if (info->flags & IMX_USE_SCU)
427
+		return info->imx_pinconf_set(pctldev, pin_id,
428
+					   configs, num_configs);
429
+	else
430
+		return imx_pinconf_set_mmio(pctldev, pin_id,
431
+					    configs, num_configs);
432
+}
433
+
362
434
 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
363
435
 				   struct seq_file *s, unsigned pin_id)
364
436
 {
365
437
 	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
366
-	const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
438
+	const struct imx_pinctrl_soc_info *info = ipctl->info;
439
+	const struct imx_pin_reg *pin_reg;
367
440
 	unsigned long config;
441
+	int ret;
368
442
 
369
-	if (!pin_reg || pin_reg->conf_reg == -1) {
370
-		seq_puts(s, "N/A");
371
-		return;
443
+	if (info->flags & IMX_USE_SCU) {
444
+		ret = info->imx_pinconf_get(pctldev, pin_id, &config);
445
+		if (ret) {
446
+			dev_err(ipctl->dev, "failed to get %s pinconf\n",
447
+				pin_get_name(pctldev, pin_id));
448
+			seq_puts(s, "N/A");
449
+			return;
450
+		}
451
+	} else {
452
+		pin_reg = &ipctl->pin_regs[pin_id];
453
+		if (pin_reg->conf_reg == -1) {
454
+			seq_puts(s, "N/A");
455
+			return;
456
+		}
457
+
458
+		config = readl(ipctl->base + pin_reg->conf_reg);
372
459
 	}
373
460
 
374
-	config = readl(ipctl->base + pin_reg->conf_reg);
375
461
 	seq_printf(s, "0x%lx", config);
376
462
 }
377
463
 
..
..
@@ -419,9 +505,65 @@
419
505
  *     <mux_reg conf_reg input_reg mux_mode input_val>
420
506
  * SHARE_MUX_CONF_REG:
421
507
  *     <mux_conf_reg input_reg mux_mode input_val>
508
+ * IMX_USE_SCU:
509
+ *	<pin_id mux_mode>
422
510
  */
423
511
 #define FSL_PIN_SIZE 24
424
512
 #define FSL_PIN_SHARE_SIZE 20
513
+#define FSL_SCU_PIN_SIZE 12
514
+
515
+static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl,
516
+				       unsigned int *pin_id, struct imx_pin *pin,
517
+				       const __be32 **list_p,
518
+				       struct device_node *np)
519
+{
520
+	const struct imx_pinctrl_soc_info *info = ipctl->info;
521
+	struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
522
+	struct imx_pin_reg *pin_reg;
523
+	const __be32 *list = *list_p;
524
+	u32 mux_reg, conf_reg;
525
+	u32 config;
526
+
527
+	mux_reg = be32_to_cpu(*list++);
528
+
529
+	if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
530
+		mux_reg = -1;
531
+
532
+	if (info->flags & SHARE_MUX_CONF_REG) {
533
+		conf_reg = mux_reg;
534
+	} else {
535
+		conf_reg = be32_to_cpu(*list++);
536
+		if (!conf_reg)
537
+			conf_reg = -1;
538
+	}
539
+
540
+	*pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
541
+	pin_reg = &ipctl->pin_regs[*pin_id];
542
+	pin->pin = *pin_id;
543
+	pin_reg->mux_reg = mux_reg;
544
+	pin_reg->conf_reg = conf_reg;
545
+	pin_mmio->input_reg = be32_to_cpu(*list++);
546
+	pin_mmio->mux_mode = be32_to_cpu(*list++);
547
+	pin_mmio->input_val = be32_to_cpu(*list++);
548
+
549
+	if (info->generic_pinconf) {
550
+		/* generic pin config decoded */
551
+		pin_mmio->config = imx_pinconf_parse_generic_config(np, ipctl);
552
+	} else {
553
+		/* legacy pin config read from devicetree */
554
+		config = be32_to_cpu(*list++);
555
+
556
+		/* SION bit is in mux register */
557
+		if (config & IMX_PAD_SION)
558
+			pin_mmio->mux_mode |= IOMUXC_CONFIG_SION;
559
+		pin_mmio->config = config & ~IMX_PAD_SION;
560
+	}
561
+
562
+	*list_p = list;
563
+
564
+	dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name,
565
+			     pin_mmio->mux_mode, pin_mmio->config);
566
+}
425
567
 
426
568
 static int imx_pinctrl_parse_groups(struct device_node *np,
427
569
 				    struct group_desc *grp,
..
..
@@ -429,14 +571,16 @@
429
571
 				    u32 index)
430
572
 {
431
573
 	const struct imx_pinctrl_soc_info *info = ipctl->info;
574
+	struct imx_pin *pin;
432
575
 	int size, pin_size;
433
576
 	const __be32 *list;
434
577
 	int i;
435
-	u32 config;
436
578
 
437
-	dev_dbg(ipctl->dev, "group(%d): %s\n", index, np->name);
579
+	dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np);
438
580
 
439
-	if (info->flags & SHARE_MUX_CONF_REG)
581
+	if (info->flags & IMX_USE_SCU)
582
+		pin_size = FSL_SCU_PIN_SIZE;
583
+	else if (info->flags & SHARE_MUX_CONF_REG)
440
584
 		pin_size = FSL_PIN_SHARE_SIZE;
441
585
 	else
442
586
 		pin_size = FSL_PIN_SIZE;
..
..
@@ -473,9 +617,6 @@
473
617
 		return -EINVAL;
474
618
 	}
475
619
 
476
-	/* first try to parse the generic pin config */
477
-	config = imx_pinconf_parse_generic_config(np, ipctl);
478
-
479
620
 	grp->num_pins = size / pin_size;
480
621
 	grp->data = devm_kcalloc(ipctl->dev,
481
622
 				 grp->num_pins, sizeof(struct imx_pin),
..
..
@@ -487,48 +628,13 @@
487
628
 		return -ENOMEM;
488
629
 
489
630
 	for (i = 0; i < grp->num_pins; i++) {
490
-		u32 mux_reg = be32_to_cpu(*list++);
491
-		u32 conf_reg;
492
-		unsigned int pin_id;
493
-		struct imx_pin_reg *pin_reg;
494
-		struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
495
-
496
-		if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
497
-			mux_reg = -1;
498
-
499
-		if (info->flags & SHARE_MUX_CONF_REG) {
500
-			conf_reg = mux_reg;
501
-		} else {
502
-			conf_reg = be32_to_cpu(*list++);
503
-			if (!conf_reg)
504
-				conf_reg = -1;
505
-		}
506
-
507
-		pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
508
-		pin_reg = &ipctl->pin_regs[pin_id];
509
-		pin->pin = pin_id;
510
-		grp->pins[i] = pin_id;
511
-		pin_reg->mux_reg = mux_reg;
512
-		pin_reg->conf_reg = conf_reg;
513
-		pin->input_reg = be32_to_cpu(*list++);
514
-		pin->mux_mode = be32_to_cpu(*list++);
515
-		pin->input_val = be32_to_cpu(*list++);
516
-
517
-		if (info->generic_pinconf) {
518
-			/* generic pin config decoded */
519
-			pin->config = config;
520
-		} else {
521
-			/* legacy pin config read from devicetree */
522
-			config = be32_to_cpu(*list++);
523
-
524
-			/* SION bit is in mux register */
525
-			if (config & IMX_PAD_SION)
526
-				pin->mux_mode |= IOMUXC_CONFIG_SION;
527
-			pin->config = config & ~IMX_PAD_SION;
528
-		}
529
-
530
-		dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
531
-				pin->mux_mode, pin->config);
631
+		pin = &((struct imx_pin *)(grp->data))[i];
632
+		if (info->flags & IMX_USE_SCU)
633
+			info->imx_pinctrl_parse_pin(ipctl, &grp->pins[i],
634
+						  pin, &list);
635
+		else
636
+			imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
637
+						   pin, &list, np);
532
638
 	}
533
639
 
534
640
 	return 0;
..
..
@@ -544,7 +650,7 @@
544
650
 	struct group_desc *grp;
545
651
 	u32 i = 0;
546
652
 
547
-	dev_dbg(pctl->dev, "parse function(%d): %s\n", index, np->name);
653
+	dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np);
548
654
 
549
655
 	func = pinmux_generic_get_function(pctl, index);
550
656
 	if (!func)
..
..
@@ -567,8 +673,10 @@
567
673
 
568
674
 		grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc),
569
675
 				   GFP_KERNEL);
570
-		if (!grp)
676
+		if (!grp) {
677
+			of_node_put(child);
571
678
 			return -ENOMEM;
679
+		}
572
680
 
573
681
 		mutex_lock(&ipctl->mutex);
574
682
 		radix_tree_insert(&pctl->pin_group_tree,
..
..
@@ -592,12 +700,17 @@
592
700
 	struct device_node *pinctrl_np;
593
701
 
594
702
 	for_each_child_of_node(np, function_np) {
595
-		if (of_property_read_bool(function_np, "fsl,pins"))
703
+		if (of_property_read_bool(function_np, "fsl,pins")) {
704
+			of_node_put(function_np);
596
705
 			return true;
706
+		}
597
707
 
598
708
 		for_each_child_of_node(function_np, pinctrl_np) {
599
-			if (of_property_read_bool(pinctrl_np, "fsl,pins"))
709
+			if (of_property_read_bool(pinctrl_np, "fsl,pins")) {
710
+				of_node_put(pinctrl_np);
711
+				of_node_put(function_np);
600
712
 				return false;
713
+			}
601
714
 		}
602
715
 	}
603
716
 
..
..
@@ -670,7 +783,6 @@
670
783
 	struct pinctrl_desc *imx_pinctrl_desc;
671
784
 	struct device_node *np;
672
785
 	struct imx_pinctrl *ipctl;
673
-	struct resource *res;
674
786
 	struct regmap *gpr;
675
787
 	int ret, i;
676
788
 
..
..
@@ -690,35 +802,36 @@
690
802
 	if (!ipctl)
691
803
 		return -ENOMEM;
692
804
 
693
-	ipctl->pin_regs = devm_kmalloc_array(&pdev->dev,
694
-				       info->npins, sizeof(*ipctl->pin_regs),
695
-				       GFP_KERNEL);
696
-	if (!ipctl->pin_regs)
697
-		return -ENOMEM;
805
+	if (!(info->flags & IMX_USE_SCU)) {
806
+		ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
807
+						     sizeof(*ipctl->pin_regs),
808
+						     GFP_KERNEL);
809
+		if (!ipctl->pin_regs)
810
+			return -ENOMEM;
698
811
 
699
-	for (i = 0; i < info->npins; i++) {
700
-		ipctl->pin_regs[i].mux_reg = -1;
701
-		ipctl->pin_regs[i].conf_reg = -1;
702
-	}
703
-
704
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
705
-	ipctl->base = devm_ioremap_resource(&pdev->dev, res);
706
-	if (IS_ERR(ipctl->base))
707
-		return PTR_ERR(ipctl->base);
708
-
709
-	if (of_property_read_bool(dev_np, "fsl,input-sel")) {
710
-		np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
711
-		if (!np) {
712
-			dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
713
-			return -EINVAL;
812
+		for (i = 0; i < info->npins; i++) {
813
+			ipctl->pin_regs[i].mux_reg = -1;
814
+			ipctl->pin_regs[i].conf_reg = -1;
714
815
 		}
715
816
 
716
-		ipctl->input_sel_base = of_iomap(np, 0);
717
-		of_node_put(np);
718
-		if (!ipctl->input_sel_base) {
719
-			dev_err(&pdev->dev,
720
-				"iomuxc input select base address not found\n");
721
-			return -ENOMEM;
817
+		ipctl->base = devm_platform_ioremap_resource(pdev, 0);
818
+		if (IS_ERR(ipctl->base))
819
+			return PTR_ERR(ipctl->base);
820
+
821
+		if (of_property_read_bool(dev_np, "fsl,input-sel")) {
822
+			np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
823
+			if (!np) {
824
+				dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
825
+				return -EINVAL;
826
+			}
827
+
828
+			ipctl->input_sel_base = of_iomap(np, 0);
829
+			of_node_put(np);
830
+			if (!ipctl->input_sel_base) {
831
+				dev_err(&pdev->dev,
832
+					"iomuxc input select base address not found\n");
833
+				return -ENOMEM;
834
+			}
722
835
 		}
723
836
 	}
724
837
 
..
..
@@ -765,3 +878,28 @@
765
878
 
766
879
 	return pinctrl_enable(ipctl->pctl);
767
880
 }
881
+EXPORT_SYMBOL_GPL(imx_pinctrl_probe);
882
+
883
+static int __maybe_unused imx_pinctrl_suspend(struct device *dev)
884
+{
885
+	struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
886
+
887
+	return pinctrl_force_sleep(ipctl->pctl);
888
+}
889
+
890
+static int __maybe_unused imx_pinctrl_resume(struct device *dev)
891
+{
892
+	struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
893
+
894
+	return pinctrl_force_default(ipctl->pctl);
895
+}
896
+
897
+const struct dev_pm_ops imx_pinctrl_pm_ops = {
898
+	SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend,
899
+					imx_pinctrl_resume)
900
+};
901
+EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops);
902
+
903
+MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
904
+MODULE_DESCRIPTION("NXP i.MX common pinctrl driver");
905
+MODULE_LICENSE("GPL v2");