forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/pci/hotplug/pciehp_hpc.c
....@@ -12,20 +12,38 @@
1212  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
1313  */
1414 
15
+#define dev_fmt(fmt) "pciehp: " fmt
16
+
17
+#include <linux/dmi.h>
1518 #include <linux/kernel.h>
16
-#include <linux/module.h>
1719 #include <linux/types.h>
18
-#include <linux/signal.h>
1920 #include <linux/jiffies.h>
2021 #include <linux/kthread.h>
2122 #include <linux/pci.h>
2223 #include <linux/pm_runtime.h>
2324 #include <linux/interrupt.h>
24
-#include <linux/time.h>
2525 #include <linux/slab.h>
2626 
2727 #include "../pci.h"
2828 #include "pciehp.h"
29
+
30
+static const struct dmi_system_id inband_presence_disabled_dmi_table[] = {
31
+	/*
32
+	 * Match all Dell systems, as some Dell systems have inband
33
+	 * presence disabled on NVMe slots (but don't support the bit to
34
+	 * report it). Setting inband presence disabled should have no
35
+	 * negative effect, except on broken hotplug slots that never
36
+	 * assert presence detect--and those will still work, they will
37
+	 * just have a bit of extra delay before being probed.
38
+	 */
39
+	{
40
+		.ident = "Dell System",
41
+		.matches = {
42
+			DMI_MATCH(DMI_OEM_STRING, "Dell System"),
43
+		},
44
+	},
45
+	{}
46
+};
2947 
3048 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
3149 {
....@@ -43,13 +61,13 @@
4361 	if (pciehp_poll_mode) {
4462 		ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl,
4563 						"pciehp_poll-%s",
46
-						slot_name(ctrl->slot));
64
+						slot_name(ctrl));
4765 		return PTR_ERR_OR_ZERO(ctrl->poll_thread);
4866 	}
4967 
5068 	/* Installs the interrupt handler */
5169 	retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist,
52
-				      IRQF_SHARED, MY_NAME, ctrl);
70
+				      IRQF_SHARED, "pciehp", ctrl);
5371 	if (retval)
5472 		ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
5573 			 irq);
....@@ -69,7 +87,7 @@
6987 	struct pci_dev *pdev = ctrl_dev(ctrl);
7088 	u16 slot_status;
7189 
72
-	while (true) {
90
+	do {
7391 		pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
7492 		if (slot_status == (u16) ~0) {
7593 			ctrl_info(ctrl, "%s: no response from device\n",
....@@ -80,13 +98,13 @@
8098 		if (slot_status & PCI_EXP_SLTSTA_CC) {
8199 			pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
82100 						   PCI_EXP_SLTSTA_CC);
101
+			ctrl->cmd_busy = 0;
102
+			smp_mb();
83103 			return 1;
84104 		}
85
-		if (timeout < 0)
86
-			break;
87105 		msleep(10);
88106 		timeout -= 10;
89
-	}
107
+	} while (timeout >= 0);
90108 	return 0;	/* timeout */
91109 }
92110 
....@@ -159,9 +177,9 @@
159177 	slot_ctrl |= (cmd & mask);
160178 	ctrl->cmd_busy = 1;
161179 	smp_mb();
180
+	ctrl->slot_ctrl = slot_ctrl;
162181 	pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
163182 	ctrl->cmd_started = jiffies;
164
-	ctrl->slot_ctrl = slot_ctrl;
165183 
166184 	/*
167185 	 * Controllers with the Intel CF118 and similar errata advertise
....@@ -202,26 +220,31 @@
202220 	pcie_do_write_cmd(ctrl, cmd, mask, false);
203221 }
204222 
205
-bool pciehp_check_link_active(struct controller *ctrl)
223
+/**
224
+ * pciehp_check_link_active() - Is the link active
225
+ * @ctrl: PCIe hotplug controller
226
+ *
227
+ * Check whether the downstream link is currently active. Note it is
228
+ * possible that the card is removed immediately after this so the
229
+ * caller may need to take it into account.
230
+ *
231
+ * If the hotplug controller itself is not available anymore returns
232
+ * %-ENODEV.
233
+ */
234
+int pciehp_check_link_active(struct controller *ctrl)
206235 {
207236 	struct pci_dev *pdev = ctrl_dev(ctrl);
208237 	u16 lnk_status;
209
-	bool ret;
238
+	int ret;
210239 
211
-	pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
240
+	ret = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
241
+	if (ret == PCIBIOS_DEVICE_NOT_FOUND || lnk_status == (u16)~0)
242
+		return -ENODEV;
243
+
212244 	ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
213
-
214
-	if (ret)
215
-		ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
245
+	ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
216246 
217247 	return ret;
218
-}
219
-
220
-static void pcie_wait_link_active(struct controller *ctrl)
221
-{
222
-	struct pci_dev *pdev = ctrl_dev(ctrl);
223
-
224
-	pcie_wait_for_link(pdev, true);
225248 }
226249 
227250 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
....@@ -242,12 +265,26 @@
242265 		delay -= step;
243266 	} while (delay > 0);
244267 
245
-	if (count > 1 && pciehp_debug)
246
-		printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
268
+	if (count > 1)
269
+		pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
247270 			pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
248271 			PCI_FUNC(devfn), count, step, l);
249272 
250273 	return found;
274
+}
275
+
276
+static void pcie_wait_for_presence(struct pci_dev *pdev)
277
+{
278
+	int timeout = 1250;
279
+	u16 slot_status;
280
+
281
+	do {
282
+		pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
283
+		if (slot_status & PCI_EXP_SLTSTA_PDS)
284
+			return;
285
+		msleep(10);
286
+		timeout -= 10;
287
+	} while (timeout > 0);
251288 }
252289 
253290 int pciehp_check_link_status(struct controller *ctrl)
....@@ -256,18 +293,14 @@
256293 	bool found;
257294 	u16 lnk_status;
258295 
259
-	/*
260
-	 * Data Link Layer Link Active Reporting must be capable for
261
-	 * hot-plug capable downstream port. But old controller might
262
-	 * not implement it. In this case, we wait for 1000 ms.
263
-	*/
264
-	if (ctrl->link_active_reporting)
265
-		pcie_wait_link_active(ctrl);
266
-	else
267
-		msleep(1000);
296
+	if (!pcie_wait_for_link(pdev, true)) {
297
+		ctrl_info(ctrl, "Slot(%s): No link\n", slot_name(ctrl));
298
+		return -1;
299
+	}
268300 
269
-	/* wait 100ms before read pci conf, and try in 1s */
270
-	msleep(100);
301
+	if (ctrl->inband_presence_disabled)
302
+		pcie_wait_for_presence(pdev);
303
+
271304 	found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
272305 					PCI_DEVFN(0, 0));
273306 
....@@ -280,15 +313,18 @@
280313 	ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
281314 	if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
282315 	    !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
283
-		ctrl_err(ctrl, "link training error: status %#06x\n",
284
-			 lnk_status);
316
+		ctrl_info(ctrl, "Slot(%s): Cannot train link: status %#06x\n",
317
+			  slot_name(ctrl), lnk_status);
285318 		return -1;
286319 	}
287320 
288321 	pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
289322 
290
-	if (!found)
323
+	if (!found) {
324
+		ctrl_info(ctrl, "Slot(%s): No device found\n",
325
+			  slot_name(ctrl));
291326 		return -1;
327
+	}
292328 
293329 	return 0;
294330 }
....@@ -318,8 +354,8 @@
318354 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
319355 				    u8 *status)
320356 {
321
-	struct slot *slot = hotplug_slot->private;
322
-	struct pci_dev *pdev = ctrl_dev(slot->ctrl);
357
+	struct controller *ctrl = to_ctrl(hotplug_slot);
358
+	struct pci_dev *pdev = ctrl_dev(ctrl);
323359 	u16 slot_ctrl;
324360 
325361 	pci_config_pm_runtime_get(pdev);
....@@ -329,9 +365,9 @@
329365 	return 0;
330366 }
331367 
332
-void pciehp_get_attention_status(struct slot *slot, u8 *status)
368
+int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status)
333369 {
334
-	struct controller *ctrl = slot->ctrl;
370
+	struct controller *ctrl = to_ctrl(hotplug_slot);
335371 	struct pci_dev *pdev = ctrl_dev(ctrl);
336372 	u16 slot_ctrl;
337373 
....@@ -355,11 +391,12 @@
355391 		*status = 0xFF;
356392 		break;
357393 	}
394
+
395
+	return 0;
358396 }
359397 
360
-void pciehp_get_power_status(struct slot *slot, u8 *status)
398
+void pciehp_get_power_status(struct controller *ctrl, u8 *status)
361399 {
362
-	struct controller *ctrl = slot->ctrl;
363400 	struct pci_dev *pdev = ctrl_dev(ctrl);
364401 	u16 slot_ctrl;
365402 
....@@ -380,27 +417,66 @@
380417 	}
381418 }
382419 
383
-void pciehp_get_latch_status(struct slot *slot, u8 *status)
420
+void pciehp_get_latch_status(struct controller *ctrl, u8 *status)
384421 {
385
-	struct pci_dev *pdev = ctrl_dev(slot->ctrl);
422
+	struct pci_dev *pdev = ctrl_dev(ctrl);
386423 	u16 slot_status;
387424 
388425 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
389426 	*status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
390427 }
391428 
392
-void pciehp_get_adapter_status(struct slot *slot, u8 *status)
429
+/**
430
+ * pciehp_card_present() - Is the card present
431
+ * @ctrl: PCIe hotplug controller
432
+ *
433
+ * Function checks whether the card is currently present in the slot and
434
+ * in that case returns true. Note it is possible that the card is
435
+ * removed immediately after the check so the caller may need to take
436
+ * this into account.
437
+ *
438
+ * It the hotplug controller itself is not available anymore returns
439
+ * %-ENODEV.
440
+ */
441
+int pciehp_card_present(struct controller *ctrl)
393442 {
394
-	struct pci_dev *pdev = ctrl_dev(slot->ctrl);
443
+	struct pci_dev *pdev = ctrl_dev(ctrl);
395444 	u16 slot_status;
445
+	int ret;
396446 
397
-	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
398
-	*status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
447
+	ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
448
+	if (ret == PCIBIOS_DEVICE_NOT_FOUND || slot_status == (u16)~0)
449
+		return -ENODEV;
450
+
451
+	return !!(slot_status & PCI_EXP_SLTSTA_PDS);
399452 }
400453 
401
-int pciehp_query_power_fault(struct slot *slot)
454
+/**
455
+ * pciehp_card_present_or_link_active() - whether given slot is occupied
456
+ * @ctrl: PCIe hotplug controller
457
+ *
458
+ * Unlike pciehp_card_present(), which determines presence solely from the
459
+ * Presence Detect State bit, this helper also returns true if the Link Active
460
+ * bit is set.  This is a concession to broken hotplug ports which hardwire
461
+ * Presence Detect State to zero, such as Wilocity's [1ae9:0200].
462
+ *
463
+ * Returns: %1 if the slot is occupied and %0 if it is not. If the hotplug
464
+ *	    port is not present anymore returns %-ENODEV.
465
+ */
466
+int pciehp_card_present_or_link_active(struct controller *ctrl)
402467 {
403
-	struct pci_dev *pdev = ctrl_dev(slot->ctrl);
468
+	int ret;
469
+
470
+	ret = pciehp_card_present(ctrl);
471
+	if (ret)
472
+		return ret;
473
+
474
+	return pciehp_check_link_active(ctrl);
475
+}
476
+
477
+int pciehp_query_power_fault(struct controller *ctrl)
478
+{
479
+	struct pci_dev *pdev = ctrl_dev(ctrl);
404480 	u16 slot_status;
405481 
406482 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
....@@ -410,8 +486,7 @@
410486 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
411487 				    u8 status)
412488 {
413
-	struct slot *slot = hotplug_slot->private;
414
-	struct controller *ctrl = slot->ctrl;
489
+	struct controller *ctrl = to_ctrl(hotplug_slot);
415490 	struct pci_dev *pdev = ctrl_dev(ctrl);
416491 
417492 	pci_config_pm_runtime_get(pdev);
....@@ -421,77 +496,44 @@
421496 	return 0;
422497 }
423498 
424
-void pciehp_set_attention_status(struct slot *slot, u8 value)
499
+/**
500
+ * pciehp_set_indicators() - set attention indicator, power indicator, or both
501
+ * @ctrl: PCIe hotplug controller
502
+ * @pwr: one of:
503
+ *	PCI_EXP_SLTCTL_PWR_IND_ON
504
+ *	PCI_EXP_SLTCTL_PWR_IND_BLINK
505
+ *	PCI_EXP_SLTCTL_PWR_IND_OFF
506
+ * @attn: one of:
507
+ *	PCI_EXP_SLTCTL_ATTN_IND_ON
508
+ *	PCI_EXP_SLTCTL_ATTN_IND_BLINK
509
+ *	PCI_EXP_SLTCTL_ATTN_IND_OFF
510
+ *
511
+ * Either @pwr or @attn can also be INDICATOR_NOOP to leave that indicator
512
+ * unchanged.
513
+ */
514
+void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn)
425515 {
426
-	struct controller *ctrl = slot->ctrl;
427
-	u16 slot_cmd;
516
+	u16 cmd = 0, mask = 0;
428517 
429
-	if (!ATTN_LED(ctrl))
430
-		return;
431
-
432
-	switch (value) {
433
-	case 0:		/* turn off */
434
-		slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
435
-		break;
436
-	case 1:		/* turn on */
437
-		slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
438
-		break;
439
-	case 2:		/* turn blink */
440
-		slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
441
-		break;
442
-	default:
443
-		return;
518
+	if (PWR_LED(ctrl) && pwr != INDICATOR_NOOP) {
519
+		cmd |= (pwr & PCI_EXP_SLTCTL_PIC);
520
+		mask |= PCI_EXP_SLTCTL_PIC;
444521 	}
445
-	pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
446
-	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
447
-		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
522
+
523
+	if (ATTN_LED(ctrl) && attn != INDICATOR_NOOP) {
524
+		cmd |= (attn & PCI_EXP_SLTCTL_AIC);
525
+		mask |= PCI_EXP_SLTCTL_AIC;
526
+	}
527
+
528
+	if (cmd) {
529
+		pcie_write_cmd_nowait(ctrl, cmd, mask);
530
+		ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
531
+			 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
532
+	}
448533 }
449534 
450
-void pciehp_green_led_on(struct slot *slot)
535
+int pciehp_power_on_slot(struct controller *ctrl)
451536 {
452
-	struct controller *ctrl = slot->ctrl;
453
-
454
-	if (!PWR_LED(ctrl))
455
-		return;
456
-
457
-	pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
458
-			      PCI_EXP_SLTCTL_PIC);
459
-	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
460
-		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
461
-		 PCI_EXP_SLTCTL_PWR_IND_ON);
462
-}
463
-
464
-void pciehp_green_led_off(struct slot *slot)
465
-{
466
-	struct controller *ctrl = slot->ctrl;
467
-
468
-	if (!PWR_LED(ctrl))
469
-		return;
470
-
471
-	pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
472
-			      PCI_EXP_SLTCTL_PIC);
473
-	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
474
-		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
475
-		 PCI_EXP_SLTCTL_PWR_IND_OFF);
476
-}
477
-
478
-void pciehp_green_led_blink(struct slot *slot)
479
-{
480
-	struct controller *ctrl = slot->ctrl;
481
-
482
-	if (!PWR_LED(ctrl))
483
-		return;
484
-
485
-	pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
486
-			      PCI_EXP_SLTCTL_PIC);
487
-	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
488
-		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
489
-		 PCI_EXP_SLTCTL_PWR_IND_BLINK);
490
-}
491
-
492
-int pciehp_power_on_slot(struct slot *slot)
493
-{
494
-	struct controller *ctrl = slot->ctrl;
495537 	struct pci_dev *pdev = ctrl_dev(ctrl);
496538 	u16 slot_status;
497539 	int retval;
....@@ -515,14 +557,38 @@
515557 	return retval;
516558 }
517559 
518
-void pciehp_power_off_slot(struct slot *slot)
560
+void pciehp_power_off_slot(struct controller *ctrl)
519561 {
520
-	struct controller *ctrl = slot->ctrl;
521
-
522562 	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
523563 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
524564 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
525565 		 PCI_EXP_SLTCTL_PWR_OFF);
566
+}
567
+
568
+static void pciehp_ignore_dpc_link_change(struct controller *ctrl,
569
+					  struct pci_dev *pdev, int irq)
570
+{
571
+	/*
572
+	 * Ignore link changes which occurred while waiting for DPC recovery.
573
+	 * Could be several if DPC triggered multiple times consecutively.
574
+	 */
575
+	synchronize_hardirq(irq);
576
+	atomic_and(~PCI_EXP_SLTSTA_DLLSC, &ctrl->pending_events);
577
+	if (pciehp_poll_mode)
578
+		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
579
+					   PCI_EXP_SLTSTA_DLLSC);
580
+	ctrl_info(ctrl, "Slot(%s): Link Down/Up ignored (recovered by DPC)\n",
581
+		  slot_name(ctrl));
582
+
583
+	/*
584
+	 * If the link is unexpectedly down after successful recovery,
585
+	 * the corresponding link change may have been ignored above.
586
+	 * Synthesize it to ensure that it is acted on.
587
+	 */
588
+	down_read_nested(&ctrl->reset_lock, ctrl->depth);
589
+	if (!pciehp_check_link_active(ctrl))
590
+		pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC);
591
+	up_read(&ctrl->reset_lock);
526592 }
527593 
528594 static irqreturn_t pciehp_isr(int irq, void *dev_id)
....@@ -533,9 +599,11 @@
533599 	u16 status, events = 0;
534600 
535601 	/*
536
-	 * Interrupts only occur in D3hot or shallower (PCIe r4.0, sec 6.7.3.4).
602
+	 * Interrupts only occur in D3hot or shallower and only if enabled
603
+	 * in the Slot Control register (PCIe r4.0, sec 6.7.3.4).
537604 	 */
538
-	if (pdev->current_state == PCI_D3cold)
605
+	if (pdev->current_state == PCI_D3cold ||
606
+	    (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
539607 		return IRQ_NONE;
540608 
541609 	/*
....@@ -576,6 +644,8 @@
576644 	 */
577645 	if (ctrl->power_fault_detected)
578646 		status &= ~PCI_EXP_SLTSTA_PFD;
647
+	else if (status & PCI_EXP_SLTSTA_PFD)
648
+		ctrl->power_fault_detected = true;
579649 
580650 	events |= status;
581651 	if (!events) {
....@@ -585,7 +655,7 @@
585655 	}
586656 
587657 	if (status) {
588
-		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
658
+		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, status);
589659 
590660 		/*
591661 		 * In MSI mode, all event bits must be zero before the port
....@@ -630,7 +700,6 @@
630700 {
631701 	struct controller *ctrl = (struct controller *)dev_id;
632702 	struct pci_dev *pdev = ctrl_dev(ctrl);
633
-	struct slot *slot = ctrl->slot;
634703 	irqreturn_t ret;
635704 	u32 events;
636705 
....@@ -655,27 +724,36 @@
655724 	/* Check Attention Button Pressed */
656725 	if (events & PCI_EXP_SLTSTA_ABP) {
657726 		ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
658
-			  slot_name(slot));
659
-		pciehp_handle_button_press(slot);
727
+			  slot_name(ctrl));
728
+		pciehp_handle_button_press(ctrl);
660729 	}
661730 
662731 	/* Check Power Fault Detected */
663
-	if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
664
-		ctrl->power_fault_detected = 1;
665
-		ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));
666
-		pciehp_set_attention_status(slot, 1);
667
-		pciehp_green_led_off(slot);
732
+	if (events & PCI_EXP_SLTSTA_PFD) {
733
+		ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl));
734
+		pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
735
+				      PCI_EXP_SLTCTL_ATTN_IND_ON);
736
+	}
737
+
738
+	/*
739
+	 * Ignore Link Down/Up events caused by Downstream Port Containment
740
+	 * if recovery from the error succeeded.
741
+	 */
742
+	if ((events & PCI_EXP_SLTSTA_DLLSC) && pci_dpc_recovered(pdev) &&
743
+	    ctrl->state == ON_STATE) {
744
+		events &= ~PCI_EXP_SLTSTA_DLLSC;
745
+		pciehp_ignore_dpc_link_change(ctrl, pdev, irq);
668746 	}
669747 
670748 	/*
671749 	 * Disable requests have higher priority than Presence Detect Changed
672750 	 * or Data Link Layer State Changed events.
673751 	 */
674
-	down_read(&ctrl->reset_lock);
752
+	down_read_nested(&ctrl->reset_lock, ctrl->depth);
675753 	if (events & DISABLE_SLOT)
676
-		pciehp_handle_disable_request(slot);
754
+		pciehp_handle_disable_request(ctrl);
677755 	else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
678
-		pciehp_handle_presence_or_link_change(slot, events);
756
+		pciehp_handle_presence_or_link_change(ctrl, events);
679757 	up_read(&ctrl->reset_lock);
680758 
681759 	ret = IRQ_HANDLED;
....@@ -764,6 +842,29 @@
764842 				   PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
765843 }
766844 
845
+void pcie_enable_interrupt(struct controller *ctrl)
846
+{
847
+	u16 mask;
848
+
849
+	mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
850
+	pcie_write_cmd(ctrl, mask, mask);
851
+}
852
+
853
+void pcie_disable_interrupt(struct controller *ctrl)
854
+{
855
+	u16 mask;
856
+
857
+	/*
858
+	 * Mask hot-plug interrupt to prevent it triggering immediately
859
+	 * when the link goes inactive (we still get PME when any of the
860
+	 * enabled events is detected). Same goes with Link Layer State
861
+	 * changed event which generates PME immediately when the link goes
862
+	 * inactive so mask it as well.
863
+	 */
864
+	mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
865
+	pcie_write_cmd(ctrl, 0, mask);
866
+}
867
+
767868 /*
768869  * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
769870  * bus reset of the bridge, but at the same time we want to ensure that it is
....@@ -772,9 +873,9 @@
772873  * momentarily, if we see that they could interfere. Also, clear any spurious
773874  * events after.
774875  */
775
-int pciehp_reset_slot(struct slot *slot, int probe)
876
+int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, int probe)
776877 {
777
-	struct controller *ctrl = slot->ctrl;
878
+	struct controller *ctrl = to_ctrl(hotplug_slot);
778879 	struct pci_dev *pdev = ctrl_dev(ctrl);
779880 	u16 stat_mask = 0, ctrl_mask = 0;
780881 	int rc;
....@@ -782,7 +883,7 @@
782883 	if (probe)
783884 		return 0;
784885 
785
-	down_write(&ctrl->reset_lock);
886
+	down_write_nested(&ctrl->reset_lock, ctrl->depth);
786887 
787888 	if (!ATTN_BUTTN(ctrl)) {
788889 		ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
....@@ -824,63 +925,48 @@
824925 	}
825926 }
826927 
827
-static int pcie_init_slot(struct controller *ctrl)
828
-{
829
-	struct pci_bus *subordinate = ctrl_dev(ctrl)->subordinate;
830
-	struct slot *slot;
831
-
832
-	slot = kzalloc(sizeof(*slot), GFP_KERNEL);
833
-	if (!slot)
834
-		return -ENOMEM;
835
-
836
-	down_read(&pci_bus_sem);
837
-	slot->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
838
-	up_read(&pci_bus_sem);
839
-
840
-	slot->ctrl = ctrl;
841
-	mutex_init(&slot->lock);
842
-	INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
843
-	ctrl->slot = slot;
844
-	return 0;
845
-}
846
-
847
-static void pcie_cleanup_slot(struct controller *ctrl)
848
-{
849
-	struct slot *slot = ctrl->slot;
850
-
851
-	cancel_delayed_work_sync(&slot->work);
852
-	kfree(slot);
853
-}
854
-
855928 static inline void dbg_ctrl(struct controller *ctrl)
856929 {
857930 	struct pci_dev *pdev = ctrl->pcie->port;
858931 	u16 reg16;
859932 
860
-	if (!pciehp_debug)
861
-		return;
862
-
863
-	ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
933
+	ctrl_dbg(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
864934 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
865
-	ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
935
+	ctrl_dbg(ctrl, "Slot Status            : 0x%04x\n", reg16);
866936 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
867
-	ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
937
+	ctrl_dbg(ctrl, "Slot Control           : 0x%04x\n", reg16);
868938 }
869939 
870940 #define FLAG(x, y)	(((x) & (y)) ? '+' : '-')
871941 
942
+static inline int pcie_hotplug_depth(struct pci_dev *dev)
943
+{
944
+	struct pci_bus *bus = dev->bus;
945
+	int depth = 0;
946
+
947
+	while (bus->parent) {
948
+		bus = bus->parent;
949
+		if (bus->self && bus->self->is_hotplug_bridge)
950
+			depth++;
951
+	}
952
+
953
+	return depth;
954
+}
955
+
872956 struct controller *pcie_init(struct pcie_device *dev)
873957 {
874958 	struct controller *ctrl;
875
-	u32 slot_cap, link_cap;
876
-	u8 occupied, poweron;
959
+	u32 slot_cap, slot_cap2, link_cap;
960
+	u8 poweron;
877961 	struct pci_dev *pdev = dev->port;
962
+	struct pci_bus *subordinate = pdev->subordinate;
878963 
879964 	ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
880965 	if (!ctrl)
881
-		goto abort;
966
+		return NULL;
882967 
883968 	ctrl->pcie = dev;
969
+	ctrl->depth = pcie_hotplug_depth(dev->port);
884970 	pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
885971 
886972 	if (pdev->hotplug_user_indicators)
....@@ -895,15 +981,29 @@
895981 
896982 	ctrl->slot_cap = slot_cap;
897983 	mutex_init(&ctrl->ctrl_lock);
984
+	mutex_init(&ctrl->state_lock);
898985 	init_rwsem(&ctrl->reset_lock);
899986 	init_waitqueue_head(&ctrl->requester);
900987 	init_waitqueue_head(&ctrl->queue);
988
+	INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work);
901989 	dbg_ctrl(ctrl);
990
+
991
+	down_read(&pci_bus_sem);
992
+	ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
993
+	up_read(&pci_bus_sem);
994
+
995
+	pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP2, &slot_cap2);
996
+	if (slot_cap2 & PCI_EXP_SLTCAP2_IBPD) {
997
+		pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_IBPD_DISABLE,
998
+				      PCI_EXP_SLTCTL_IBPD_DISABLE);
999
+		ctrl->inband_presence_disabled = 1;
1000
+	}
1001
+
1002
+	if (dmi_first_match(inband_presence_disabled_dmi_table))
1003
+		ctrl->inband_presence_disabled = 1;
9021004 
9031005 	/* Check if Data Link Layer Link Active Reporting is implemented */
9041006 	pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
905
-	if (link_cap & PCI_EXP_LNKCAP_DLLLARC)
906
-		ctrl->link_active_reporting = 1;
9071007 
9081008 	/* Clear all remaining event bits in Slot Status register. */
9091009 	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
....@@ -911,7 +1011,7 @@
9111011 		PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
9121012 		PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
9131013 
914
-	ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c%s\n",
1014
+	ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c IbPresDis%c LLActRep%c%s\n",
9151015 		(slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
9161016 		FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
9171017 		FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
....@@ -922,36 +1022,28 @@
9221022 		FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
9231023 		FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
9241024 		FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
1025
+		FLAG(slot_cap2, PCI_EXP_SLTCAP2_IBPD),
9251026 		FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC),
9261027 		pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
927
-
928
-	if (pcie_init_slot(ctrl))
929
-		goto abort_ctrl;
9301028 
9311029 	/*
9321030 	 * If empty slot's power status is on, turn power off.  The IRQ isn't
9331031 	 * requested yet, so avoid triggering a notification with this command.
9341032 	 */
9351033 	if (POWER_CTRL(ctrl)) {
936
-		pciehp_get_adapter_status(ctrl->slot, &occupied);
937
-		pciehp_get_power_status(ctrl->slot, &poweron);
938
-		if (!occupied && poweron) {
1034
+		pciehp_get_power_status(ctrl, &poweron);
1035
+		if (!pciehp_card_present_or_link_active(ctrl) && poweron) {
9391036 			pcie_disable_notification(ctrl);
940
-			pciehp_power_off_slot(ctrl->slot);
1037
+			pciehp_power_off_slot(ctrl);
9411038 		}
9421039 	}
9431040 
9441041 	return ctrl;
945
-
946
-abort_ctrl:
947
-	kfree(ctrl);
948
-abort:
949
-	return NULL;
9501042 }
9511043 
9521044 void pciehp_release_ctrl(struct controller *ctrl)
9531045 {
954
-	pcie_cleanup_slot(ctrl);
1046
+	cancel_delayed_work_sync(&ctrl->button_work);
9551047 	kfree(ctrl);
9561048 }
9571049 
....@@ -968,7 +1060,11 @@
9681060 }
9691061 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
9701062 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1063
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0110,
1064
+			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
9711065 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
9721066 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
9731067 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
9741068 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1069
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401,
1070
+			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);