add stmac read mac form eeprom

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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/pci/controller/dwc/pcie-dw-ep-rockchip.c
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@@ -10,7 +10,6 @@
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10
 
11
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 #include <linux/clk.h>
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12
 #include <linux/gpio/consumer.h>
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-#include <linux/iopoll.h>
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 #include <linux/miscdevice.h>
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 #include <linux/mfd/syscon.h>
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 #include <linux/module.h>
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@@ -82,10 +81,6 @@
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81
 #define PCIE_CLIENT_HOT_RESET_CTRL      0x180
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 #define PCIE_CLIENT_LTSSM_STATUS	0x300
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 #define PCIE_CLIENT_INTR_MASK		0x24
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-#define PCIE_LTSSM_APP_DLY1_EN		BIT(0)
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-#define PCIE_LTSSM_APP_DLY2_EN		BIT(1)
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-#define PCIE_LTSSM_APP_DLY1_DONE	BIT(2)
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-#define PCIE_LTSSM_APP_DLY2_DONE	BIT(3)
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 #define PCIE_LTSSM_ENABLE_ENHANCE       BIT(4)
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 #define PCIE_CLIENT_MSI_GEN_CON		0x38
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86
 
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@@ -111,7 +106,6 @@
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106
 #define PCIE_EP_OBJ_INFO_DRV_VERSION	0x00000001
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107
 
113
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 #define PCIE_BAR_MAX_NUM		6
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-#define PCIE_HOTRESET_TMOUT_US		10000
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109
 
116
110
 struct rockchip_pcie {
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111
 	struct dw_pcie			pci;
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@@ -136,8 +130,6 @@
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 	phys_addr_t			dbi_base_physical;
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 	struct pcie_ep_obj_info		*obj_info;
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 	enum pcie_ep_mmap_resource	cur_mmap_res;
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-	struct workqueue_struct		*hot_rst_wq;
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-	struct work_struct		hot_rst_work;
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133
 };
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134
 
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 struct rockchip_pcie_misc_dev {
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@@ -207,7 +199,6 @@
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 	struct device_node *np = dev->of_node;
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 	void *addr;
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 	struct resource *dbi_base;
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-	struct resource *apb_base;
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 	struct device_node *mem;
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 	struct resource reg;
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 	char name[8];
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@@ -223,17 +214,14 @@
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 	rockchip->pci.dbi_base = devm_ioremap_resource(dev, dbi_base);
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215
 	if (IS_ERR(rockchip->pci.dbi_base))
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 		return PTR_ERR(rockchip->pci.dbi_base);
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+	rockchip->pci.atu_base = rockchip->pci.dbi_base + DEFAULT_DBI_ATU_OFFSET;
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218
 	rockchip->dbi_base_physical = dbi_base->start;
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219
 
228
-	apb_base = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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-						"pcie-apb");
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-	if (!apb_base) {
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+	rockchip->apb_base = devm_platform_ioremap_resource_byname(pdev, "pcie-apb");
221
+	if (!rockchip->apb_base) {
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 		dev_err(dev, "get pcie-apb failed\n");
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223
 		return -ENODEV;
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224
 	}
234
-	rockchip->apb_base = devm_ioremap_resource(dev, apb_base);
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-	if (IS_ERR(rockchip->apb_base))
236
-		return PTR_ERR(rockchip->apb_base);
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225
 
238
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 	rockchip->rst_gpio = devm_gpiod_get_optional(dev, "reset",
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227
 						     GPIOD_OUT_HIGH);
..
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@@ -580,7 +568,7 @@
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568
 
581
569
 	as_type = DW_PCIE_AS_MEM;
582
570
 
583
-	ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr, as_type);
571
+	ret = dw_pcie_prog_inbound_atu(pci, 0, free_win, bar, cpu_addr, as_type);
584
572
 	if (ret < 0) {
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573
 		dev_err(pci->dev, "Failed to program IB window\n");
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574
 		return ret;
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@@ -598,8 +586,7 @@
598
586
 
599
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 	/* LTSSM EN ctrl mode */
600
588
 	val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_HOT_RESET_CTRL);
601
-	val |= (PCIE_LTSSM_ENABLE_ENHANCE | PCIE_LTSSM_APP_DLY2_EN) |
602
-		((PCIE_LTSSM_ENABLE_ENHANCE | PCIE_LTSSM_APP_DLY2_EN) << 16);
589
+	val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16);
603
590
 	rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
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591
 }
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592
 
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@@ -655,7 +642,7 @@
655
642
 	u32 chn;
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643
 	union int_status wr_status, rd_status;
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644
 	union int_clear clears;
658
-	u32 reg, mask;
645
+	u32 reg, val, mask;
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646
 	bool sigio = false;
660
647
 
661
648
 	/* ELBI helper, only check the valid bits, and discard the rest interrupts */
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@@ -726,8 +713,14 @@
726
713
 	}
727
714
 
728
715
 	reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
729
-	if (reg & BIT(2))
730
-		queue_work(rockchip->hot_rst_wq, &rockchip->hot_rst_work);
716
+	if (reg & BIT(2)) {
717
+		/* Setup command register */
718
+		val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
719
+		val &= 0xffff0000;
720
+		val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
721
+		       PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
722
+		dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
723
+	}
731
724
 
732
725
 	rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
733
726
 
..
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@@ -875,23 +868,6 @@
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 	table->weilo.weight0 = 0x0;
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869
 	table->start.stop = 0x0;
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 	table->start.chnl = table->chn;
878
-}
879
-
880
-static void rockchip_pcie_hot_rst_work(struct work_struct *work)
881
-{
882
-	struct rockchip_pcie *rockchip = container_of(work, struct rockchip_pcie, hot_rst_work);
883
-	u32 status;
884
-	int ret;
885
-
886
-	if (rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_HOT_RESET_CTRL) & PCIE_LTSSM_APP_DLY2_EN) {
887
-		ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_LTSSM_STATUS,
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-			 status, ((status & 0x3F) == 0), 100, PCIE_HOTRESET_TMOUT_US);
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-		if (ret)
890
-			dev_err(rockchip->pci.dev, "wait for detect quiet failed!\n");
891
-
892
-		rockchip_pcie_writel_apb(rockchip, (PCIE_LTSSM_APP_DLY2_DONE) | ((PCIE_LTSSM_APP_DLY2_DONE) << 16),
893
-					PCIE_CLIENT_HOT_RESET_CTRL);
894
-	}
895
871
 }
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872
 
897
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 static int rockchip_pcie_get_dma_status(struct dma_trx_obj *obj, u8 chn, enum dma_dir dir)
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@@ -1145,7 +1121,6 @@
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 	struct rockchip_pcie *rockchip;
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1122
 	int ret;
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1123
 	int retry, i;
1148
-	u32 reg;
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1124
 
1150
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 	rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
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 	if (!rockchip)
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@@ -1206,26 +1181,6 @@
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1207
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 	rockchip_pcie_start_link(&rockchip->pci);
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 	rockchip_pcie_devmode_update(rockchip, RKEP_MODE_KERNEL, RKEP_SMODE_LNKRDY);
1209
-
1210
-	rockchip->hot_rst_wq = create_singlethread_workqueue("rkep_hot_rst_wq");
1211
-	if (!rockchip->hot_rst_wq) {
1212
-		dev_err(dev, "failed to create hot_rst workqueue\n");
1213
-		ret = -ENOMEM;
1214
-		goto deinit_phy;
1215
-	}
1216
-	INIT_WORK(&rockchip->hot_rst_work, rockchip_pcie_hot_rst_work);
1217
-
1218
-	reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
1219
-	if ((reg & BIT(2)) &&
1220
-	    (rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_HOT_RESET_CTRL) & PCIE_LTSSM_APP_DLY2_EN)) {
1221
-		rockchip_pcie_writel_apb(rockchip, PCIE_LTSSM_APP_DLY2_DONE | (PCIE_LTSSM_APP_DLY2_DONE << 16),
1222
-					 PCIE_CLIENT_HOT_RESET_CTRL);
1223
-		dev_info(dev, "hot reset ever\n");
1224
-	}
1225
-	rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
1226
-
1227
-	/* Enable client reset or link down interrupt */
1228
-	rockchip_pcie_writel_apb(rockchip, 0x40000, PCIE_CLIENT_INTR_MASK);
1229
1184
 
1230
1185
 	for (retry = 0; retry < 10000; retry++) {
1231
1186
 		if (dw_pcie_link_up(&rockchip->pci)) {