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| 1 | | -/* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | 1 | /* |
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| 3 | 2 | * Structure used by apps whose drivers access SDIO drivers. |
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| 4 | 3 | * Pulled out separately so dhdu and wlu can both use it. |
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| 5 | 4 | * |
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| 6 | | - * Copyright (C) 1999-2019, Broadcom Corporation |
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| 7 | | - * |
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| 5 | + * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation |
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| 6 | + * |
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| 7 | + * Copyright (C) 1999-2017, Broadcom Corporation |
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| 8 | + * |
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| 8 | 9 | * Unless you and Broadcom execute a separate written software license |
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| 9 | 10 | * agreement governing use of this software, this software is licensed to you |
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| 10 | 11 | * under the terms of the GNU General Public License version 2 (the "GPL"), |
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| 11 | 12 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the |
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| 12 | 13 | * following added to such license: |
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| 13 | | - * |
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| 14 | + * |
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| 14 | 15 | * As a special exception, the copyright holders of this software give you |
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| 15 | 16 | * permission to link this software with independent modules, and to copy and |
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| 16 | 17 | * distribute the resulting executable under terms of your choice, provided that |
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| .. | .. |
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| 18 | 19 | * the license of that module. An independent module is a module which is not |
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| 19 | 20 | * derived from this software. The special exception does not apply to any |
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| 20 | 21 | * modifications of the software. |
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| 21 | | - * |
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| 22 | + * |
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| 22 | 23 | * Notwithstanding the above, under no circumstances may you combine this |
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| 23 | 24 | * software in any way with any other Broadcom software provided under a license |
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| 24 | 25 | * other than the GPL, without Broadcom's express prior written consent. |
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| .. | .. |
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| 26 | 27 | * |
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| 27 | 28 | * <<Broadcom-WL-IPTag/Open:>> |
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| 28 | 29 | * |
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| 29 | | - * $Id: sdiovar.h 514727 2014-11-12 03:02:48Z $ |
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| 30 | + * $Id: sdiovar.h 660496 2016-09-20 19:28:50Z $ |
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| 30 | 31 | */ |
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| 31 | 32 | |
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| 32 | 33 | #ifndef _sdiovar_h_ |
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| 33 | 34 | #define _sdiovar_h_ |
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| 34 | 35 | |
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| 35 | 36 | #include <typedefs.h> |
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| 36 | | - |
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| 37 | | -/* require default structure packing */ |
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| 38 | | -#define BWL_DEFAULT_PACKING |
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| 39 | | -#include <packed_section_start.h> |
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| 40 | 37 | |
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| 41 | 38 | typedef struct sdreg { |
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| 42 | 39 | int func; |
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| .. | .. |
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| 56 | 53 | |
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| 57 | 54 | #define NUM_PREV_TRANSACTIONS 16 |
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| 58 | 55 | |
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| 56 | +#ifdef BCMSPI |
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| 57 | +/* Error statistics for gSPI */ |
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| 58 | +struct spierrstats_t { |
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| 59 | + uint32 dna; /* The requested data is not available. */ |
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| 60 | + uint32 rdunderflow; /* FIFO underflow happened due to current (F2, F3) rd command */ |
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| 61 | + uint32 wroverflow; /* FIFO underflow happened due to current (F1, F2, F3) wr command */ |
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| 59 | 62 | |
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| 60 | | -#include <packed_section_end.h> |
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| 63 | + uint32 f2interrupt; /* OR of all F2 related intr status bits. */ |
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| 64 | + uint32 f3interrupt; /* OR of all F3 related intr status bits. */ |
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| 65 | + |
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| 66 | + uint32 f2rxnotready; /* F2 FIFO is not ready to receive data (FIFO empty) */ |
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| 67 | + uint32 f3rxnotready; /* F3 FIFO is not ready to receive data (FIFO empty) */ |
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| 68 | + |
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| 69 | + uint32 hostcmddataerr; /* Error in command or host data, detected by CRC/checksum |
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| 70 | + * (optional) |
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| 71 | + */ |
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| 72 | + uint32 f2pktavailable; /* Packet is available in F2 TX FIFO */ |
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| 73 | + uint32 f3pktavailable; /* Packet is available in F2 TX FIFO */ |
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| 74 | + |
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| 75 | + uint32 dstatus[NUM_PREV_TRANSACTIONS]; /* dstatus bits of last 16 gSPI transactions */ |
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| 76 | + uint32 spicmd[NUM_PREV_TRANSACTIONS]; |
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| 77 | +}; |
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| 78 | +#endif /* BCMSPI */ |
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| 79 | + |
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| 80 | +typedef struct sdio_bus_metrics { |
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| 81 | + uint32 active_dur; /* msecs */ |
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| 82 | + |
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| 83 | + /* Generic */ |
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| 84 | + uint32 data_intr_cnt; /* data interrupt counter */ |
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| 85 | + uint32 mb_intr_cnt; /* mailbox interrupt counter */ |
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| 86 | + uint32 error_intr_cnt; /* error interrupt counter */ |
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| 87 | + uint32 wakehost_cnt; /* counter for OOB wakehost */ |
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| 88 | + |
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| 89 | + /* DS forcewake */ |
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| 90 | + uint32 ds_wake_on_cnt; /* counter for (clock) ON */ |
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| 91 | + uint32 ds_wake_on_dur; /* duration for (clock) ON) */ |
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| 92 | + uint32 ds_wake_off_cnt; /* counter for (clock) OFF */ |
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| 93 | + uint32 ds_wake_off_dur; /* duration for (clock) OFF */ |
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| 94 | + |
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| 95 | + /* DS_D0 state */ |
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| 96 | + uint32 ds_d0_cnt; /* counter for DS_D0 state */ |
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| 97 | + uint32 ds_d0_dur; /* duration for DS_D0 state */ |
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| 98 | + |
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| 99 | + /* DS_D3 state */ |
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| 100 | + uint32 ds_d3_cnt; /* counter for DS_D3 state */ |
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| 101 | + uint32 ds_d3_dur; /* duration for DS_D3 state */ |
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| 102 | + |
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| 103 | + /* DS DEV_WAKE */ |
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| 104 | + uint32 ds_dw_assrt_cnt; /* counter for DW_ASSERT */ |
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| 105 | + uint32 ds_dw_dassrt_cnt; /* counter for DW_DASSERT */ |
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| 106 | + |
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| 107 | + /* DS mailbox signals */ |
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| 108 | + uint32 ds_tx_dsreq_cnt; /* counter for tx HMB_DATA_DSREQ */ |
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| 109 | + uint32 ds_tx_dsexit_cnt; /* counter for tx HMB_DATA_DSEXIT */ |
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| 110 | + uint32 ds_tx_d3ack_cnt; /* counter for tx HMB_DATA_D3ACK */ |
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| 111 | + uint32 ds_tx_d3exit_cnt; /* counter for tx HMB_DATA_D3EXIT */ |
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| 112 | + uint32 ds_rx_dsack_cnt; /* counter for rx SMB_DATA_DSACK */ |
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| 113 | + uint32 ds_rx_dsnack_cnt; /* counter for rx SMB_DATA_DSNACK */ |
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| 114 | + uint32 ds_rx_d3inform_cnt; /* counter for rx SMB_DATA_D3INFORM */ |
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| 115 | +} sdio_bus_metrics_t; |
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| 116 | + |
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| 117 | +/* Bus interface info for SDIO */ |
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| 118 | +typedef struct wl_pwr_sdio_stats { |
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| 119 | + uint16 type; /* WL_PWRSTATS_TYPE_SDIO */ |
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| 120 | + uint16 len; /* Up to 4K-1, top 4 bits are reserved */ |
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| 121 | + |
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| 122 | + sdio_bus_metrics_t sdio; /* stats from SDIO bus driver */ |
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| 123 | +} wl_pwr_sdio_stats_t; |
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| 61 | 124 | |
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| 62 | 125 | #endif /* _sdiovar_h_ */ |
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