add stmac read mac form eeprom

hc

2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192se/rf.c
..
..
@@ -1,27 +1,5 @@
1
-/******************************************************************************
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- *
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- * Copyright(c) 2009-2012  Realtek Corporation.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of version 2 of the GNU General Public License as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * The full GNU General Public License is included in this distribution in the
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- * file called LICENSE.
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- *
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- * Contact Information:
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- * wlanfae <wlanfae@realtek.com>
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- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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- * Hsinchu 300, Taiwan.
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- *
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- * Larry Finger <Larry.Finger@lwfinger.net>
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- *
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- *****************************************************************************/
1
+// SPDX-License-Identifier: GPL-2.0
2
+/* Copyright(c) 2009-2012  Realtek Corporation.*/
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3
 
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4
 #include "../wifi.h"
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5
 #include "reg.h"
..
..
@@ -47,7 +25,7 @@
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25
 
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 	/* We only care about the path A for legacy. */
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27
 	if (rtlefuse->eeprom_version < 2) {
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-		pwrbase0 = pwrlevel[0] + (rtlefuse->legacy_httxpowerdiff & 0xf);
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+		pwrbase0 = pwrlevel[0] + (rtlefuse->legacy_ht_txpowerdiff & 0xf);
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29
 	} else {
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 		legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff
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31
 						[RF90_PATH_A][chnl - 1];
..
..
@@ -117,13 +95,13 @@
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95
 	}
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96
 
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 	if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
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-		RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
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-			 "40MHz finalpwr_idx (A / B) = 0x%x / 0x%x\n",
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-			 p_final_pwridx[0], p_final_pwridx[1]);
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+		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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+			"40MHz finalpwr_idx (A / B) = 0x%x / 0x%x\n",
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+			p_final_pwridx[0], p_final_pwridx[1]);
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101
 	} else {
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-		RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
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-			 "20MHz finalpwr_idx (A / B) = 0x%x / 0x%x\n",
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-			 p_final_pwridx[0], p_final_pwridx[1]);
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+		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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+			"20MHz finalpwr_idx (A / B) = 0x%x / 0x%x\n",
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+			p_final_pwridx[0], p_final_pwridx[1]);
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105
 	}
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106
 }
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107
 
..
..
@@ -146,9 +124,9 @@
146
124
 		if (ant_pwr_diff < -8)
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125
 			ant_pwr_diff = -8;
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126
 
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-		RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
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-			 "Antenna Diff from RF-B to RF-A = %d (0x%x)\n",
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-			 ant_pwr_diff, ant_pwr_diff & 0xf);
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+		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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+			"Antenna Diff from RF-B to RF-A = %d (0x%x)\n",
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+			ant_pwr_diff, ant_pwr_diff & 0xf);
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130
 
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 		ant_pwr_diff &= 0xf;
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132
 	}
..
..
@@ -165,8 +143,8 @@
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143
 	rtl_set_bbreg(hw, RFPGA0_TXGAINSTAGE, (BXBTXAGC | BXCTXAGC | BXDTXAGC),
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144
 		      u4reg_val);
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145
 
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-	RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Write BCD-Diff(0x%x) = 0x%x\n",
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-		 RFPGA0_TXGAINSTAGE, u4reg_val);
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+	rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Write BCD-Diff(0x%x) = 0x%x\n",
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+		RFPGA0_TXGAINSTAGE, u4reg_val);
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148
 }
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149
 
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150
 static void _rtl92s_get_txpower_writeval_byregulatory(struct ieee80211_hw *hw,
..
..
@@ -191,8 +169,8 @@
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169
 		writeval = rtlphy->mcs_offset[chnlgroup][index] +
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170
 				((index < 2) ? pwrbase0 : pwrbase1);
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171
 
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-		RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
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-			 "RTK better performance, writeval = 0x%x\n", writeval);
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+		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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+			"RTK better performance, writeval = 0x%x\n", writeval);
196
174
 		break;
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175
 	case 1:
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176
 		/* Realtek regulatory increase power diff defined
..
..
@@ -200,9 +178,9 @@
200
178
 		if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
201
179
 			writeval = ((index < 2) ? pwrbase0 : pwrbase1);
202
180
 
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-			RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
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-				 "Realtek regulatory, 40MHz, writeval = 0x%x\n",
205
-				 writeval);
181
+			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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+				"Realtek regulatory, 40MHz, writeval = 0x%x\n",
183
+				writeval);
206
184
 		} else {
207
185
 			chnlgroup = 0;
208
186
 
..
..
@@ -221,16 +199,16 @@
221
199
 					+ ((index < 2) ?
222
200
 					pwrbase0 : pwrbase1);
223
201
 
224
-			RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
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-				 "Realtek regulatory, 20MHz, writeval = 0x%x\n",
226
-				 writeval);
202
+			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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+				"Realtek regulatory, 20MHz, writeval = 0x%x\n",
204
+				writeval);
227
205
 		}
228
206
 		break;
229
207
 	case 2:
230
208
 		/* Better regulatory don't increase any power diff */
231
209
 		writeval = ((index < 2) ? pwrbase0 : pwrbase1);
232
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
233
-			 "Better regulatory, writeval = 0x%x\n", writeval);
210
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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+			"Better regulatory, writeval = 0x%x\n", writeval);
234
212
 		break;
235
213
 	case 3:
236
214
 		/* Customer defined power diff. increase power diff
..
..
@@ -238,15 +216,15 @@
238
216
 		chnlgroup = 0;
239
217
 
240
218
 		if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
241
-			RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
242
-				 "customer's limit, 40MHz = 0x%x\n",
243
-				 rtlefuse->pwrgroup_ht40
244
-				 [RF90_PATH_A][chnl - 1]);
219
+			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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+				"customer's limit, 40MHz = 0x%x\n",
221
+				rtlefuse->pwrgroup_ht40
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+				[RF90_PATH_A][chnl - 1]);
245
223
 		} else {
246
-			RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
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-				 "customer's limit, 20MHz = 0x%x\n",
248
-				 rtlefuse->pwrgroup_ht20
249
-				 [RF90_PATH_A][chnl - 1]);
224
+			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
225
+				"customer's limit, 20MHz = 0x%x\n",
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+				rtlefuse->pwrgroup_ht20
227
+				[RF90_PATH_A][chnl - 1]);
250
228
 		}
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229
 
252
230
 		for (i = 0; i < 4; i++) {
..
..
@@ -278,20 +256,20 @@
278
256
 				(pwrdiff_limit[2] << 16) |
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257
 				(pwrdiff_limit[1] << 8) |
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258
 				(pwrdiff_limit[0]);
281
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
282
-			 "Customer's limit = 0x%x\n", customer_limit);
259
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
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+			"Customer's limit = 0x%x\n", customer_limit);
283
261
 
284
262
 		writeval = customer_limit + ((index < 2) ?
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263
 					     pwrbase0 : pwrbase1);
286
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
287
-			 "Customer, writeval = 0x%x\n", writeval);
264
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
265
+			"Customer, writeval = 0x%x\n", writeval);
288
266
 		break;
289
267
 	default:
290
268
 		chnlgroup = 0;
291
269
 		writeval = rtlphy->mcs_offset[chnlgroup][index] +
292
270
 				((index < 2) ? pwrbase0 : pwrbase1);
293
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
294
-			 "RTK better performance, writeval = 0x%x\n", writeval);
271
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
272
+			"RTK better performance, writeval = 0x%x\n", writeval);
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273
 		break;
296
274
 	}
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275