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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h
....@@ -1,27 +1,6 @@
1
-/******************************************************************************
2
- *
3
- * Copyright(c) 2009-2012  Realtek Corporation.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of version 2 of the GNU General Public License as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
14
- * The full GNU General Public License is included in this distribution in the
15
- * file called LICENSE.
16
- *
17
- * Contact Information:
18
- * wlanfae <wlanfae@realtek.com>
19
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20
- * Hsinchu 300, Taiwan.
21
- *
22
- * Larry Finger <Larry.Finger@lwfinger.net>
23
- *
24
- *****************************************************************************/
1
+/* SPDX-License-Identifier: GPL-2.0 */
2
+/* Copyright(c) 2009-2012  Realtek Corporation.*/
3
+
254 #ifndef __REALTEK_92S_DEF_H__
265 #define __REALTEK_92S_DEF_H__
276 
....@@ -45,192 +24,186 @@
4524 #define TX_DESC_SIZE_RTL8192S			(16 * 4)
4625 #define TX_CMDDESC_SIZE_RTL8192S		(16 * 4)
4726 
48
-/* Define a macro that takes a le32 word, converts it to host ordering,
49
- * right shifts by a specified count, creates a mask of the specified
50
- * bit count, and extracts that number of bits.
51
- */
52
-
53
-#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask)		\
54
-	((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) &	\
55
-	BIT_LEN_MASK_32(__mask))
56
-
57
-/* Define a macro that clears a bit field in an le32 word and
58
- * sets the specified value into that bit field. The resulting
59
- * value remains in le32 ordering; however, it is properly converted
60
- * to host ordering for the clear and set operations before conversion
61
- * back to le32.
62
- */
63
-
64
-#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val)	\
65
-	(*(__le32 *)(__pdesc) =					\
66
-	(cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) &	\
67
-	(~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) |	\
68
-	(((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
69
-
7027 /* macros to read/write various fields in RX or TX descriptors */
7128 
7229 /* Dword 0 */
73
-#define SET_TX_DESC_PKT_SIZE(__pdesc, __val)			\
74
-	SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
75
-#define SET_TX_DESC_OFFSET(__pdesc, __val)			\
76
-	SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
77
-#define SET_TX_DESC_TYPE(__pdesc, __val)			\
78
-	SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val)
79
-#define SET_TX_DESC_LAST_SEG(__pdesc, __val)			\
80
-	SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
81
-#define SET_TX_DESC_FIRST_SEG(__pdesc, __val)			\
82
-	SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
83
-#define SET_TX_DESC_LINIP(__pdesc, __val)			\
84
-	SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
85
-#define SET_TX_DESC_AMSDU(__pdesc, __val)			\
86
-	SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
87
-#define SET_TX_DESC_GREEN_FIELD(__pdesc, __val)			\
88
-	SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
89
-#define SET_TX_DESC_OWN(__pdesc, __val)				\
90
-	SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
30
+static inline void set_tx_desc_pkt_size(__le32 *__pdesc, u32 __val)
31
+{
32
+	le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));
33
+}
9134 
92
-#define GET_TX_DESC_OWN(__pdesc)				\
93
-	SHIFT_AND_MASK_LE(__pdesc, 31, 1)
35
+static inline void set_tx_desc_offset(__le32 *__pdesc, u32 __val)
36
+{
37
+	le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));
38
+}
39
+
40
+static inline void set_tx_desc_last_seg(__le32 *__pdesc, u32 __val)
41
+{
42
+	le32p_replace_bits(__pdesc, __val, BIT(26));
43
+}
44
+
45
+static inline void set_tx_desc_first_seg(__le32 *__pdesc, u32 __val)
46
+{
47
+	le32p_replace_bits(__pdesc, __val, BIT(27));
48
+}
49
+
50
+static inline void set_tx_desc_linip(__le32 *__pdesc, u32 __val)
51
+{
52
+	le32p_replace_bits(__pdesc, __val, BIT(28));
53
+}
54
+
55
+static inline void set_tx_desc_own(__le32 *__pdesc, u32 __val)
56
+{
57
+	le32p_replace_bits(__pdesc, __val, BIT(31));
58
+}
59
+
60
+static inline u32 get_tx_desc_own(__le32 *__pdesc)
61
+{
62
+	return le32_get_bits(*(__pdesc), BIT(31));
63
+}
9464 
9565 /* Dword 1 */
96
-#define SET_TX_DESC_MACID(__pdesc, __val)			\
97
-	SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val)
98
-#define SET_TX_DESC_MORE_DATA(__pdesc, __val)			\
99
-	SET_BITS_OFFSET_LE(__pdesc + 4, 5, 1, __val)
100
-#define SET_TX_DESC_MORE_FRAG(__pdesc, __val)			\
101
-	SET_BITS_OFFSET_LE(__pdesc + 4, 6, 1, __val)
102
-#define SET_TX_DESC_PIFS(__pdesc, __val)			\
103
-	SET_BITS_OFFSET_LE(__pdesc + 4, 7, 1, __val)
104
-#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val)			\
105
-	SET_BITS_OFFSET_LE(__pdesc + 4, 8, 5, __val)
106
-#define SET_TX_DESC_ACK_POLICY(__pdesc, __val)			\
107
-	SET_BITS_OFFSET_LE(__pdesc + 4, 13, 2, __val)
108
-#define SET_TX_DESC_NO_ACM(__pdesc, __val)			\
109
-	SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val)
110
-#define SET_TX_DESC_NON_QOS(__pdesc, __val)			\
111
-	SET_BITS_OFFSET_LE(__pdesc + 4, 16, 1, __val)
112
-#define SET_TX_DESC_KEY_ID(__pdesc, __val)			\
113
-	SET_BITS_OFFSET_LE(__pdesc + 4, 17, 2, __val)
114
-#define SET_TX_DESC_OUI(__pdesc, __val)				\
115
-	SET_BITS_OFFSET_LE(__pdesc + 4, 19, 1, __val)
116
-#define SET_TX_DESC_PKT_TYPE(__pdesc, __val)			\
117
-	SET_BITS_OFFSET_LE(__pdesc + 4, 20, 1, __val)
118
-#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val)			\
119
-	SET_BITS_OFFSET_LE(__pdesc + 4, 21, 1, __val)
120
-#define SET_TX_DESC_SEC_TYPE(__pdesc, __val)			\
121
-	SET_BITS_OFFSET_LE(__pdesc + 4, 22, 2, __val)
122
-#define SET_TX_DESC_WDS(__pdesc, __val)				\
123
-	SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val)
124
-#define SET_TX_DESC_HTC(__pdesc, __val)				\
125
-	SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val)
126
-#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val)			\
127
-	SET_BITS_OFFSET_LE(__pdesc + 4, 26, 5, __val)
128
-#define SET_TX_DESC_HWPC(__pdesc, __val)			\
129
-	SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val)
66
+static inline void set_tx_desc_macid(__le32 *__pdesc, u32 __val)
67
+{
68
+	le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0));
69
+}
70
+
71
+static inline void set_tx_desc_queue_sel(__le32 *__pdesc, u32 __val)
72
+{
73
+	le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));
74
+}
75
+
76
+static inline void set_tx_desc_non_qos(__le32 *__pdesc, u32 __val)
77
+{
78
+	le32p_replace_bits((__pdesc + 1), __val, BIT(16));
79
+}
80
+
81
+static inline void set_tx_desc_sec_type(__le32 *__pdesc, u32 __val)
82
+{
83
+	le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));
84
+}
13085 
13186 /* Dword 2 */
132
-#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val)		\
133
-	SET_BITS_OFFSET_LE(__pdesc + 8, 0, 6, __val)
134
-#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val)		\
135
-	SET_BITS_OFFSET_LE(__pdesc + 8, 6, 1, __val)
136
-#define SET_TX_DESC_TSFL(__pdesc, __val)			\
137
-	SET_BITS_OFFSET_LE(__pdesc + 8, 7, 5, __val)
138
-#define SET_TX_DESC_RTS_RETRY_COUNT(__pdesc, __val)		\
139
-	SET_BITS_OFFSET_LE(__pdesc + 8, 12, 6, __val)
140
-#define SET_TX_DESC_DATA_RETRY_COUNT(__pdesc, __val)		\
141
-	SET_BITS_OFFSET_LE(__pdesc + 8, 18, 6, __val)
142
-#define	SET_TX_DESC_RSVD_MACID(__pdesc, __val)			\
143
-	SET_BITS_OFFSET_LE(((__pdesc) + 8), 24, 5, __val)
144
-#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val)			\
145
-	SET_BITS_OFFSET_LE(__pdesc + 8, 29, 1, __val)
146
-#define SET_TX_DESC_AGG_BREAK(__pdesc, __val)			\
147
-	SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val)
148
-#define SET_TX_DESC_OWN_MAC(__pdesc, __val)			\
149
-	SET_BITS_OFFSET_LE(__pdesc + 8, 31, 1, __val)
87
+static inline void	set_tx_desc_rsvd_macid(__le32 *__pdesc, u32 __val)
88
+{
89
+	le32p_replace_bits((__pdesc + 2), __val, GENMASK(28, 24));
90
+}
91
+
92
+static inline void set_tx_desc_agg_enable(__le32 *__pdesc, u32 __val)
93
+{
94
+	le32p_replace_bits((__pdesc + 2), __val, BIT(29));
95
+}
15096 
15197 /* Dword 3 */
152
-#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val)		\
153
-	SET_BITS_OFFSET_LE(__pdesc + 12, 0, 8, __val)
154
-#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val)			\
155
-	SET_BITS_OFFSET_LE(__pdesc + 12, 8, 8, __val)
156
-#define SET_TX_DESC_SEQ(__pdesc, __val)				\
157
-	SET_BITS_OFFSET_LE(__pdesc + 12, 16, 12, __val)
158
-#define SET_TX_DESC_FRAG(__pdesc, __val)			\
159
-	SET_BITS_OFFSET_LE(__pdesc + 12, 28, 4, __val)
98
+static inline void set_tx_desc_seq(__le32 *__pdesc, u32 __val)
99
+{
100
+	le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16));
101
+}
160102 
161103 /* Dword 4 */
162
-#define SET_TX_DESC_RTS_RATE(__pdesc, __val)			\
163
-	SET_BITS_OFFSET_LE(__pdesc + 16, 0, 6, __val)
164
-#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val)		\
165
-	SET_BITS_OFFSET_LE(__pdesc + 16, 6, 1, __val)
166
-#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val)		\
167
-	SET_BITS_OFFSET_LE(__pdesc + 16, 7, 4, __val)
168
-#define SET_TX_DESC_CTS_ENABLE(__pdesc, __val)			\
169
-	SET_BITS_OFFSET_LE(__pdesc + 16, 11, 1, __val)
170
-#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val)			\
171
-	SET_BITS_OFFSET_LE(__pdesc + 16, 12, 1, __val)
172
-#define SET_TX_DESC_RA_BRSR_ID(__pdesc, __val)			\
173
-	SET_BITS_OFFSET_LE(__pdesc + 16, 13, 3, __val)
174
-#define SET_TX_DESC_TXHT(__pdesc, __val)			\
175
-	SET_BITS_OFFSET_LE(__pdesc + 16, 16, 1, __val)
176
-#define SET_TX_DESC_TX_SHORT(__pdesc, __val)			\
177
-	SET_BITS_OFFSET_LE(__pdesc + 16, 17, 1, __val)
178
-#define SET_TX_DESC_TX_BANDWIDTH(__pdesc, __val)		\
179
-	SET_BITS_OFFSET_LE(__pdesc + 16, 18, 1, __val)
180
-#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val)		\
181
-	SET_BITS_OFFSET_LE(__pdesc + 16, 19, 2, __val)
182
-#define SET_TX_DESC_TX_STBC(__pdesc, __val)			\
183
-	SET_BITS_OFFSET_LE(__pdesc + 16, 21, 2, __val)
184
-#define SET_TX_DESC_TX_REVERSE_DIRECTION(__pdesc, __val)	\
185
-	SET_BITS_OFFSET_LE(__pdesc + 16, 23, 1, __val)
186
-#define SET_TX_DESC_RTS_HT(__pdesc, __val)			\
187
-	SET_BITS_OFFSET_LE(__pdesc + 16, 24, 1, __val)
188
-#define SET_TX_DESC_RTS_SHORT(__pdesc, __val)			\
189
-	SET_BITS_OFFSET_LE(__pdesc + 16, 25, 1, __val)
190
-#define SET_TX_DESC_RTS_BANDWIDTH(__pdesc, __val)		\
191
-	SET_BITS_OFFSET_LE(__pdesc + 16, 26, 1, __val)
192
-#define SET_TX_DESC_RTS_SUB_CARRIER(__pdesc, __val)		\
193
-	SET_BITS_OFFSET_LE(__pdesc + 16, 27, 2, __val)
194
-#define SET_TX_DESC_RTS_STBC(__pdesc, __val)			\
195
-	SET_BITS_OFFSET_LE(__pdesc + 16, 29, 2, __val)
196
-#define SET_TX_DESC_USER_RATE(__pdesc, __val)			\
197
-	SET_BITS_OFFSET_LE(__pdesc + 16, 31, 1, __val)
104
+static inline void set_tx_desc_rts_rate(__le32 *__pdesc, u32 __val)
105
+{
106
+	le32p_replace_bits((__pdesc + 4), __val, GENMASK(5, 0));
107
+}
108
+
109
+static inline void set_tx_desc_cts_enable(__le32 *__pdesc, u32 __val)
110
+{
111
+	le32p_replace_bits((__pdesc + 4), __val, BIT(11));
112
+}
113
+
114
+static inline void set_tx_desc_rts_enable(__le32 *__pdesc, u32 __val)
115
+{
116
+	le32p_replace_bits((__pdesc + 4), __val, BIT(12));
117
+}
118
+
119
+static inline void set_tx_desc_ra_brsr_id(__le32 *__pdesc, u32 __val)
120
+{
121
+	le32p_replace_bits((__pdesc + 4), __val, GENMASK(15, 13));
122
+}
123
+
124
+static inline void set_tx_desc_txht(__le32 *__pdesc, u32 __val)
125
+{
126
+	le32p_replace_bits((__pdesc + 4), __val, BIT(16));
127
+}
128
+
129
+static inline void set_tx_desc_tx_short(__le32 *__pdesc, u32 __val)
130
+{
131
+	le32p_replace_bits((__pdesc + 4), __val, BIT(17));
132
+}
133
+
134
+static inline void set_tx_desc_tx_bandwidth(__le32 *__pdesc, u32 __val)
135
+{
136
+	le32p_replace_bits((__pdesc + 4), __val, BIT(18));
137
+}
138
+
139
+static inline void set_tx_desc_tx_sub_carrier(__le32 *__pdesc, u32 __val)
140
+{
141
+	le32p_replace_bits((__pdesc + 4), __val, GENMASK(20, 19));
142
+}
143
+
144
+static inline void set_tx_desc_rts_short(__le32 *__pdesc, u32 __val)
145
+{
146
+	le32p_replace_bits((__pdesc + 4), __val, BIT(25));
147
+}
148
+
149
+static inline void set_tx_desc_rts_bandwidth(__le32 *__pdesc, u32 __val)
150
+{
151
+	le32p_replace_bits((__pdesc + 4), __val, BIT(26));
152
+}
153
+
154
+static inline void set_tx_desc_rts_sub_carrier(__le32 *__pdesc, u32 __val)
155
+{
156
+	le32p_replace_bits((__pdesc + 4), __val, GENMASK(28, 27));
157
+}
158
+
159
+static inline void set_tx_desc_rts_stbc(__le32 *__pdesc, u32 __val)
160
+{
161
+	le32p_replace_bits((__pdesc + 4), __val, GENMASK(30, 29));
162
+}
163
+
164
+static inline void set_tx_desc_user_rate(__le32 *__pdesc, u32 __val)
165
+{
166
+	le32p_replace_bits((__pdesc + 4), __val, BIT(31));
167
+}
198168 
199169 /* Dword 5 */
200
-#define SET_TX_DESC_PACKET_ID(__pdesc, __val)			\
201
-	SET_BITS_OFFSET_LE(__pdesc + 20, 0, 9, __val)
202
-#define SET_TX_DESC_TX_RATE(__pdesc, __val)			\
203
-	SET_BITS_OFFSET_LE(__pdesc + 20, 9, 6, __val)
204
-#define SET_TX_DESC_DISABLE_FB(__pdesc, __val)			\
205
-	SET_BITS_OFFSET_LE(__pdesc + 20, 15, 1, __val)
206
-#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val)		\
207
-	SET_BITS_OFFSET_LE(__pdesc + 20, 16, 5, __val)
208
-#define SET_TX_DESC_TX_AGC(__pdesc, __val)			\
209
-	SET_BITS_OFFSET_LE(__pdesc + 20, 21, 11, __val)
170
+static inline void set_tx_desc_packet_id(__le32 *__pdesc, u32 __val)
171
+{
172
+	le32p_replace_bits((__pdesc + 5), __val, GENMASK(8, 0));
173
+}
210174 
211
-/* Dword 6 */
212
-#define SET_TX_DESC_IP_CHECK_SUM(__pdesc, __val)		\
213
-	SET_BITS_OFFSET_LE(__pdesc + 24, 0, 16, __val)
214
-#define SET_TX_DESC_TCP_CHECK_SUM(__pdesc, __val)		\
215
-	SET_BITS_OFFSET_LE(__pdesc + 24, 16, 16, __val)
175
+static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val)
176
+{
177
+	le32p_replace_bits((__pdesc + 5), __val, GENMASK(14, 9));
178
+}
179
+
180
+static inline void set_tx_desc_data_rate_fb_limit(__le32 *__pdesc, u32 __val)
181
+{
182
+	le32p_replace_bits((__pdesc + 5), __val, GENMASK(20, 16));
183
+}
216184 
217185 /* Dword 7 */
218
-#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val)		\
219
-	SET_BITS_OFFSET_LE(__pdesc + 28, 0, 16, __val)
220
-#define SET_TX_DESC_IP_HEADER_OFFSET(__pdesc, __val)		\
221
-	SET_BITS_OFFSET_LE(__pdesc + 28, 16, 8, __val)
222
-#define SET_TX_DESC_TCP_ENABLE(__pdesc, __val)			\
223
-	SET_BITS_OFFSET_LE(__pdesc + 28, 31, 1, __val)
186
+static inline void set_tx_desc_tx_buffer_size(__le32 *__pdesc, u32 __val)
187
+{
188
+	le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));
189
+}
224190 
225191 /* Dword 8 */
226
-#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val)		\
227
-	SET_BITS_OFFSET_LE(__pdesc + 32, 0, 32, __val)
228
-#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc)			\
229
-	SHIFT_AND_MASK_LE(__pdesc + 32, 0, 32)
192
+static inline void set_tx_desc_tx_buffer_address(__le32 *__pdesc, u32 __val)
193
+{
194
+	*(__pdesc + 8) = cpu_to_le32(__val);
195
+}
196
+
197
+static inline u32 get_tx_desc_tx_buffer_address(__le32 *__pdesc)
198
+{
199
+	return le32_to_cpu(*((__pdesc + 8)));
200
+}
230201 
231202 /* Dword 9 */
232
-#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val)		\
233
-	SET_BITS_OFFSET_LE(__pdesc + 36, 0, 32, __val)
203
+static inline void set_tx_desc_next_desc_address(__le32 *__pdesc, u32 __val)
204
+{
205
+	*(__pdesc + 9) = cpu_to_le32(__val);
206
+}
234207 
235208 /* Because the PCI Tx descriptors are chaied at the
236209  * initialization and all the NextDescAddresses in
....@@ -247,208 +220,115 @@
247220 #define RX_DRV_INFO_SIZE_UNIT				8
248221 
249222 /* DWORD 0 */
250
-#define SET_RX_STATUS_DESC_PKT_LEN(__pdesc, __val)		\
251
-	SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
252
-#define SET_RX_STATUS_DESC_CRC32(__pdesc, __val)		\
253
-	SET_BITS_OFFSET_LE(__pdesc, 14, 1, __val)
254
-#define SET_RX_STATUS_DESC_ICV(__pdesc, __val)			\
255
-	SET_BITS_OFFSET_LE(__pdesc, 15, 1, __val)
256
-#define SET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc, __val)		\
257
-	SET_BITS_OFFSET_LE(__pdesc, 16, 4, __val)
258
-#define SET_RX_STATUS_DESC_SECURITY(__pdesc, __val)		\
259
-	SET_BITS_OFFSET_LE(__pdesc, 20, 3, __val)
260
-#define SET_RX_STATUS_DESC_QOS(__pdesc, __val)			\
261
-	SET_BITS_OFFSET_LE(__pdesc, 23, 1, __val)
262
-#define SET_RX_STATUS_DESC_SHIFT(__pdesc, __val)		\
263
-	SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val)
264
-#define SET_RX_STATUS_DESC_PHY_STATUS(__pdesc, __val)		\
265
-	SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
266
-#define SET_RX_STATUS_DESC_SWDEC(__pdesc, __val)		\
267
-	SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
268
-#define SET_RX_STATUS_DESC_LAST_SEG(__pdesc, __val)		\
269
-	SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
270
-#define SET_RX_STATUS_DESC_FIRST_SEG(__pdesc, __val)		\
271
-	SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
272
-#define SET_RX_STATUS_DESC_EOR(__pdesc, __val)			\
273
-	SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
274
-#define SET_RX_STATUS_DESC_OWN(__pdesc, __val)			\
275
-	SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
223
+static inline void set_rx_status_desc_pkt_len(__le32 *__pdesc, u32 __val)
224
+{
225
+	le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));
226
+}
276227 
277
-#define GET_RX_STATUS_DESC_PKT_LEN(__pdesc)			\
278
-	SHIFT_AND_MASK_LE(__pdesc, 0, 14)
279
-#define GET_RX_STATUS_DESC_CRC32(__pdesc)			\
280
-	SHIFT_AND_MASK_LE(__pdesc, 14, 1)
281
-#define GET_RX_STATUS_DESC_ICV(__pdesc)				\
282
-	SHIFT_AND_MASK_LE(__pdesc, 15, 1)
283
-#define GET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc)		\
284
-	SHIFT_AND_MASK_LE(__pdesc, 16, 4)
285
-#define GET_RX_STATUS_DESC_SECURITY(__pdesc)			\
286
-	SHIFT_AND_MASK_LE(__pdesc, 20, 3)
287
-#define GET_RX_STATUS_DESC_QOS(__pdesc)				\
288
-	SHIFT_AND_MASK_LE(__pdesc, 23, 1)
289
-#define GET_RX_STATUS_DESC_SHIFT(__pdesc)			\
290
-	SHIFT_AND_MASK_LE(__pdesc, 24, 2)
291
-#define GET_RX_STATUS_DESC_PHY_STATUS(__pdesc)			\
292
-	SHIFT_AND_MASK_LE(__pdesc, 26, 1)
293
-#define GET_RX_STATUS_DESC_SWDEC(__pdesc)			\
294
-	SHIFT_AND_MASK_LE(__pdesc, 27, 1)
295
-#define GET_RX_STATUS_DESC_LAST_SEG(__pdesc)			\
296
-	SHIFT_AND_MASK_LE(__pdesc, 28, 1)
297
-#define GET_RX_STATUS_DESC_FIRST_SEG(__pdesc)			\
298
-	SHIFT_AND_MASK_LE(__pdesc, 29, 1)
299
-#define GET_RX_STATUS_DESC_EOR(__pdesc)				\
300
-	SHIFT_AND_MASK_LE(__pdesc, 30, 1)
301
-#define GET_RX_STATUS_DESC_OWN(__pdesc)				\
302
-	SHIFT_AND_MASK_LE(__pdesc, 31, 1)
228
+static inline void set_rx_status_desc_eor(__le32 *__pdesc, u32 __val)
229
+{
230
+	le32p_replace_bits(__pdesc, __val, BIT(30));
231
+}
232
+
233
+static inline void set_rx_status_desc_own(__le32 *__pdesc, u32 __val)
234
+{
235
+	le32p_replace_bits(__pdesc, __val, BIT(31));
236
+}
237
+
238
+static inline u32 get_rx_status_desc_pkt_len(__le32 *__pdesc)
239
+{
240
+	return le32_get_bits(*(__pdesc), GENMASK(13, 0));
241
+}
242
+
243
+static inline u32 get_rx_status_desc_crc32(__le32 *__pdesc)
244
+{
245
+	return le32_get_bits(*(__pdesc), BIT(14));
246
+}
247
+
248
+static inline u32 get_rx_status_desc_icv(__le32 *__pdesc)
249
+{
250
+	return le32_get_bits(*(__pdesc), BIT(15));
251
+}
252
+
253
+static inline u32 get_rx_status_desc_drvinfo_size(__le32 *__pdesc)
254
+{
255
+	return le32_get_bits(*(__pdesc), GENMASK(19, 16));
256
+}
257
+
258
+static inline u32 get_rx_status_desc_shift(__le32 *__pdesc)
259
+{
260
+	return le32_get_bits(*(__pdesc), GENMASK(25, 24));
261
+}
262
+
263
+static inline u32 get_rx_status_desc_phy_status(__le32 *__pdesc)
264
+{
265
+	return le32_get_bits(*(__pdesc), BIT(26));
266
+}
267
+
268
+static inline u32 get_rx_status_desc_swdec(__le32 *__pdesc)
269
+{
270
+	return le32_get_bits(*(__pdesc), BIT(27));
271
+}
272
+
273
+static inline u32 get_rx_status_desc_own(__le32 *__pdesc)
274
+{
275
+	return le32_get_bits(*(__pdesc), BIT(31));
276
+}
303277 
304278 /* DWORD 1 */
305
-#define SET_RX_STATUS_DESC_MACID(__pdesc, __val)		\
306
-	SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val)
307
-#define SET_RX_STATUS_DESC_TID(__pdesc, __val)			\
308
-	SET_BITS_OFFSET_LE(__pdesc + 4, 5, 4, __val)
309
-#define SET_RX_STATUS_DESC_PAGGR(__pdesc, __val)		\
310
-	SET_BITS_OFFSET_LE(__pdesc + 4, 14, 1, __val)
311
-#define SET_RX_STATUS_DESC_FAGGR(__pdesc, __val)		\
312
-	SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val)
313
-#define SET_RX_STATUS_DESC_A1_FIT(__pdesc, __val)		\
314
-	SET_BITS_OFFSET_LE(__pdesc + 4, 16, 4, __val)
315
-#define SET_RX_STATUS_DESC_A2_FIT(__pdesc, __val)		\
316
-	SET_BITS_OFFSET_LE(__pdesc + 4, 20, 4, __val)
317
-#define SET_RX_STATUS_DESC_PAM(__pdesc, __val)			\
318
-	SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val)
319
-#define SET_RX_STATUS_DESC_PWR(__pdesc, __val)			\
320
-	SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val)
321
-#define SET_RX_STATUS_DESC_MOREDATA(__pdesc, __val)		\
322
-	SET_BITS_OFFSET_LE(__pdesc + 4, 26, 1, __val)
323
-#define SET_RX_STATUS_DESC_MOREFRAG(__pdesc, __val)		\
324
-	SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val)
325
-#define SET_RX_STATUS_DESC_TYPE(__pdesc, __val)			\
326
-	SET_BITS_OFFSET_LE(__pdesc + 4, 28, 2, __val)
327
-#define SET_RX_STATUS_DESC_MC(__pdesc, __val)			\
328
-	SET_BITS_OFFSET_LE(__pdesc + 4, 30, 1, __val)
329
-#define SET_RX_STATUS_DESC_BC(__pdesc, __val)			\
330
-	SET_BITS_OFFSET_LE(__pdesc + 4, 31, 1, __val)
279
+static inline u32 get_rx_status_desc_paggr(__le32 *__pdesc)
280
+{
281
+	return le32_get_bits(*(__pdesc + 1), BIT(14));
282
+}
331283 
332
-#define GET_RX_STATUS_DEC_MACID(__pdesc)			\
333
-	SHIFT_AND_MASK_LE(__pdesc + 4, 0, 5)
334
-#define GET_RX_STATUS_DESC_TID(__pdesc)				\
335
-	SHIFT_AND_MASK_LE(__pdesc + 4, 5, 4)
336
-#define GET_RX_STATUS_DESC_PAGGR(__pdesc)			\
337
-	SHIFT_AND_MASK_LE(__pdesc + 4, 14, 1)
338
-#define GET_RX_STATUS_DESC_FAGGR(__pdesc)			\
339
-	SHIFT_AND_MASK_LE(__pdesc + 4, 15, 1)
340
-#define GET_RX_STATUS_DESC_A1_FIT(__pdesc)			\
341
-	SHIFT_AND_MASK_LE(__pdesc + 4, 16, 4)
342
-#define GET_RX_STATUS_DESC_A2_FIT(__pdesc)			\
343
-	SHIFT_AND_MASK_LE(__pdesc + 4, 20, 4)
344
-#define GET_RX_STATUS_DESC_PAM(__pdesc)				\
345
-	SHIFT_AND_MASK_LE(__pdesc + 4, 24, 1)
346
-#define GET_RX_STATUS_DESC_PWR(__pdesc)				\
347
-	SHIFT_AND_MASK_LE(__pdesc + 4, 25, 1)
348
-#define GET_RX_STATUS_DESC_MORE_DATA(__pdesc)			\
349
-	SHIFT_AND_MASK_LE(__pdesc + 4, 26, 1)
350
-#define GET_RX_STATUS_DESC_MORE_FRAG(__pdesc)			\
351
-	SHIFT_AND_MASK_LE(__pdesc + 4, 27, 1)
352
-#define GET_RX_STATUS_DESC_TYPE(__pdesc)			\
353
-	SHIFT_AND_MASK_LE(__pdesc + 4, 28, 2)
354
-#define GET_RX_STATUS_DESC_MC(__pdesc)				\
355
-	SHIFT_AND_MASK_LE(__pdesc + 4, 30, 1)
356
-#define GET_RX_STATUS_DESC_BC(__pdesc)				\
357
-	SHIFT_AND_MASK_LE(__pdesc + 4, 31, 1)
358
-
359
-/* DWORD 2 */
360
-#define SET_RX_STATUS_DESC_SEQ(__pdesc, __val)			\
361
-	SET_BITS_OFFSET_LE(__pdesc + 8, 0, 12, __val)
362
-#define SET_RX_STATUS_DESC_FRAG(__pdesc, __val)			\
363
-	SET_BITS_OFFSET_LE(__pdesc + 8, 12, 4, __val)
364
-#define SET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc, __val)		\
365
-	SET_BITS_OFFSET_LE(__pdesc + 8, 16, 8, __val)
366
-#define SET_RX_STATUS_DESC_NEXT_IND(__pdesc, __val)		\
367
-	SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val)
368
-
369
-#define GET_RX_STATUS_DESC_SEQ(__pdesc)				\
370
-	SHIFT_AND_MASK_LE(__pdesc + 8, 0, 12)
371
-#define GET_RX_STATUS_DESC_FRAG(__pdesc)			\
372
-	SHIFT_AND_MASK_LE(__pdesc + 8, 12, 4)
373
-#define GET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc)			\
374
-	SHIFT_AND_MASK_LE(__pdesc + 8, 16, 8)
375
-#define GET_RX_STATUS_DESC_NEXT_IND(__pdesc)			\
376
-	SHIFT_AND_MASK_LE(__pdesc + 8, 30, 1)
284
+static inline u32 get_rx_status_desc_faggr(__le32 *__pdesc)
285
+{
286
+	return le32_get_bits(*(__pdesc + 1), BIT(15));
287
+}
377288 
378289 /* DWORD 3 */
379
-#define SET_RX_STATUS_DESC_RX_MCS(__pdesc, __val)		\
380
-	SET_BITS_OFFSET_LE(__pdesc + 12, 0, 6, __val)
381
-#define SET_RX_STATUS_DESC_RX_HT(__pdesc, __val)		\
382
-	SET_BITS_OFFSET_LE(__pdesc + 12, 6, 1, __val)
383
-#define SET_RX_STATUS_DESC_AMSDU(__pdesc, __val)		\
384
-	SET_BITS_OFFSET_LE(__pdesc + 12, 7, 1, __val)
385
-#define SET_RX_STATUS_DESC_SPLCP(__pdesc, __val)		\
386
-	SET_BITS_OFFSET_LE(__pdesc + 12, 8, 1, __val)
387
-#define SET_RX_STATUS_DESC_BW(__pdesc, __val)			\
388
-	SET_BITS_OFFSET_LE(__pdesc + 12, 9, 1, __val)
389
-#define SET_RX_STATUS_DESC_HTC(__pdesc, __val)			\
390
-	SET_BITS_OFFSET_LE(__pdesc + 12, 10, 1, __val)
391
-#define SET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc, __val)		\
392
-	SET_BITS_OFFSET_LE(__pdesc + 12, 11, 1, __val)
393
-#define SET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc, __val)		\
394
-	SET_BITS_OFFSET_LE(__pdesc + 12, 12, 1, __val)
395
-#define SET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc, __val)	\
396
-	SET_BITS_OFFSET_LE(__pdesc + 12, 13, 1, __val)
397
-#define SET_RX_STATUS_DESC_HWPC_ERR(__pdesc, __val)		\
398
-	SET_BITS_OFFSET_LE(__pdesc + 12, 14, 1, __val)
399
-#define SET_RX_STATUS_DESC_HWPC_IND(__pdesc, __val)		\
400
-	SET_BITS_OFFSET_LE(__pdesc + 12, 15, 1, __val)
401
-#define SET_RX_STATUS_DESC_IV0(__pdesc, __val)			\
402
-	SET_BITS_OFFSET_LE(__pdesc + 12, 16, 16, __val)
290
+static inline u32 get_rx_status_desc_rx_mcs(__le32 *__pdesc)
291
+{
292
+	return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0));
293
+}
403294 
404
-#define GET_RX_STATUS_DESC_RX_MCS(__pdesc)			\
405
-	SHIFT_AND_MASK_LE(__pdesc + 12, 0, 6)
406
-#define GET_RX_STATUS_DESC_RX_HT(__pdesc)			\
407
-	SHIFT_AND_MASK_LE(__pdesc + 12, 6, 1)
408
-#define GET_RX_STATUS_DESC_AMSDU(__pdesc)			\
409
-	SHIFT_AND_MASK_LE(__pdesc + 12, 7, 1)
410
-#define GET_RX_STATUS_DESC_SPLCP(__pdesc)			\
411
-	SHIFT_AND_MASK_LE(__pdesc + 12, 8, 1)
412
-#define GET_RX_STATUS_DESC_BW(__pdesc)				\
413
-	SHIFT_AND_MASK_LE(__pdesc + 12, 9, 1)
414
-#define GET_RX_STATUS_DESC_HTC(__pdesc)				\
415
-	SHIFT_AND_MASK_LE(__pdesc + 12, 10, 1)
416
-#define GET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc)			\
417
-	SHIFT_AND_MASK_LE(__pdesc + 12, 11, 1)
418
-#define GET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc)			\
419
-	SHIFT_AND_MASK_LE(__pdesc + 12, 12, 1)
420
-#define GET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc)		\
421
-	SHIFT_AND_MASK_LE(__pdesc + 12, 13, 1)
422
-#define GET_RX_STATUS_DESC_HWPC_ERR(__pdesc)			\
423
-	SHIFT_AND_MASK_LE(__pdesc + 12, 14, 1)
424
-#define GET_RX_STATUS_DESC_HWPC_IND(__pdesc)			\
425
-	SHIFT_AND_MASK_LE(__pdesc + 12, 15, 1)
426
-#define GET_RX_STATUS_DESC_IV0(__pdesc)				\
427
-	SHIFT_AND_MASK_LE(__pdesc + 12, 16, 16)
295
+static inline u32 get_rx_status_desc_rx_ht(__le32 *__pdesc)
296
+{
297
+	return le32_get_bits(*(__pdesc + 3), BIT(6));
298
+}
428299 
429
-/* DWORD 4 */
430
-#define SET_RX_STATUS_DESC_IV1(__pdesc, __val)			\
431
-	SET_BITS_OFFSET_LE(__pdesc + 16, 0, 32, __val)
432
-#define GET_RX_STATUS_DESC_IV1(__pdesc)				\
433
-	SHIFT_AND_MASK_LE(__pdesc + 16, 0, 32)
300
+static inline u32 get_rx_status_desc_splcp(__le32 *__pdesc)
301
+{
302
+	return le32_get_bits(*(__pdesc + 3), BIT(8));
303
+}
304
+
305
+static inline u32 get_rx_status_desc_bw(__le32 *__pdesc)
306
+{
307
+	return le32_get_bits(*(__pdesc + 3), BIT(9));
308
+}
434309 
435310 /* DWORD 5 */
436
-#define SET_RX_STATUS_DESC_TSFL(__pdesc, __val)			\
437
-	SET_BITS_OFFSET_LE(__pdesc + 20, 0, 32, __val)
438
-#define GET_RX_STATUS_DESC_TSFL(__pdesc)			\
439
-	SHIFT_AND_MASK_LE(__pdesc + 20, 0, 32)
311
+static inline u32 get_rx_status_desc_tsfl(__le32 *__pdesc)
312
+{
313
+	return le32_to_cpu(*((__pdesc + 5)));
314
+}
440315 
441316 /* DWORD 6 */
442
-#define SET_RX_STATUS__DESC_BUFF_ADDR(__pdesc, __val)	\
443
-	SET_BITS_OFFSET_LE(__pdesc + 24, 0, 32, __val)
444
-#define GET_RX_STATUS_DESC_BUFF_ADDR(__pdesc)			\
445
-	SHIFT_AND_MASK_LE(__pdesc + 24, 0, 32)
317
+static inline void set_rx_status__desc_buff_addr(__le32 *__pdesc, u32 __val)
318
+{
319
+	*(__pdesc + 6) = cpu_to_le32(__val);
320
+}
321
+
322
+static inline u32 get_rx_status_desc_buff_addr(__le32 *__pdesc)
323
+{
324
+	return le32_to_cpu(*(__pdesc + 6));
325
+}
446326 
447327 #define SE_RX_HAL_IS_CCK_RATE(_pdesc)\
448
-	(GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE1M ||	\
449
-	 GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE2M ||	\
450
-	 GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE5_5M ||\
451
-	 GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE11M)
328
+	(get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE1M ||	\
329
+	 get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE2M ||	\
330
+	 get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE5_5M ||\
331
+	 get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE11M)
452332 
453333 enum rf_optype {
454334 	RF_OP_BY_SW_3WIRE = 0,