~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,45 +1,38 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* (c) Copyright 2002-2010, Ralink Technology, Inc.
3	4	* Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
4	5	* Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
5	6	* Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
6		- *
7		- * This program is free software; you can redistribute it and/or modify
8		- * it under the terms of the GNU General Public License version 2
9		- * as published by the Free Software Foundation
10		- *
11		- * This program is distributed in the hope that it will be useful,
12		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
13		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14		- * GNU General Public License for more details.
15	7	*/
	8	+
	9	+#include <linux/kernel.h>
	10	+#include <linux/etherdevice.h>
16	11
17	12	#include "mt76x0.h"
18	13	#include "mcu.h"
19	14	#include "eeprom.h"
20		-#include "trace.h"
21	15	#include "phy.h"
22	16	#include "initvals.h"
23	17	#include "initvals_phy.h"
24		-
25		-#include <linux/etherdevice.h>
	18	+#include "../mt76x02_phy.h"
26	19
27	20	static int
28		-mt76x0_rf_csr_wr(struct mt76x0_dev *dev, u32 offset, u8 value)
	21	+mt76x0_rf_csr_wr(struct mt76x02_dev *dev, u32 offset, u8 value)
29	22	{
30	23	int ret = 0;
31	24	u8 bank, reg;
32	25
33		- if (test_bit(MT76_REMOVED, &dev->mt76.state))
	26	+ if (test_bit(MT76_REMOVED, &dev->mphy.state))
34	27	return -ENODEV;
35	28
36	29	bank = MT_RF_BANK(offset);
37	30	reg = MT_RF_REG(offset);
38	31
39		- if (WARN_ON_ONCE(reg > 64) \|\| WARN_ON_ONCE(bank) > 8)
	32	+ if (WARN_ON_ONCE(reg > 127) \|\| WARN_ON_ONCE(bank > 8))
40	33	return -EINVAL;
41	34
42		- mutex_lock(&dev->reg_atomic_mutex);
	35	+ mutex_lock(&dev->phy_mutex);
43	36
44	37	if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) {
45	38	ret = -ETIMEDOUT;
..	..	@@ -47,14 +40,14 @@
47	40	}
48	41
49	42	mt76_wr(dev, MT_RF_CSR_CFG,
50		- FIELD_PREP(MT_RF_CSR_CFG_DATA, value) \|
51		- FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) \|
52		- FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) \|
53		- MT_RF_CSR_CFG_WR \|
54		- MT_RF_CSR_CFG_KICK);
55		- trace_mt76x0_rf_write(&dev->mt76, bank, offset, value);
	43	+ FIELD_PREP(MT_RF_CSR_CFG_DATA, value) \|
	44	+ FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) \|
	45	+ FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) \|
	46	+ MT_RF_CSR_CFG_WR \|
	47	+ MT_RF_CSR_CFG_KICK);
	48	+
56	49	out:
57		- mutex_unlock(&dev->reg_atomic_mutex);
	50	+ mutex_unlock(&dev->phy_mutex);
58	51
59	52	if (ret < 0)
60	53	dev_err(dev->mt76.dev, "Error: RF write %d:%d failed:%d!!\n",
..	..	@@ -63,43 +56,41 @@
63	56	return ret;
64	57	}
65	58
66		-static int
67		-mt76x0_rf_csr_rr(struct mt76x0_dev *dev, u32 offset)
	59	+static int mt76x0_rf_csr_rr(struct mt76x02_dev *dev, u32 offset)
68	60	{
69	61	int ret = -ETIMEDOUT;
70	62	u32 val;
71	63	u8 bank, reg;
72	64
73		- if (test_bit(MT76_REMOVED, &dev->mt76.state))
	65	+ if (test_bit(MT76_REMOVED, &dev->mphy.state))
74	66	return -ENODEV;
75	67
76	68	bank = MT_RF_BANK(offset);
77	69	reg = MT_RF_REG(offset);
78	70
79		- if (WARN_ON_ONCE(reg > 64) \|\| WARN_ON_ONCE(bank) > 8)
	71	+ if (WARN_ON_ONCE(reg > 127) \|\| WARN_ON_ONCE(bank > 8))
80	72	return -EINVAL;
81	73
82		- mutex_lock(&dev->reg_atomic_mutex);
	74	+ mutex_lock(&dev->phy_mutex);
83	75
84	76	if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100))
85	77	goto out;
86	78
87	79	mt76_wr(dev, MT_RF_CSR_CFG,
88		- FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) \|
89		- FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) \|
90		- MT_RF_CSR_CFG_KICK);
	80	+ FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) \|
	81	+ FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) \|
	82	+ MT_RF_CSR_CFG_KICK);
91	83
92	84	if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100))
93	85	goto out;
94	86
95	87	val = mt76_rr(dev, MT_RF_CSR_CFG);
96	88	if (FIELD_GET(MT_RF_CSR_CFG_REG_ID, val) == reg &&
97		- FIELD_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank) {
	89	+ FIELD_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank)
98	90	ret = FIELD_GET(MT_RF_CSR_CFG_DATA, val);
99		- trace_mt76x0_rf_read(&dev->mt76, bank, offset, ret);
100		- }
	91	+
101	92	out:
102		- mutex_unlock(&dev->reg_atomic_mutex);
	93	+ mutex_unlock(&dev->phy_mutex);
103	94
104	95	if (ret < 0)
105	96	dev_err(dev->mt76.dev, "Error: RF read %d:%d failed:%d!!\n",
..	..	@@ -109,36 +100,37 @@
109	100	}
110	101
111	102	static int
112		-rf_wr(struct mt76x0_dev *dev, u32 offset, u8 val)
	103	+mt76x0_rf_wr(struct mt76x02_dev *dev, u32 offset, u8 val)
113	104	{
114		- if (test_bit(MT76_STATE_MCU_RUNNING, &dev->mt76.state)) {
	105	+ if (mt76_is_usb(&dev->mt76)) {
115	106	struct mt76_reg_pair pair = {
116	107	.reg = offset,
117	108	.value = val,
118	109	};
119	110
120		- return mt76x0_write_reg_pairs(dev, MT_MCU_MEMMAP_RF, &pair, 1);
	111	+ WARN_ON_ONCE(!test_bit(MT76_STATE_MCU_RUNNING,
	112	+ &dev->mphy.state));
	113	+ return mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1);
121	114	} else {
122		- WARN_ON_ONCE(1);
123	115	return mt76x0_rf_csr_wr(dev, offset, val);
124	116	}
125	117	}
126	118
127		-static int
128		-rf_rr(struct mt76x0_dev *dev, u32 offset)
	119	+static int mt76x0_rf_rr(struct mt76x02_dev *dev, u32 offset)
129	120	{
130	121	int ret;
131	122	u32 val;
132	123
133		- if (test_bit(MT76_STATE_MCU_RUNNING, &dev->mt76.state)) {
	124	+ if (mt76_is_usb(&dev->mt76)) {
134	125	struct mt76_reg_pair pair = {
135	126	.reg = offset,
136	127	};
137	128
138		- ret = mt76x0_read_reg_pairs(dev, MT_MCU_MEMMAP_RF, &pair, 1);
	129	+ WARN_ON_ONCE(!test_bit(MT76_STATE_MCU_RUNNING,
	130	+ &dev->mphy.state));
	131	+ ret = mt76_rd_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1);
139	132	val = pair.value;
140	133	} else {
141		- WARN_ON_ONCE(1);
142	134	ret = val = mt76x0_rf_csr_rr(dev, offset);
143	135	}
144	136
..	..	@@ -146,46 +138,57 @@
146	138	}
147	139
148	140	static int
149		-rf_rmw(struct mt76x0_dev *dev, u32 offset, u8 mask, u8 val)
	141	+mt76x0_rf_rmw(struct mt76x02_dev *dev, u32 offset, u8 mask, u8 val)
150	142	{
151	143	int ret;
152	144
153		- ret = rf_rr(dev, offset);
	145	+ ret = mt76x0_rf_rr(dev, offset);
154	146	if (ret < 0)
155	147	return ret;
	148	+
156	149	val \|= ret & ~mask;
157		- ret = rf_wr(dev, offset, val);
158		- if (ret)
159		- return ret;
160	150
161		- return val;
	151	+ ret = mt76x0_rf_wr(dev, offset, val);
	152	+ return ret ? ret : val;
162	153	}
163	154
164	155	static int
165		-rf_set(struct mt76x0_dev *dev, u32 offset, u8 val)
	156	+mt76x0_rf_set(struct mt76x02_dev *dev, u32 offset, u8 val)
166	157	{
167		- return rf_rmw(dev, offset, 0, val);
	158	+ return mt76x0_rf_rmw(dev, offset, 0, val);
168	159	}
169	160
170		-#if 0
171	161	static int
172		-rf_clear(struct mt76x0_dev *dev, u32 offset, u8 mask)
	162	+mt76x0_rf_clear(struct mt76x02_dev *dev, u32 offset, u8 mask)
173	163	{
174		- return rf_rmw(dev, offset, mask, 0);
	164	+ return mt76x0_rf_rmw(dev, offset, mask, 0);
175	165	}
176		-#endif
177	166
178		-#define RF_RANDOM_WRITE(dev, tab) \
179		- mt76x0_write_reg_pairs(dev, MT_MCU_MEMMAP_RF, tab, ARRAY_SIZE(tab));
	167	+static void
	168	+mt76x0_phy_rf_csr_wr_rp(struct mt76x02_dev *dev,
	169	+ const struct mt76_reg_pair *data,
	170	+ int n)
	171	+{
	172	+ while (n-- > 0) {
	173	+ mt76x0_rf_csr_wr(dev, data->reg, data->value);
	174	+ data++;
	175	+ }
	176	+}
180	177
181		-int mt76x0_wait_bbp_ready(struct mt76x0_dev *dev)
	178	+#define RF_RANDOM_WRITE(dev, tab) do { \
	179	+ if (mt76_is_mmio(&dev->mt76)) \
	180	+ mt76x0_phy_rf_csr_wr_rp(dev, tab, ARRAY_SIZE(tab)); \
	181	+ else \
	182	+ mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, tab, ARRAY_SIZE(tab));\
	183	+} while (0)
	184	+
	185	+int mt76x0_phy_wait_bbp_ready(struct mt76x02_dev *dev)
182	186	{
183	187	int i = 20;
184	188	u32 val;
185	189
186	190	do {
187	191	val = mt76_rr(dev, MT_BBP(CORE, 0));
188		- printk("BBP version %08x\n", val);
189	192	if (val && ~val)
190	193	break;
191	194	} while (--i);
..	..	@@ -195,129 +198,19 @@
195	198	return -EIO;
196	199	}
197	200
	201	+ dev_dbg(dev->mt76.dev, "BBP version %08x\n", val);
198	202	return 0;
199	203	}
200	204
201	205	static void
202		-mt76x0_bbp_set_ctrlch(struct mt76x0_dev *dev, enum nl80211_chan_width width,
203		- u8 ctrl)
204		-{
205		- int core_val, agc_val;
206		-
207		- switch (width) {
208		- case NL80211_CHAN_WIDTH_80:
209		- core_val = 3;
210		- agc_val = 7;
211		- break;
212		- case NL80211_CHAN_WIDTH_40:
213		- core_val = 2;
214		- agc_val = 3;
215		- break;
216		- default:
217		- core_val = 0;
218		- agc_val = 1;
219		- break;
220		- }
221		-
222		- mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
223		- mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);
224		- mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);
225		- mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);
226		-}
227		-
228		-int mt76x0_phy_get_rssi(struct mt76x0_dev dev, struct mt76x0_rxwi rxwi)
229		-{
230		- s8 lna_gain, rssi_offset;
231		- int val;
232		-
233		- if (dev->mt76.chandef.chan->band == NL80211_BAND_2GHZ) {
234		- lna_gain = dev->ee->lna_gain_2ghz;
235		- rssi_offset = dev->ee->rssi_offset_2ghz[0];
236		- } else {
237		- lna_gain = dev->ee->lna_gain_5ghz[0];
238		- rssi_offset = dev->ee->rssi_offset_5ghz[0];
239		- }
240		-
241		- val = rxwi->rssi[0] + rssi_offset - lna_gain;
242		-
243		- return val;
244		-}
245		-
246		-static void mt76x0_vco_cal(struct mt76x0_dev *dev, u8 channel)
247		-{
248		- u8 val;
249		-
250		- val = rf_rr(dev, MT_RF(0, 4));
251		- if ((val & 0x70) != 0x30)
252		- return;
253		-
254		- /*
255		- * Calibration Mode - Open loop, closed loop, and amplitude:
256		- * B0.R06.[0]: 1
257		- * B0.R06.[3:1] bp_close_code: 100
258		- * B0.R05.[7:0] bp_open_code: 0x0
259		- * B0.R04.[2:0] cal_bits: 000
260		- * B0.R03.[2:0] startup_time: 011
261		- * B0.R03.[6:4] settle_time:
262		- * 80MHz channel: 110
263		- * 40MHz channel: 101
264		- * 20MHz channel: 100
265		- */
266		- val = rf_rr(dev, MT_RF(0, 6));
267		- val &= ~0xf;
268		- val \|= 0x09;
269		- rf_wr(dev, MT_RF(0, 6), val);
270		-
271		- val = rf_rr(dev, MT_RF(0, 5));
272		- if (val != 0)
273		- rf_wr(dev, MT_RF(0, 5), 0x0);
274		-
275		- val = rf_rr(dev, MT_RF(0, 4));
276		- val &= ~0x07;
277		- rf_wr(dev, MT_RF(0, 4), val);
278		-
279		- val = rf_rr(dev, MT_RF(0, 3));
280		- val &= ~0x77;
281		- if (channel == 1 \|\| channel == 7 \|\| channel == 9 \|\| channel >= 13) {
282		- val \|= 0x63;
283		- } else if (channel == 3 \|\| channel == 4 \|\| channel == 10) {
284		- val \|= 0x53;
285		- } else if (channel == 2 \|\| channel == 5 \|\| channel == 6 \|\|
286		- channel == 8 \|\| channel == 11 \|\| channel == 12) {
287		- val \|= 0x43;
288		- } else {
289		- WARN(1, "Unknown channel %u\n", channel);
290		- return;
291		- }
292		- rf_wr(dev, MT_RF(0, 3), val);
293		-
294		- /* TODO replace by mt76x0_rf_set(dev, MT_RF(0, 4), BIT(7)); */
295		- val = rf_rr(dev, MT_RF(0, 4));
296		- val = ((val & ~(0x80)) \| 0x80);
297		- rf_wr(dev, MT_RF(0, 4), val);
298		-
299		- msleep(2);
300		-}
301		-
302		-static void
303		-mt76x0_mac_set_ctrlch(struct mt76x0_dev *dev, bool primary_upper)
304		-{
305		- mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,
306		- primary_upper);
307		-}
308		-
309		-static void
310		-mt76x0_phy_set_band(struct mt76x0_dev *dev, enum nl80211_band band)
	206	+mt76x0_phy_set_band(struct mt76x02_dev *dev, enum nl80211_band band)
311	207	{
312	208	switch (band) {
313	209	case NL80211_BAND_2GHZ:
314	210	RF_RANDOM_WRITE(dev, mt76x0_rf_2g_channel_0_tab);
315	211
316		- rf_wr(dev, MT_RF(5, 0), 0x45);
317		- rf_wr(dev, MT_RF(6, 0), 0x44);
318		-
319		- mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
320		- mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
	212	+ mt76x0_rf_wr(dev, MT_RF(5, 0), 0x45);
	213	+ mt76x0_rf_wr(dev, MT_RF(6, 0), 0x44);
321	214
322	215	mt76_wr(dev, MT_TX_ALC_VGA3, 0x00050007);
323	216	mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x003E0002);
..	..	@@ -325,11 +218,8 @@
325	218	case NL80211_BAND_5GHZ:
326	219	RF_RANDOM_WRITE(dev, mt76x0_rf_5g_channel_0_tab);
327	220
328		- rf_wr(dev, MT_RF(5, 0), 0x44);
329		- rf_wr(dev, MT_RF(6, 0), 0x45);
330		-
331		- mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
332		- mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
	221	+ mt76x0_rf_wr(dev, MT_RF(5, 0), 0x44);
	222	+ mt76x0_rf_wr(dev, MT_RF(6, 0), 0x45);
333	223
334	224	mt76_wr(dev, MT_TX_ALC_VGA3, 0x00000005);
335	225	mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x01010102);
..	..	@@ -339,25 +229,21 @@
339	229	}
340	230	}
341	231
342		-#define EXT_PA_2G_5G 0x0
343		-#define EXT_PA_5G_ONLY 0x1
344		-#define EXT_PA_2G_ONLY 0x2
345		-#define INT_PA_2G_5G 0x3
346		-
347	232	static void
348		-mt76x0_phy_set_chan_rf_params(struct mt76x0_dev *dev, u8 channel, u16 rf_bw_band)
	233	+mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel,
	234	+ u16 rf_bw_band)
349	235	{
	236	+ const struct mt76x0_freq_item *freq_item;
350	237	u16 rf_band = rf_bw_band & 0xff00;
351	238	u16 rf_bw = rf_bw_band & 0x00ff;
	239	+ enum nl80211_band band;
	240	+ bool b_sdm = false;
352	241	u32 mac_reg;
353		- u8 rf_val;
354	242	int i;
355		- bool bSDM = false;
356		- const struct mt76x0_freq_item *freq_item;
357	243
358	244	for (i = 0; i < ARRAY_SIZE(mt76x0_sdm_channel); i++) {
359	245	if (channel == mt76x0_sdm_channel[i]) {
360		- bSDM = true;
	246	+ b_sdm = true;
361	247	break;
362	248	}
363	249	}
..	..	@@ -366,108 +252,84 @@
366	252	if (channel == mt76x0_frequency_plan[i].channel) {
367	253	rf_band = mt76x0_frequency_plan[i].band;
368	254
369		- if (bSDM)
370		- freq_item = &(mt76x0_sdm_frequency_plan[i]);
	255	+ if (b_sdm)
	256	+ freq_item = &mt76x0_sdm_frequency_plan[i];
371	257	else
372		- freq_item = &(mt76x0_frequency_plan[i]);
	258	+ freq_item = &mt76x0_frequency_plan[i];
373	259
374		- rf_wr(dev, MT_RF(0, 37), freq_item->pllR37);
375		- rf_wr(dev, MT_RF(0, 36), freq_item->pllR36);
376		- rf_wr(dev, MT_RF(0, 35), freq_item->pllR35);
377		- rf_wr(dev, MT_RF(0, 34), freq_item->pllR34);
378		- rf_wr(dev, MT_RF(0, 33), freq_item->pllR33);
	260	+ mt76x0_rf_wr(dev, MT_RF(0, 37), freq_item->pllR37);
	261	+ mt76x0_rf_wr(dev, MT_RF(0, 36), freq_item->pllR36);
	262	+ mt76x0_rf_wr(dev, MT_RF(0, 35), freq_item->pllR35);
	263	+ mt76x0_rf_wr(dev, MT_RF(0, 34), freq_item->pllR34);
	264	+ mt76x0_rf_wr(dev, MT_RF(0, 33), freq_item->pllR33);
379	265
380		- rf_val = rf_rr(dev, MT_RF(0, 32));
381		- rf_val &= ~0xE0;
382		- rf_val \|= freq_item->pllR32_b7b5;
383		- rf_wr(dev, MT_RF(0, 32), rf_val);
	266	+ mt76x0_rf_rmw(dev, MT_RF(0, 32), 0xe0,
	267	+ freq_item->pllR32_b7b5);
384	268
385	269	/* R32<4:0> pll_den: (Denomina - 8) */
386		- rf_val = rf_rr(dev, MT_RF(0, 32));
387		- rf_val &= ~0x1F;
388		- rf_val \|= freq_item->pllR32_b4b0;
389		- rf_wr(dev, MT_RF(0, 32), rf_val);
	270	+ mt76x0_rf_rmw(dev, MT_RF(0, 32), MT_RF_PLL_DEN_MASK,
	271	+ freq_item->pllR32_b4b0);
390	272
391	273	/* R31<7:5> */
392		- rf_val = rf_rr(dev, MT_RF(0, 31));
393		- rf_val &= ~0xE0;
394		- rf_val \|= freq_item->pllR31_b7b5;
395		- rf_wr(dev, MT_RF(0, 31), rf_val);
	274	+ mt76x0_rf_rmw(dev, MT_RF(0, 31), 0xe0,
	275	+ freq_item->pllR31_b7b5);
396	276
397	277	/* R31<4:0> pll_k(Nominator) */
398		- rf_val = rf_rr(dev, MT_RF(0, 31));
399		- rf_val &= ~0x1F;
400		- rf_val \|= freq_item->pllR31_b4b0;
401		- rf_wr(dev, MT_RF(0, 31), rf_val);
	278	+ mt76x0_rf_rmw(dev, MT_RF(0, 31), MT_RF_PLL_K_MASK,
	279	+ freq_item->pllR31_b4b0);
402	280
403	281	/* R30<7> sdm_reset_n */
404		- rf_val = rf_rr(dev, MT_RF(0, 30));
405		- rf_val &= ~0x80;
406		- if (bSDM) {
407		- rf_wr(dev, MT_RF(0, 30), rf_val);
408		- rf_val \|= 0x80;
409		- rf_wr(dev, MT_RF(0, 30), rf_val);
	282	+ if (b_sdm) {
	283	+ mt76x0_rf_clear(dev, MT_RF(0, 30),
	284	+ MT_RF_SDM_RESET_MASK);
	285	+ mt76x0_rf_set(dev, MT_RF(0, 30),
	286	+ MT_RF_SDM_RESET_MASK);
410	287	} else {
411		- rf_val \|= freq_item->pllR30_b7;
412		- rf_wr(dev, MT_RF(0, 30), rf_val);
	288	+ mt76x0_rf_rmw(dev, MT_RF(0, 30),
	289	+ MT_RF_SDM_RESET_MASK,
	290	+ freq_item->pllR30_b7);
413	291	}
414	292
415	293	/* R30<6:2> sdmmash_prbs,sin */
416		- rf_val = rf_rr(dev, MT_RF(0, 30));
417		- rf_val &= ~0x7C;
418		- rf_val \|= freq_item->pllR30_b6b2;
419		- rf_wr(dev, MT_RF(0, 30), rf_val);
	294	+ mt76x0_rf_rmw(dev, MT_RF(0, 30),
	295	+ MT_RF_SDM_MASH_PRBS_MASK,
	296	+ freq_item->pllR30_b6b2);
420	297
421	298	/* R30<1> sdm_bp */
422		- rf_val = rf_rr(dev, MT_RF(0, 30));
423		- rf_val &= ~0x02;
424		- rf_val \|= (freq_item->pllR30_b1 << 1);
425		- rf_wr(dev, MT_RF(0, 30), rf_val);
	299	+ mt76x0_rf_rmw(dev, MT_RF(0, 30), MT_RF_SDM_BP_MASK,
	300	+ freq_item->pllR30_b1 << 1);
426	301
427	302	/* R30<0> R29<7:0> (hex) pll_n */
428		- rf_val = freq_item->pll_n & 0x00FF;
429		- rf_wr(dev, MT_RF(0, 29), rf_val);
	303	+ mt76x0_rf_wr(dev, MT_RF(0, 29),
	304	+ freq_item->pll_n & 0xff);
430	305
431		- rf_val = rf_rr(dev, MT_RF(0, 30));
432		- rf_val &= ~0x1;
433		- rf_val \|= ((freq_item->pll_n >> 8) & 0x0001);
434		- rf_wr(dev, MT_RF(0, 30), rf_val);
	306	+ mt76x0_rf_rmw(dev, MT_RF(0, 30), 0x1,
	307	+ (freq_item->pll_n >> 8) & 0x1);
435	308
436	309	/* R28<7:6> isi_iso */
437		- rf_val = rf_rr(dev, MT_RF(0, 28));
438		- rf_val &= ~0xC0;
439		- rf_val \|= freq_item->pllR28_b7b6;
440		- rf_wr(dev, MT_RF(0, 28), rf_val);
	310	+ mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_ISI_ISO_MASK,
	311	+ freq_item->pllR28_b7b6);
441	312
442	313	/* R28<5:4> pfd_dly */
443		- rf_val = rf_rr(dev, MT_RF(0, 28));
444		- rf_val &= ~0x30;
445		- rf_val \|= freq_item->pllR28_b5b4;
446		- rf_wr(dev, MT_RF(0, 28), rf_val);
	314	+ mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_PFD_DLY_MASK,
	315	+ freq_item->pllR28_b5b4);
447	316
448	317	/* R28<3:2> clksel option */
449		- rf_val = rf_rr(dev, MT_RF(0, 28));
450		- rf_val &= ~0x0C;
451		- rf_val \|= freq_item->pllR28_b3b2;
452		- rf_wr(dev, MT_RF(0, 28), rf_val);
	318	+ mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_CLK_SEL_MASK,
	319	+ freq_item->pllR28_b3b2);
453	320
454	321	/* R28<1:0> R27<7:0> R26<7:0> (hex) sdm_k */
455		- rf_val = freq_item->pll_sdm_k & 0x000000FF;
456		- rf_wr(dev, MT_RF(0, 26), rf_val);
	322	+ mt76x0_rf_wr(dev, MT_RF(0, 26),
	323	+ freq_item->pll_sdm_k & 0xff);
	324	+ mt76x0_rf_wr(dev, MT_RF(0, 27),
	325	+ (freq_item->pll_sdm_k >> 8) & 0xff);
457	326
458		- rf_val = ((freq_item->pll_sdm_k >> 8) & 0x000000FF);
459		- rf_wr(dev, MT_RF(0, 27), rf_val);
460		-
461		- rf_val = rf_rr(dev, MT_RF(0, 28));
462		- rf_val &= ~0x3;
463		- rf_val \|= ((freq_item->pll_sdm_k >> 16) & 0x0003);
464		- rf_wr(dev, MT_RF(0, 28), rf_val);
	327	+ mt76x0_rf_rmw(dev, MT_RF(0, 28), 0x3,
	328	+ (freq_item->pll_sdm_k >> 16) & 0x3);
465	329
466	330	/* R24<1:0> xo_div */
467		- rf_val = rf_rr(dev, MT_RF(0, 24));
468		- rf_val &= ~0x3;
469		- rf_val \|= freq_item->pllR24_b1b0;
470		- rf_wr(dev, MT_RF(0, 24), rf_val);
	331	+ mt76x0_rf_rmw(dev, MT_RF(0, 24), MT_RF_XO_DIV_MASK,
	332	+ freq_item->pllR24_b1b0);
471	333
472	334	break;
473	335	}
..	..	@@ -475,51 +337,46 @@
475	337
476	338	for (i = 0; i < ARRAY_SIZE(mt76x0_rf_bw_switch_tab); i++) {
477	339	if (rf_bw == mt76x0_rf_bw_switch_tab[i].bw_band) {
478		- rf_wr(dev, mt76x0_rf_bw_switch_tab[i].rf_bank_reg,
479		- mt76x0_rf_bw_switch_tab[i].value);
	340	+ mt76x0_rf_wr(dev,
	341	+ mt76x0_rf_bw_switch_tab[i].rf_bank_reg,
	342	+ mt76x0_rf_bw_switch_tab[i].value);
480	343	} else if ((rf_bw == (mt76x0_rf_bw_switch_tab[i].bw_band & 0xFF)) &&
481	344	(rf_band & mt76x0_rf_bw_switch_tab[i].bw_band)) {
482		- rf_wr(dev, mt76x0_rf_bw_switch_tab[i].rf_bank_reg,
483		- mt76x0_rf_bw_switch_tab[i].value);
	345	+ mt76x0_rf_wr(dev,
	346	+ mt76x0_rf_bw_switch_tab[i].rf_bank_reg,
	347	+ mt76x0_rf_bw_switch_tab[i].value);
484	348	}
485	349	}
486	350
487	351	for (i = 0; i < ARRAY_SIZE(mt76x0_rf_band_switch_tab); i++) {
488	352	if (mt76x0_rf_band_switch_tab[i].bw_band & rf_band) {
489		- rf_wr(dev, mt76x0_rf_band_switch_tab[i].rf_bank_reg,
490		- mt76x0_rf_band_switch_tab[i].value);
	353	+ mt76x0_rf_wr(dev,
	354	+ mt76x0_rf_band_switch_tab[i].rf_bank_reg,
	355	+ mt76x0_rf_band_switch_tab[i].value);
491	356	}
492	357	}
493	358
494		- mac_reg = mt76_rr(dev, MT_RF_MISC);
495		- mac_reg &= ~0xC; /* Clear 0x518[3:2] */
496		- mt76_wr(dev, MT_RF_MISC, mac_reg);
	359	+ mt76_clear(dev, MT_RF_MISC, 0xc);
497	360
498		- if (dev->ee->pa_type == INT_PA_2G_5G \|\|
499		- (dev->ee->pa_type == EXT_PA_5G_ONLY && (rf_band & RF_G_BAND)) \|\|
500		- (dev->ee->pa_type == EXT_PA_2G_ONLY && (rf_band & RF_A_BAND))) {
501		- ; /* Internal PA - nothing to do. */
502		- } else {
503		- /*
504		- MT_RF_MISC (offset: 0x0518)
505		- [2]1'b1: enable external A band PA, 1'b0: disable external A band PA
506		- [3]1'b1: enable external G band PA, 1'b0: disable external G band PA
507		- */
508		- if (rf_band & RF_A_BAND) {
509		- mac_reg = mt76_rr(dev, MT_RF_MISC);
510		- mac_reg \|= 0x4;
511		- mt76_wr(dev, MT_RF_MISC, mac_reg);
512		- } else {
513		- mac_reg = mt76_rr(dev, MT_RF_MISC);
514		- mac_reg \|= 0x8;
515		- mt76_wr(dev, MT_RF_MISC, mac_reg);
516		- }
	361	+ band = (rf_band & RF_G_BAND) ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
	362	+ if (mt76x02_ext_pa_enabled(dev, band)) {
	363	+ /* MT_RF_MISC (offset: 0x0518)
	364	+ * [2]1'b1: enable external A band PA
	365	+ * 1'b0: disable external A band PA
	366	+ * [3]1'b1: enable external G band PA
	367	+ * 1'b0: disable external G band PA
	368	+ */
	369	+ if (rf_band & RF_A_BAND)
	370	+ mt76_set(dev, MT_RF_MISC, BIT(2));
	371	+ else
	372	+ mt76_set(dev, MT_RF_MISC, BIT(3));
517	373
518	374	/* External PA */
519	375	for (i = 0; i < ARRAY_SIZE(mt76x0_rf_ext_pa_tab); i++)
520	376	if (mt76x0_rf_ext_pa_tab[i].bw_band & rf_band)
521		- rf_wr(dev, mt76x0_rf_ext_pa_tab[i].rf_bank_reg,
522		- mt76x0_rf_ext_pa_tab[i].value);
	377	+ mt76x0_rf_wr(dev,
	378	+ mt76x0_rf_ext_pa_tab[i].rf_bank_reg,
	379	+ mt76x0_rf_ext_pa_tab[i].value);
523	380	}
524	381
525	382	if (rf_band & RF_G_BAND) {
..	..	@@ -530,7 +387,9 @@
530	387	mt76_wr(dev, MT_TX_ALC_CFG_1, mac_reg);
531	388	} else {
532	389	mt76_wr(dev, MT_TX0_RF_GAIN_ATTEN, 0x686A7800);
533		- /* Set Atten mode = 0 For Ext A band, Disable Tx Inc dcoc Cal. */
	390	+ /* Set Atten mode = 0
	391	+ * For Ext A band, Disable Tx Inc dcoc Cal.
	392	+ */
534	393	mac_reg = mt76_rr(dev, MT_TX_ALC_CFG_1);
535	394	mac_reg &= 0x890400FF;
536	395	mt76_wr(dev, MT_TX_ALC_CFG_1, mac_reg);
..	..	@@ -538,7 +397,7 @@
538	397	}
539	398
540	399	static void
541		-mt76x0_phy_set_chan_bbp_params(struct mt76x0_dev *dev, u8 channel, u16 rf_bw_band)
	400	+mt76x0_phy_set_chan_bbp_params(struct mt76x02_dev *dev, u16 rf_bw_band)
542	401	{
543	402	int i;
544	403
..	..	@@ -551,20 +410,10 @@
551	410
552	411	if (pair->reg == MT_BBP(AGC, 8)) {
553	412	u32 val = pair->value;
554		- u8 gain = FIELD_GET(MT_BBP_AGC_GAIN, val);
	413	+ u8 gain;
555	414
556		- if (channel > 14) {
557		- if (channel < 100)
558		- gain -= dev->ee->lna_gain_5ghz[0]*2;
559		- else if (channel < 137)
560		- gain -= dev->ee->lna_gain_5ghz[1]*2;
561		- else
562		- gain -= dev->ee->lna_gain_5ghz[2]*2;
563		-
564		- } else {
565		- gain -= dev->ee->lna_gain_2ghz*2;
566		- }
567		-
	415	+ gain = FIELD_GET(MT_BBP_AGC_GAIN, val);
	416	+ gain -= dev->cal.rx.lna_gain * 2;
568	417	val &= ~MT_BBP_AGC_GAIN;
569	418	val \|= FIELD_PREP(MT_BBP_AGC_GAIN, gain);
570	419	mt76_wr(dev, pair->reg, val);
..	..	@@ -574,46 +423,54 @@
574	423	}
575	424	}
576	425
577		-#if 0
578		-static void
579		-mt76x0_extra_power_over_mac(struct mt76x0_dev *dev)
	426	+static void mt76x0_phy_ant_select(struct mt76x02_dev *dev)
580	427	{
581		- u32 val;
	428	+ u16 ee_ant = mt76x02_eeprom_get(dev, MT_EE_ANTENNA);
	429	+ u16 ee_cfg1 = mt76x02_eeprom_get(dev, MT_EE_CFG1_INIT);
	430	+ u16 nic_conf2 = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2);
	431	+ u32 wlan, coex3;
	432	+ bool ant_div;
582	433
583		- val = ((mt76_rr(dev, MT_TX_PWR_CFG_1) & 0x00003f00) >> 8);
584		- val \|= ((mt76_rr(dev, MT_TX_PWR_CFG_2) & 0x00003f00) << 8);
585		- mt76_wr(dev, MT_TX_PWR_CFG_7, val);
	434	+ wlan = mt76_rr(dev, MT_WLAN_FUN_CTRL);
	435	+ coex3 = mt76_rr(dev, MT_COEXCFG3);
586	436
587		- /* TODO: fix VHT */
588		- val = ((mt76_rr(dev, MT_TX_PWR_CFG_3) & 0x0000ff00) >> 8);
589		- mt76_wr(dev, MT_TX_PWR_CFG_8, val);
	437	+ ee_ant &= ~(BIT(14) \| BIT(12));
	438	+ wlan &= ~(BIT(6) \| BIT(5));
	439	+ coex3 &= ~GENMASK(5, 2);
590	440
591		- val = ((mt76_rr(dev, MT_TX_PWR_CFG_4) & 0x0000ff00) >> 8);
592		- mt76_wr(dev, MT_TX_PWR_CFG_9, val);
593		-}
594		-
595		-static void
596		-mt76x0_phy_set_tx_power(struct mt76x0_dev *dev, u8 channel, u8 rf_bw_band)
597		-{
598		- u32 val;
599		- int i;
600		- int bw = (rf_bw_band & RF_BW_20) ? 0 : 1;
601		-
602		- for (i = 0; i < 4; i++) {
603		- if (channel <= 14)
604		- val = dev->ee->tx_pwr_cfg_2g[i][bw];
	441	+ if (ee_ant & MT_EE_ANTENNA_DUAL) {
	442	+ /* dual antenna mode */
	443	+ ant_div = !(nic_conf2 & MT_EE_NIC_CONF_2_ANT_OPT) &&
	444	+ (nic_conf2 & MT_EE_NIC_CONF_2_ANT_DIV);
	445	+ if (ant_div)
	446	+ ee_ant \|= BIT(12);
605	447	else
606		- val = dev->ee->tx_pwr_cfg_5g[i][bw];
607		-
608		- mt76_wr(dev, MT_TX_PWR_CFG_0 + 4*i, val);
	448	+ coex3 \|= BIT(4);
	449	+ coex3 \|= BIT(3);
	450	+ if (dev->mt76.cap.has_2ghz)
	451	+ wlan \|= BIT(6);
	452	+ } else {
	453	+ /* sigle antenna mode */
	454	+ if (dev->mt76.cap.has_5ghz) {
	455	+ coex3 \|= BIT(3) \| BIT(4);
	456	+ } else {
	457	+ wlan \|= BIT(6);
	458	+ coex3 \|= BIT(1);
	459	+ }
609	460	}
610	461
611		- mt76x0_extra_power_over_mac(dev);
	462	+ if (is_mt7630(dev))
	463	+ ee_ant \|= BIT(14) \| BIT(11);
	464	+
	465	+ mt76_wr(dev, MT_WLAN_FUN_CTRL, wlan);
	466	+ mt76_rmw(dev, MT_CMB_CTRL, GENMASK(15, 0), ee_ant);
	467	+ mt76_rmw(dev, MT_CSR_EE_CFG1, GENMASK(15, 0), ee_cfg1);
	468	+ mt76_clear(dev, MT_COEXCFG0, BIT(2));
	469	+ mt76_wr(dev, MT_COEXCFG3, coex3);
612	470	}
613		-#endif
614	471
615	472	static void
616		-mt76x0_bbp_set_bw(struct mt76x0_dev *dev, enum nl80211_chan_width width)
	473	+mt76x0_phy_bbp_set_bw(struct mt76x02_dev *dev, enum nl80211_chan_width width)
617	474	{
618	475	enum { BW_20 = 0, BW_40 = 1, BW_80 = 2, BW_10 = 4};
619	476	int bw;
..	..	@@ -637,42 +494,422 @@
637	494	case NL80211_CHAN_WIDTH_160:
638	495	case NL80211_CHAN_WIDTH_5:
639	496	/* TODO error */
640		- return ;
	497	+ return;
641	498	}
642	499
643		- mt76x0_mcu_function_select(dev, BW_SETTING, bw);
	500	+ mt76x02_mcu_function_select(dev, BW_SETTING, bw);
644	501	}
645	502
646		-static void
647		-mt76x0_phy_set_chan_pwr(struct mt76x0_dev *dev, u8 channel)
	503	+static void mt76x0_phy_tssi_dc_calibrate(struct mt76x02_dev *dev)
648	504	{
649		- static const int mt76x0_tx_pwr_ch_list[] = {
650		- 1,2,3,4,5,6,7,8,9,10,11,12,13,14,
651		- 36,38,40,44,46,48,52,54,56,60,62,64,
652		- 100,102,104,108,110,112,116,118,120,124,126,128,132,134,136,140,
653		- 149,151,153,157,159,161,165,167,169,171,173,
654		- 42,58,106,122,155
655		- };
656		- int i;
	505	+ struct ieee80211_channel *chan = dev->mphy.chandef.chan;
657	506	u32 val;
658	507
659		- for (i = 0; i < ARRAY_SIZE(mt76x0_tx_pwr_ch_list); i++)
660		- if (mt76x0_tx_pwr_ch_list[i] == channel)
661		- break;
	508	+ if (chan->band == NL80211_BAND_5GHZ)
	509	+ mt76x0_rf_clear(dev, MT_RF(0, 67), 0xf);
662	510
663		- if (WARN_ON(i == ARRAY_SIZE(mt76x0_tx_pwr_ch_list)))
664		- return;
	511	+ /* bypass ADDA control */
	512	+ mt76_wr(dev, MT_RF_SETTING_0, 0x60002237);
	513	+ mt76_wr(dev, MT_RF_BYPASS_0, 0xffffffff);
665	514
666		- val = mt76_rr(dev, MT_TX_ALC_CFG_0);
667		- val &= ~0x3f3f;
668		- val \|= dev->ee->tx_pwr_per_chan[i];
669		- val \|= 0x2f2f << 16;
670		- mt76_wr(dev, MT_TX_ALC_CFG_0, val);
	515	+ /* bbp sw reset */
	516	+ mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
	517	+ usleep_range(500, 1000);
	518	+ mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
	519	+
	520	+ val = (chan->band == NL80211_BAND_5GHZ) ? 0x80055 : 0x80050;
	521	+ mt76_wr(dev, MT_BBP(CORE, 34), val);
	522	+
	523	+ /* enable TX with DAC0 input */
	524	+ mt76_wr(dev, MT_BBP(TXBE, 6), BIT(31));
	525	+
	526	+ mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200);
	527	+ dev->cal.tssi_dc = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
	528	+
	529	+ /* stop bypass ADDA */
	530	+ mt76_wr(dev, MT_RF_BYPASS_0, 0);
	531	+ /* stop TX */
	532	+ mt76_wr(dev, MT_BBP(TXBE, 6), 0);
	533	+ /* bbp sw reset */
	534	+ mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
	535	+ usleep_range(500, 1000);
	536	+ mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
	537	+
	538	+ if (chan->band == NL80211_BAND_5GHZ)
	539	+ mt76x0_rf_rmw(dev, MT_RF(0, 67), 0xf, 0x4);
671	540	}
672	541
673	542	static int
674		-__mt76x0_phy_set_channel(struct mt76x0_dev *dev,
675		- struct cfg80211_chan_def *chandef)
	543	+mt76x0_phy_tssi_adc_calibrate(struct mt76x02_dev dev, s16 ltssi,
	544	+ u8 *info)
	545	+{
	546	+ struct ieee80211_channel *chan = dev->mphy.chandef.chan;
	547	+ u32 val;
	548	+
	549	+ val = (chan->band == NL80211_BAND_5GHZ) ? 0x80055 : 0x80050;
	550	+ mt76_wr(dev, MT_BBP(CORE, 34), val);
	551	+
	552	+ if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) {
	553	+ mt76_clear(dev, MT_BBP(CORE, 34), BIT(4));
	554	+ return -ETIMEDOUT;
	555	+ }
	556	+
	557	+ *ltssi = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
	558	+ if (chan->band == NL80211_BAND_5GHZ)
	559	+ *ltssi += 128;
	560	+
	561	+ /* set packet info#1 mode */
	562	+ mt76_wr(dev, MT_BBP(CORE, 34), 0x80041);
	563	+ info[0] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
	564	+
	565	+ /* set packet info#2 mode */
	566	+ mt76_wr(dev, MT_BBP(CORE, 34), 0x80042);
	567	+ info[1] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
	568	+
	569	+ /* set packet info#3 mode */
	570	+ mt76_wr(dev, MT_BBP(CORE, 34), 0x80043);
	571	+ info[2] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
	572	+
	573	+ return 0;
	574	+}
	575	+
	576	+static u8 mt76x0_phy_get_rf_pa_mode(struct mt76x02_dev *dev,
	577	+ int index, u8 tx_rate)
	578	+{
	579	+ u32 val, reg;
	580	+
	581	+ reg = (index == 1) ? MT_RF_PA_MODE_CFG1 : MT_RF_PA_MODE_CFG0;
	582	+ val = mt76_rr(dev, reg);
	583	+ return (val & (3 << (tx_rate * 2))) >> (tx_rate * 2);
	584	+}
	585	+
	586	+static int
	587	+mt76x0_phy_get_target_power(struct mt76x02_dev *dev, u8 tx_mode,
	588	+ u8 info, s8 target_power,
	589	+ s8 *target_pa_power)
	590	+{
	591	+ u8 tx_rate, cur_power;
	592	+
	593	+ cur_power = mt76_rr(dev, MT_TX_ALC_CFG_0) & MT_TX_ALC_CFG_0_CH_INIT_0;
	594	+ switch (tx_mode) {
	595	+ case 0:
	596	+ /* cck rates */
	597	+ tx_rate = (info[0] & 0x60) >> 5;
	598	+ if (tx_rate > 3)
	599	+ return -EINVAL;
	600	+
	601	+ *target_power = cur_power + dev->mt76.rate_power.cck[tx_rate];
	602	+ *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 0, tx_rate);
	603	+ break;
	604	+ case 1: {
	605	+ u8 index;
	606	+
	607	+ /* ofdm rates */
	608	+ tx_rate = (info[0] & 0xf0) >> 4;
	609	+ switch (tx_rate) {
	610	+ case 0xb:
	611	+ index = 0;
	612	+ break;
	613	+ case 0xf:
	614	+ index = 1;
	615	+ break;
	616	+ case 0xa:
	617	+ index = 2;
	618	+ break;
	619	+ case 0xe:
	620	+ index = 3;
	621	+ break;
	622	+ case 0x9:
	623	+ index = 4;
	624	+ break;
	625	+ case 0xd:
	626	+ index = 5;
	627	+ break;
	628	+ case 0x8:
	629	+ index = 6;
	630	+ break;
	631	+ case 0xc:
	632	+ index = 7;
	633	+ break;
	634	+ default:
	635	+ return -EINVAL;
	636	+ }
	637	+
	638	+ *target_power = cur_power + dev->mt76.rate_power.ofdm[index];
	639	+ *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 0, index + 4);
	640	+ break;
	641	+ }
	642	+ case 4:
	643	+ /* vht rates */
	644	+ tx_rate = info[1] & 0xf;
	645	+ if (tx_rate > 9)
	646	+ return -EINVAL;
	647	+
	648	+ *target_power = cur_power + dev->mt76.rate_power.vht[tx_rate];
	649	+ *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 1, tx_rate);
	650	+ break;
	651	+ default:
	652	+ /* ht rates */
	653	+ tx_rate = info[1] & 0x7f;
	654	+ if (tx_rate > 9)
	655	+ return -EINVAL;
	656	+
	657	+ *target_power = cur_power + dev->mt76.rate_power.ht[tx_rate];
	658	+ *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 1, tx_rate);
	659	+ break;
	660	+ }
	661	+
	662	+ return 0;
	663	+}
	664	+
	665	+static s16 mt76x0_phy_lin2db(u16 val)
	666	+{
	667	+ u32 mantissa = val << 4;
	668	+ int ret, data;
	669	+ s16 exp = -4;
	670	+
	671	+ while (mantissa < BIT(15)) {
	672	+ mantissa <<= 1;
	673	+ if (--exp < -20)
	674	+ return -10000;
	675	+ }
	676	+ while (mantissa > 0xffff) {
	677	+ mantissa >>= 1;
	678	+ if (++exp > 20)
	679	+ return -10000;
	680	+ }
	681	+
	682	+ /* s(15,0) */
	683	+ if (mantissa <= 47104)
	684	+ data = mantissa + (mantissa >> 3) + (mantissa >> 4) - 38400;
	685	+ else
	686	+ data = mantissa - (mantissa >> 3) - (mantissa >> 6) - 23040;
	687	+ data = max_t(int, 0, data);
	688	+
	689	+ ret = ((15 + exp) << 15) + data;
	690	+ ret = (ret << 2) + (ret << 1) + (ret >> 6) + (ret >> 7);
	691	+ return ret >> 10;
	692	+}
	693	+
	694	+static int
	695	+mt76x0_phy_get_delta_power(struct mt76x02_dev *dev, u8 tx_mode,
	696	+ s8 target_power, s8 target_pa_power,
	697	+ s16 ltssi)
	698	+{
	699	+ struct ieee80211_channel *chan = dev->mphy.chandef.chan;
	700	+ int tssi_target = target_power << 12, tssi_slope;
	701	+ int tssi_offset, tssi_db, ret;
	702	+ u32 data;
	703	+ u16 val;
	704	+
	705	+ if (chan->band == NL80211_BAND_5GHZ) {
	706	+ u8 bound[7];
	707	+ int i, err;
	708	+
	709	+ err = mt76x02_eeprom_copy(dev, MT_EE_TSSI_BOUND1, bound,
	710	+ sizeof(bound));
	711	+ if (err < 0)
	712	+ return err;
	713	+
	714	+ for (i = 0; i < ARRAY_SIZE(bound); i++) {
	715	+ if (chan->hw_value <= bound[i] \|\| !bound[i])
	716	+ break;
	717	+ }
	718	+ val = mt76x02_eeprom_get(dev, MT_EE_TSSI_SLOPE_5G + i * 2);
	719	+
	720	+ tssi_offset = val >> 8;
	721	+ if ((tssi_offset >= 64 && tssi_offset <= 127) \|\|
	722	+ (tssi_offset & BIT(7)))
	723	+ tssi_offset -= BIT(8);
	724	+ } else {
	725	+ val = mt76x02_eeprom_get(dev, MT_EE_TSSI_SLOPE_2G);
	726	+
	727	+ tssi_offset = val >> 8;
	728	+ if (tssi_offset & BIT(7))
	729	+ tssi_offset -= BIT(8);
	730	+ }
	731	+ tssi_slope = val & 0xff;
	732	+
	733	+ switch (target_pa_power) {
	734	+ case 1:
	735	+ if (chan->band == NL80211_BAND_2GHZ)
	736	+ tssi_target += 29491; /* 3.6 * 8192 */
	737	+ fallthrough;
	738	+ case 0:
	739	+ break;
	740	+ default:
	741	+ tssi_target += 4424; /* 0.54 * 8192 */
	742	+ break;
	743	+ }
	744	+
	745	+ if (!tx_mode) {
	746	+ data = mt76_rr(dev, MT_BBP(CORE, 1));
	747	+ if (is_mt7630(dev) && mt76_is_mmio(&dev->mt76)) {
	748	+ int offset;
	749	+
	750	+ /* 2.3 * 8192 or 1.5 * 8192 */
	751	+ offset = (data & BIT(5)) ? 18841 : 12288;
	752	+ tssi_target += offset;
	753	+ } else if (data & BIT(5)) {
	754	+ /* 0.8 * 8192 */
	755	+ tssi_target += 6554;
	756	+ }
	757	+ }
	758	+
	759	+ data = mt76_rr(dev, MT_BBP(TXBE, 4));
	760	+ switch (data & 0x3) {
	761	+ case 1:
	762	+ tssi_target -= 49152; /* -6db * 8192 */
	763	+ break;
	764	+ case 2:
	765	+ tssi_target -= 98304; /* -12db * 8192 */
	766	+ break;
	767	+ case 3:
	768	+ tssi_target += 49152; /* 6db * 8192 */
	769	+ break;
	770	+ default:
	771	+ break;
	772	+ }
	773	+
	774	+ tssi_db = mt76x0_phy_lin2db(ltssi - dev->cal.tssi_dc) * tssi_slope;
	775	+ if (chan->band == NL80211_BAND_5GHZ) {
	776	+ tssi_db += ((tssi_offset - 50) << 10); /* offset s4.3 */
	777	+ tssi_target -= tssi_db;
	778	+ if (ltssi > 254 && tssi_target > 0) {
	779	+ /* upper saturate */
	780	+ tssi_target = 0;
	781	+ }
	782	+ } else {
	783	+ tssi_db += (tssi_offset << 9); /* offset s3.4 */
	784	+ tssi_target -= tssi_db;
	785	+ /* upper-lower saturate */
	786	+ if ((ltssi > 126 && tssi_target > 0) \|\|
	787	+ ((ltssi - dev->cal.tssi_dc) < 1 && tssi_target < 0)) {
	788	+ tssi_target = 0;
	789	+ }
	790	+ }
	791	+
	792	+ if ((dev->cal.tssi_target ^ tssi_target) < 0 &&
	793	+ dev->cal.tssi_target > -4096 && dev->cal.tssi_target < 4096 &&
	794	+ tssi_target > -4096 && tssi_target < 4096) {
	795	+ if ((tssi_target < 0 &&
	796	+ tssi_target + dev->cal.tssi_target > 0) \|\|
	797	+ (tssi_target > 0 &&
	798	+ tssi_target + dev->cal.tssi_target <= 0))
	799	+ tssi_target = 0;
	800	+ else
	801	+ dev->cal.tssi_target = tssi_target;
	802	+ } else {
	803	+ dev->cal.tssi_target = tssi_target;
	804	+ }
	805	+
	806	+ /* make the compensate value to the nearest compensate code */
	807	+ if (tssi_target > 0)
	808	+ tssi_target += 2048;
	809	+ else
	810	+ tssi_target -= 2048;
	811	+ tssi_target >>= 12;
	812	+
	813	+ ret = mt76_get_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP);
	814	+ if (ret & BIT(5))
	815	+ ret -= BIT(6);
	816	+ ret += tssi_target;
	817	+
	818	+ ret = min_t(int, 31, ret);
	819	+ return max_t(int, -32, ret);
	820	+}
	821	+
	822	+static void mt76x0_phy_tssi_calibrate(struct mt76x02_dev *dev)
	823	+{
	824	+ s8 target_power, target_pa_power;
	825	+ u8 tssi_info[3], tx_mode;
	826	+ s16 ltssi;
	827	+ s8 val;
	828	+
	829	+ if (mt76x0_phy_tssi_adc_calibrate(dev, &ltssi, tssi_info) < 0)
	830	+ return;
	831	+
	832	+ tx_mode = tssi_info[0] & 0x7;
	833	+ if (mt76x0_phy_get_target_power(dev, tx_mode, tssi_info,
	834	+ &target_power, &target_pa_power) < 0)
	835	+ return;
	836	+
	837	+ val = mt76x0_phy_get_delta_power(dev, tx_mode, target_power,
	838	+ target_pa_power, ltssi);
	839	+ mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, val);
	840	+}
	841	+
	842	+void mt76x0_phy_set_txpower(struct mt76x02_dev *dev)
	843	+{
	844	+ struct mt76_rate_power *t = &dev->mt76.rate_power;
	845	+ s8 info;
	846	+
	847	+ mt76x0_get_tx_power_per_rate(dev, dev->mphy.chandef.chan, t);
	848	+ mt76x0_get_power_info(dev, dev->mphy.chandef.chan, &info);
	849	+
	850	+ mt76x02_add_rate_power_offset(t, info);
	851	+ mt76x02_limit_rate_power(t, dev->txpower_conf);
	852	+ dev->mphy.txpower_cur = mt76x02_get_max_rate_power(t);
	853	+ mt76x02_add_rate_power_offset(t, -info);
	854	+
	855	+ dev->target_power = info;
	856	+ mt76x02_phy_set_txpower(dev, info, info);
	857	+}
	858	+
	859	+void mt76x0_phy_calibrate(struct mt76x02_dev *dev, bool power_on)
	860	+{
	861	+ struct ieee80211_channel *chan = dev->mphy.chandef.chan;
	862	+ int is_5ghz = (chan->band == NL80211_BAND_5GHZ) ? 1 : 0;
	863	+ u32 val, tx_alc, reg_val;
	864	+
	865	+ if (is_mt7630(dev))
	866	+ return;
	867	+
	868	+ if (power_on) {
	869	+ mt76x02_mcu_calibrate(dev, MCU_CAL_R, 0);
	870	+ mt76x02_mcu_calibrate(dev, MCU_CAL_VCO, chan->hw_value);
	871	+ usleep_range(10, 20);
	872	+
	873	+ if (mt76x0_tssi_enabled(dev)) {
	874	+ mt76_wr(dev, MT_MAC_SYS_CTRL,
	875	+ MT_MAC_SYS_CTRL_ENABLE_RX);
	876	+ mt76x0_phy_tssi_dc_calibrate(dev);
	877	+ mt76_wr(dev, MT_MAC_SYS_CTRL,
	878	+ MT_MAC_SYS_CTRL_ENABLE_TX \|
	879	+ MT_MAC_SYS_CTRL_ENABLE_RX);
	880	+ }
	881	+ }
	882	+
	883	+ tx_alc = mt76_rr(dev, MT_TX_ALC_CFG_0);
	884	+ mt76_wr(dev, MT_TX_ALC_CFG_0, 0);
	885	+ usleep_range(500, 700);
	886	+
	887	+ reg_val = mt76_rr(dev, MT_BBP(IBI, 9));
	888	+ mt76_wr(dev, MT_BBP(IBI, 9), 0xffffff7e);
	889	+
	890	+ if (is_5ghz) {
	891	+ if (chan->hw_value < 100)
	892	+ val = 0x701;
	893	+ else if (chan->hw_value < 140)
	894	+ val = 0x801;
	895	+ else
	896	+ val = 0x901;
	897	+ } else {
	898	+ val = 0x600;
	899	+ }
	900	+
	901	+ mt76x02_mcu_calibrate(dev, MCU_CAL_FULL, val);
	902	+ mt76x02_mcu_calibrate(dev, MCU_CAL_LC, is_5ghz);
	903	+ usleep_range(15000, 20000);
	904	+
	905	+ mt76_wr(dev, MT_BBP(IBI, 9), reg_val);
	906	+ mt76_wr(dev, MT_TX_ALC_CFG_0, tx_alc);
	907	+ mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, 1);
	908	+}
	909	+EXPORT_SYMBOL_GPL(mt76x0_phy_calibrate);
	910	+
	911	+void mt76x0_phy_set_channel(struct mt76x02_dev *dev,
	912	+ struct cfg80211_chan_def *chandef)
676	913	{
677	914	u32 ext_cca_chan[4] = {
678	915	[0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) \|
..	..	@@ -696,7 +933,7 @@
696	933	FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) \|
697	934	FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(3)),
698	935	};
699		- bool scan = test_bit(MT76_SCANNING, &dev->mt76.state);
	936	+ bool scan = test_bit(MT76_SCANNING, &dev->mphy.state);
700	937	int ch_group_index, freq, freq1;
701	938	u8 channel;
702	939	u32 val;
..	..	@@ -729,9 +966,19 @@
729	966	break;
730	967	}
731	968
732		- mt76x0_bbp_set_bw(dev, chandef->width);
733		- mt76x0_bbp_set_ctrlch(dev, chandef->width, ch_group_index);
734		- mt76x0_mac_set_ctrlch(dev, ch_group_index & 1);
	969	+ if (mt76_is_usb(&dev->mt76)) {
	970	+ mt76x0_phy_bbp_set_bw(dev, chandef->width);
	971	+ } else {
	972	+ if (chandef->width == NL80211_CHAN_WIDTH_80 \|\|
	973	+ chandef->width == NL80211_CHAN_WIDTH_40)
	974	+ val = 0x201;
	975	+ else
	976	+ val = 0x601;
	977	+ mt76_wr(dev, MT_TX_SW_CFG0, val);
	978	+ }
	979	+ mt76x02_phy_set_bw(dev, chandef->width, ch_group_index);
	980	+ mt76x02_phy_set_band(dev, chandef->chan->band,
	981	+ ch_group_index & 1);
735	982
736	983	mt76_rmw(dev, MT_EXT_CCA_CFG,
737	984	(MT_EXT_CCA_CFG_CCA0 \|
..	..	@@ -745,201 +992,174 @@
745	992	mt76x0_phy_set_chan_rf_params(dev, channel, rf_bw_band);
746	993
747	994	/* set Japan Tx filter at channel 14 */
748		- val = mt76_rr(dev, MT_BBP(CORE, 1));
749	995	if (channel == 14)
750		- val \|= 0x20;
	996	+ mt76_set(dev, MT_BBP(CORE, 1), 0x20);
751	997	else
752		- val &= ~0x20;
753		- mt76_wr(dev, MT_BBP(CORE, 1), val);
	998	+ mt76_clear(dev, MT_BBP(CORE, 1), 0x20);
754	999
755		- mt76x0_phy_set_chan_bbp_params(dev, channel, rf_bw_band);
	1000	+ mt76x0_read_rx_gain(dev);
	1001	+ mt76x0_phy_set_chan_bbp_params(dev, rf_bw_band);
756	1002
757		- /* Vendor driver don't do it */
758		- /* mt76x0_phy_set_tx_power(dev, channel, rf_bw_band); */
759		-
760		- mt76x0_vco_cal(dev, channel);
	1003	+ /* enable vco */
	1004	+ mt76x0_rf_set(dev, MT_RF(0, 4), BIT(7));
761	1005	if (scan)
762		- mt76x0_mcu_calibrate(dev, MCU_CAL_RXDCOC, 1);
	1006	+ return;
763	1007
764		- mt76x0_phy_set_chan_pwr(dev, channel);
765		-
766		- dev->mt76.chandef = *chandef;
767		- return 0;
768		-}
769		-
770		-int mt76x0_phy_set_channel(struct mt76x0_dev *dev,
771		- struct cfg80211_chan_def *chandef)
772		-{
773		- int ret;
774		-
775		- mutex_lock(&dev->hw_atomic_mutex);
776		- ret = __mt76x0_phy_set_channel(dev, chandef);
777		- mutex_unlock(&dev->hw_atomic_mutex);
778		-
779		- return ret;
780		-}
781		-
782		-void mt76x0_phy_recalibrate_after_assoc(struct mt76x0_dev *dev)
783		-{
784		- u32 tx_alc, reg_val;
785		- u8 channel = dev->mt76.chandef.chan->hw_value;
786		- int is_5ghz = (dev->mt76.chandef.chan->band == NL80211_BAND_5GHZ) ? 1 : 0;
787		-
788		- mt76x0_mcu_calibrate(dev, MCU_CAL_R, 0);
789		-
790		- mt76x0_vco_cal(dev, channel);
791		-
792		- tx_alc = mt76_rr(dev, MT_TX_ALC_CFG_0);
793		- mt76_wr(dev, MT_TX_ALC_CFG_0, 0);
794		- usleep_range(500, 700);
795		-
796		- reg_val = mt76_rr(dev, MT_BBP(IBI, 9));
797		- mt76_wr(dev, MT_BBP(IBI, 9), 0xffffff7e);
798		-
799		- mt76x0_mcu_calibrate(dev, MCU_CAL_RXDCOC, 0);
800		-
801		- mt76x0_mcu_calibrate(dev, MCU_CAL_LC, is_5ghz);
802		- mt76x0_mcu_calibrate(dev, MCU_CAL_LOFT, is_5ghz);
803		- mt76x0_mcu_calibrate(dev, MCU_CAL_TXIQ, is_5ghz);
804		- mt76x0_mcu_calibrate(dev, MCU_CAL_TX_GROUP_DELAY, is_5ghz);
805		- mt76x0_mcu_calibrate(dev, MCU_CAL_RXIQ, is_5ghz);
806		- mt76x0_mcu_calibrate(dev, MCU_CAL_RX_GROUP_DELAY, is_5ghz);
807		-
808		- mt76_wr(dev, MT_BBP(IBI, 9), reg_val);
809		- mt76_wr(dev, MT_TX_ALC_CFG_0, tx_alc);
810		- msleep(100);
811		-
812		- mt76x0_mcu_calibrate(dev, MCU_CAL_RXDCOC, 1);
813		-}
814		-
815		-void mt76x0_agc_save(struct mt76x0_dev *dev)
816		-{
817		- /* Only one RX path */
818		- dev->agc_save = FIELD_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, 8)));
819		-}
820		-
821		-void mt76x0_agc_restore(struct mt76x0_dev *dev)
822		-{
823		- mt76_rmw_field(dev, MT_BBP(AGC, 8), MT_BBP_AGC_GAIN, dev->agc_save);
824		-}
825		-
826		-static void mt76x0_temp_sensor(struct mt76x0_dev *dev)
827		-{
828		- u8 rf_b7_73, rf_b0_66, rf_b0_67;
829		- int cycle, temp;
830		- u32 val;
831		- s32 sval;
832		-
833		- rf_b7_73 = rf_rr(dev, MT_RF(7, 73));
834		- rf_b0_66 = rf_rr(dev, MT_RF(0, 66));
835		- rf_b0_67 = rf_rr(dev, MT_RF(0, 73));
836		-
837		- rf_wr(dev, MT_RF(7, 73), 0x02);
838		- rf_wr(dev, MT_RF(0, 66), 0x23);
839		- rf_wr(dev, MT_RF(0, 73), 0x01);
840		-
841		- mt76_wr(dev, MT_BBP(CORE, 34), 0x00080055);
842		-
843		- for (cycle = 0; cycle < 2000; cycle++) {
844		- val = mt76_rr(dev, MT_BBP(CORE, 34));
845		- if (!(val & 0x10))
846		- break;
847		- udelay(3);
848		- }
849		-
850		- if (cycle >= 2000) {
851		- val &= 0x10;
852		- mt76_wr(dev, MT_BBP(CORE, 34), val);
853		- goto done;
854		- }
855		-
856		- sval = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
857		- if (!(sval & 0x80))
858		- sval &= 0x7f; /* Positive */
859		- else
860		- sval \|= 0xffffff00; /* Negative */
861		-
862		- temp = (35 * (sval - dev->ee->temp_off))/ 10 + 25;
863		-
864		-done:
865		- rf_wr(dev, MT_RF(7, 73), rf_b7_73);
866		- rf_wr(dev, MT_RF(0, 66), rf_b0_66);
867		- rf_wr(dev, MT_RF(0, 73), rf_b0_67);
868		-}
869		-
870		-static void mt76x0_dynamic_vga_tuning(struct mt76x0_dev *dev)
871		-{
872		- u32 val, init_vga;
873		-
874		- init_vga = (dev->mt76.chandef.chan->band == NL80211_BAND_5GHZ) ? 0x54 : 0x4E;
875		- if (dev->avg_rssi > -60)
876		- init_vga -= 0x20;
877		- else if (dev->avg_rssi > -70)
878		- init_vga -= 0x10;
879		-
880		- val = mt76_rr(dev, MT_BBP(AGC, 8));
881		- val &= 0xFFFF80FF;
882		- val \|= init_vga << 8;
883		- mt76_wr(dev, MT_BBP(AGC,8), val);
884		-}
885		-
886		-static void mt76x0_phy_calibrate(struct work_struct *work)
887		-{
888		- struct mt76x0_dev *dev = container_of(work, struct mt76x0_dev,
889		- cal_work.work);
890		-
891		- mt76x0_dynamic_vga_tuning(dev);
892		- mt76x0_temp_sensor(dev);
	1008	+ mt76x02_init_agc_gain(dev);
	1009	+ mt76x0_phy_calibrate(dev, false);
	1010	+ mt76x0_phy_set_txpower(dev);
893	1011
894	1012	ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work,
895	1013	MT_CALIBRATE_INTERVAL);
896	1014	}
897	1015
898		-void mt76x0_phy_con_cal_onoff(struct mt76x0_dev *dev,
899		- struct ieee80211_bss_conf *info)
	1016	+static void mt76x0_phy_temp_sensor(struct mt76x02_dev *dev)
900	1017	{
901		- /* Start/stop collecting beacon data */
902		- spin_lock_bh(&dev->con_mon_lock);
903		- ether_addr_copy(dev->ap_bssid, info->bssid);
904		- dev->avg_rssi = 0;
905		- dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID;
906		- spin_unlock_bh(&dev->con_mon_lock);
	1018	+ u8 rf_b7_73, rf_b0_66, rf_b0_67;
	1019	+ s8 val;
	1020	+
	1021	+ rf_b7_73 = mt76x0_rf_rr(dev, MT_RF(7, 73));
	1022	+ rf_b0_66 = mt76x0_rf_rr(dev, MT_RF(0, 66));
	1023	+ rf_b0_67 = mt76x0_rf_rr(dev, MT_RF(0, 67));
	1024	+
	1025	+ mt76x0_rf_wr(dev, MT_RF(7, 73), 0x02);
	1026	+ mt76x0_rf_wr(dev, MT_RF(0, 66), 0x23);
	1027	+ mt76x0_rf_wr(dev, MT_RF(0, 67), 0x01);
	1028	+
	1029	+ mt76_wr(dev, MT_BBP(CORE, 34), 0x00080055);
	1030	+ if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) {
	1031	+ mt76_clear(dev, MT_BBP(CORE, 34), BIT(4));
	1032	+ goto done;
	1033	+ }
	1034	+
	1035	+ val = mt76_rr(dev, MT_BBP(CORE, 35));
	1036	+ val = (35 * (val - dev->cal.rx.temp_offset)) / 10 + 25;
	1037	+
	1038	+ if (abs(val - dev->cal.temp_vco) > 20) {
	1039	+ mt76x02_mcu_calibrate(dev, MCU_CAL_VCO,
	1040	+ dev->mphy.chandef.chan->hw_value);
	1041	+ dev->cal.temp_vco = val;
	1042	+ }
	1043	+ if (abs(val - dev->cal.temp) > 30) {
	1044	+ mt76x0_phy_calibrate(dev, false);
	1045	+ dev->cal.temp = val;
	1046	+ }
	1047	+
	1048	+done:
	1049	+ mt76x0_rf_wr(dev, MT_RF(7, 73), rf_b7_73);
	1050	+ mt76x0_rf_wr(dev, MT_RF(0, 66), rf_b0_66);
	1051	+ mt76x0_rf_wr(dev, MT_RF(0, 67), rf_b0_67);
	1052	+}
	1053	+
	1054	+static void mt76x0_phy_set_gain_val(struct mt76x02_dev *dev)
	1055	+{
	1056	+ u8 gain = dev->cal.agc_gain_cur[0] - dev->cal.agc_gain_adjust;
	1057	+
	1058	+ mt76_rmw_field(dev, MT_BBP(AGC, 8), MT_BBP_AGC_GAIN, gain);
	1059	+
	1060	+ if ((dev->mphy.chandef.chan->flags & IEEE80211_CHAN_RADAR) &&
	1061	+ !is_mt7630(dev))
	1062	+ mt76x02_phy_dfs_adjust_agc(dev);
907	1063	}
908	1064
909	1065	static void
910		-mt76x0_set_rx_chains(struct mt76x0_dev *dev)
	1066	+mt76x0_phy_update_channel_gain(struct mt76x02_dev *dev)
911	1067	{
912		- u32 val;
	1068	+ bool gain_change;
	1069	+ u8 gain_delta;
	1070	+ int low_gain;
913	1071
914		- val = mt76_rr(dev, MT_BBP(AGC, 0));
915		- val &= ~(BIT(3) \| BIT(4));
	1072	+ dev->cal.avg_rssi_all = mt76_get_min_avg_rssi(&dev->mt76, false);
	1073	+ if (!dev->cal.avg_rssi_all)
	1074	+ dev->cal.avg_rssi_all = -75;
916	1075
917		- if (dev->chainmask & BIT(1))
918		- val \|= BIT(3);
	1076	+ low_gain = (dev->cal.avg_rssi_all > mt76x02_get_rssi_gain_thresh(dev)) +
	1077	+ (dev->cal.avg_rssi_all > mt76x02_get_low_rssi_gain_thresh(dev));
919	1078
920		- mt76_wr(dev, MT_BBP(AGC, 0), val);
	1079	+ gain_change = dev->cal.low_gain < 0 \|\|
	1080	+ (dev->cal.low_gain & 2) ^ (low_gain & 2);
	1081	+ dev->cal.low_gain = low_gain;
921	1082
922		- mb();
923		- val = mt76_rr(dev, MT_BBP(AGC, 0));
	1083	+ if (!gain_change) {
	1084	+ if (mt76x02_phy_adjust_vga_gain(dev))
	1085	+ mt76x0_phy_set_gain_val(dev);
	1086	+ return;
	1087	+ }
	1088	+
	1089	+ dev->cal.agc_gain_adjust = (low_gain == 2) ? 0 : 10;
	1090	+ gain_delta = (low_gain == 2) ? 10 : 0;
	1091	+
	1092	+ dev->cal.agc_gain_cur[0] = dev->cal.agc_gain_init[0] - gain_delta;
	1093	+ mt76x0_phy_set_gain_val(dev);
	1094	+
	1095	+ /* clear false CCA counters */
	1096	+ mt76_rr(dev, MT_RX_STAT_1);
924	1097	}
925	1098
926		-static void
927		-mt76x0_set_tx_dac(struct mt76x0_dev *dev)
	1099	+static void mt76x0_phy_calibration_work(struct work_struct *work)
928	1100	{
929		- if (dev->chainmask & BIT(1))
930		- mt76_set(dev, MT_BBP(TXBE, 5), 3);
	1101	+ struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev,
	1102	+ cal_work.work);
	1103	+
	1104	+ mt76x0_phy_update_channel_gain(dev);
	1105	+ if (mt76x0_tssi_enabled(dev))
	1106	+ mt76x0_phy_tssi_calibrate(dev);
931	1107	else
932		- mt76_clear(dev, MT_BBP(TXBE, 5), 3);
	1108	+ mt76x0_phy_temp_sensor(dev);
	1109	+
	1110	+ ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work,
	1111	+ 4 * MT_CALIBRATE_INTERVAL);
933	1112	}
934	1113
935		-static void
936		-mt76x0_rf_init(struct mt76x0_dev *dev)
	1114	+static void mt76x0_rf_patch_reg_array(struct mt76x02_dev *dev,
	1115	+ const struct mt76_reg_pair *rp, int len)
937	1116	{
938	1117	int i;
939		- u8 val;
940	1118
941		- RF_RANDOM_WRITE(dev, mt76x0_rf_central_tab);
942		- RF_RANDOM_WRITE(dev, mt76x0_rf_2g_channel_0_tab);
	1119	+ for (i = 0; i < len; i++) {
	1120	+ u32 reg = rp[i].reg;
	1121	+ u8 val = rp[i].value;
	1122	+
	1123	+ switch (reg) {
	1124	+ case MT_RF(0, 3):
	1125	+ if (mt76_is_mmio(&dev->mt76)) {
	1126	+ if (is_mt7630(dev))
	1127	+ val = 0x70;
	1128	+ else
	1129	+ val = 0x63;
	1130	+ } else {
	1131	+ val = 0x73;
	1132	+ }
	1133	+ break;
	1134	+ case MT_RF(0, 21):
	1135	+ if (is_mt7610e(dev))
	1136	+ val = 0x10;
	1137	+ else
	1138	+ val = 0x12;
	1139	+ break;
	1140	+ case MT_RF(5, 2):
	1141	+ if (is_mt7630(dev))
	1142	+ val = 0x1d;
	1143	+ else if (is_mt7610e(dev))
	1144	+ val = 0x00;
	1145	+ else
	1146	+ val = 0x0c;
	1147	+ break;
	1148	+ default:
	1149	+ break;
	1150	+ }
	1151	+ mt76x0_rf_wr(dev, reg, val);
	1152	+ }
	1153	+}
	1154	+
	1155	+static void mt76x0_phy_rf_init(struct mt76x02_dev *dev)
	1156	+{
	1157	+ int i;
	1158	+
	1159	+ mt76x0_rf_patch_reg_array(dev, mt76x0_rf_central_tab,
	1160	+ ARRAY_SIZE(mt76x0_rf_central_tab));
	1161	+ mt76x0_rf_patch_reg_array(dev, mt76x0_rf_2g_channel_0_tab,
	1162	+ ARRAY_SIZE(mt76x0_rf_2g_channel_0_tab));
943	1163	RF_RANDOM_WRITE(dev, mt76x0_rf_5g_channel_0_tab);
944	1164	RF_RANDOM_WRITE(dev, mt76x0_rf_vga_channel_0_tab);
945	1165
..	..	@@ -947,61 +1167,47 @@
947	1167	const struct mt76x0_rf_switch_item *item = &mt76x0_rf_bw_switch_tab[i];
948	1168
949	1169	if (item->bw_band == RF_BW_20)
950		- rf_wr(dev, item->rf_bank_reg, item->value);
951		- else if (((RF_G_BAND \| RF_BW_20) & item->bw_band) == (RF_G_BAND \| RF_BW_20))
952		- rf_wr(dev, item->rf_bank_reg, item->value);
	1170	+ mt76x0_rf_wr(dev, item->rf_bank_reg, item->value);
	1171	+ else if (((RF_G_BAND \| RF_BW_20) & item->bw_band) ==
	1172	+ (RF_G_BAND \| RF_BW_20))
	1173	+ mt76x0_rf_wr(dev, item->rf_bank_reg, item->value);
953	1174	}
954	1175
955	1176	for (i = 0; i < ARRAY_SIZE(mt76x0_rf_band_switch_tab); i++) {
956	1177	if (mt76x0_rf_band_switch_tab[i].bw_band & RF_G_BAND) {
957		- rf_wr(dev,
958		- mt76x0_rf_band_switch_tab[i].rf_bank_reg,
959		- mt76x0_rf_band_switch_tab[i].value);
	1178	+ mt76x0_rf_wr(dev,
	1179	+ mt76x0_rf_band_switch_tab[i].rf_bank_reg,
	1180	+ mt76x0_rf_band_switch_tab[i].value);
960	1181	}
961	1182	}
962	1183
963		- /*
964		- Frequency calibration
965		- E1: B0.R22<6:0>: xo_cxo<6:0>
966		- E2: B0.R21<0>: xo_cxo<0>, B0.R22<7:0>: xo_cxo<8:1>
	1184	+ /* Frequency calibration
	1185	+ * E1: B0.R22<6:0>: xo_cxo<6:0>
	1186	+ * E2: B0.R21<0>: xo_cxo<0>, B0.R22<7:0>: xo_cxo<8:1>
967	1187	*/
968		- rf_wr(dev, MT_RF(0, 22), min_t(u8, dev->ee->rf_freq_off, 0xBF));
969		- val = rf_rr(dev, MT_RF(0, 22));
	1188	+ mt76x0_rf_wr(dev, MT_RF(0, 22),
	1189	+ min_t(u8, dev->cal.rx.freq_offset, 0xbf));
	1190	+ mt76x0_rf_rr(dev, MT_RF(0, 22));
970	1191
971		- /*
972		- Reset the DAC (Set B0.R73<7>=1, then set B0.R73<7>=0, and then set B0.R73<7>) during power up.
	1192	+ /* Reset procedure DAC during power-up:
	1193	+ * - set B0.R73<7>
	1194	+ * - clear B0.R73<7>
	1195	+ * - set B0.R73<7>
973	1196	*/
974		- val = rf_rr(dev, MT_RF(0, 73));
975		- val \|= 0x80;
976		- rf_wr(dev, MT_RF(0, 73), val);
977		- val &= ~0x80;
978		- rf_wr(dev, MT_RF(0, 73), val);
979		- val \|= 0x80;
980		- rf_wr(dev, MT_RF(0, 73), val);
	1197	+ mt76x0_rf_set(dev, MT_RF(0, 73), BIT(7));
	1198	+ mt76x0_rf_clear(dev, MT_RF(0, 73), BIT(7));
	1199	+ mt76x0_rf_set(dev, MT_RF(0, 73), BIT(7));
981	1200
982		- /*
983		- vcocal_en (initiate VCO calibration (reset after completion)) - It should be at the end of RF configuration.
984		- */
985		- rf_set(dev, MT_RF(0, 4), 0x80);
	1201	+ /* vcocal_en: initiate VCO calibration (reset after completion)) */
	1202	+ mt76x0_rf_set(dev, MT_RF(0, 4), 0x80);
986	1203	}
987	1204
988		-static void mt76x0_ant_select(struct mt76x0_dev *dev)
	1205	+void mt76x0_phy_init(struct mt76x02_dev *dev)
989	1206	{
990		- /* Single antenna mode. */
991		- mt76_rmw(dev, MT_WLAN_FUN_CTRL, BIT(5), BIT(6));
992		- mt76_clear(dev, MT_CMB_CTRL, BIT(14) \| BIT(12));
993		- mt76_clear(dev, MT_COEXCFG0, BIT(2));
994		- mt76_rmw(dev, MT_COEXCFG3, BIT(5) \| BIT(4) \| BIT(3) \| BIT(2), BIT(1));
995		-}
	1207	+ INIT_DELAYED_WORK(&dev->cal_work, mt76x0_phy_calibration_work);
996	1208
997		-void mt76x0_phy_init(struct mt76x0_dev *dev)
998		-{
999		- INIT_DELAYED_WORK(&dev->cal_work, mt76x0_phy_calibrate);
1000		-
1001		- mt76x0_ant_select(dev);
1002		-
1003		- mt76x0_rf_init(dev);
1004		-
1005		- mt76x0_set_rx_chains(dev);
1006		- mt76x0_set_tx_dac(dev);
	1209	+ mt76x0_phy_ant_select(dev);
	1210	+ mt76x0_phy_rf_init(dev);
	1211	+ mt76x02_phy_set_rxpath(dev);
	1212	+ mt76x02_phy_set_txdac(dev);
1007	1213	}