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| 1 | +/* SPDX-License-Identifier: ISC */ |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> |
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| 3 | | - * |
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| 4 | | - * Permission to use, copy, modify, and/or distribute this software for any |
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| 5 | | - * purpose with or without fee is hereby granted, provided that the above |
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| 6 | | - * copyright notice and this permission notice appear in all copies. |
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| 7 | | - * |
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| 8 | | - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| 9 | | - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| 10 | | - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| 11 | | - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| 12 | | - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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| 13 | | - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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| 14 | | - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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| 15 | 4 | */ |
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| 16 | 5 | #ifndef __MT76_DMA_H |
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| 17 | 6 | #define __MT76_DMA_H |
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| 7 | + |
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| 8 | +#define DMA_DUMMY_DATA ((void *)~0) |
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| 18 | 9 | |
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| 19 | 10 | #define MT_RING_SIZE 0x10 |
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| 20 | 11 | |
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| .. | .. |
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| 24 | 15 | #define MT_DMA_CTL_SD_LEN0 GENMASK(29, 16) |
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| 25 | 16 | #define MT_DMA_CTL_LAST_SEC0 BIT(30) |
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| 26 | 17 | #define MT_DMA_CTL_DMA_DONE BIT(31) |
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| 27 | | - |
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| 28 | | -#define MT_TXD_INFO_LEN GENMASK(15, 0) |
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| 29 | | -#define MT_TXD_INFO_NEXT_VLD BIT(16) |
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| 30 | | -#define MT_TXD_INFO_TX_BURST BIT(17) |
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| 31 | | -#define MT_TXD_INFO_80211 BIT(19) |
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| 32 | | -#define MT_TXD_INFO_TSO BIT(20) |
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| 33 | | -#define MT_TXD_INFO_CSO BIT(21) |
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| 34 | | -#define MT_TXD_INFO_WIV BIT(24) |
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| 35 | | -#define MT_TXD_INFO_QSEL GENMASK(26, 25) |
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| 36 | | -#define MT_TXD_INFO_DPORT GENMASK(29, 27) |
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| 37 | | -#define MT_TXD_INFO_TYPE GENMASK(31, 30) |
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| 38 | | - |
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| 39 | | -#define MT_RX_FCE_INFO_LEN GENMASK(13, 0) |
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| 40 | | -#define MT_RX_FCE_INFO_SELF_GEN BIT(15) |
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| 41 | | -#define MT_RX_FCE_INFO_CMD_SEQ GENMASK(19, 16) |
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| 42 | | -#define MT_RX_FCE_INFO_EVT_TYPE GENMASK(23, 20) |
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| 43 | | -#define MT_RX_FCE_INFO_PCIE_INTR BIT(24) |
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| 44 | | -#define MT_RX_FCE_INFO_QSEL GENMASK(26, 25) |
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| 45 | | -#define MT_RX_FCE_INFO_D_PORT GENMASK(29, 27) |
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| 46 | | -#define MT_RX_FCE_INFO_TYPE GENMASK(31, 30) |
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| 47 | | - |
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| 48 | | -/* MCU request message header */ |
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| 49 | | -#define MT_MCU_MSG_LEN GENMASK(15, 0) |
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| 50 | | -#define MT_MCU_MSG_CMD_SEQ GENMASK(19, 16) |
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| 51 | | -#define MT_MCU_MSG_CMD_TYPE GENMASK(26, 20) |
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| 52 | | -#define MT_MCU_MSG_PORT GENMASK(29, 27) |
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| 53 | | -#define MT_MCU_MSG_TYPE GENMASK(31, 30) |
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| 54 | | -#define MT_MCU_MSG_TYPE_CMD BIT(30) |
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| 55 | 18 | |
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| 56 | 19 | #define MT_DMA_HDR_LEN 4 |
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| 57 | 20 | #define MT_RX_INFO_LEN 4 |
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| .. | .. |
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| 65 | 28 | __le32 info; |
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| 66 | 29 | } __packed __aligned(4); |
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| 67 | 30 | |
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| 68 | | -enum dma_msg_port { |
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| 69 | | - WLAN_PORT, |
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| 70 | | - CPU_RX_PORT, |
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| 71 | | - CPU_TX_PORT, |
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| 72 | | - HOST_PORT, |
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| 73 | | - VIRTUAL_CPU_RX_PORT, |
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| 74 | | - VIRTUAL_CPU_TX_PORT, |
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| 75 | | - DISCARD, |
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| 31 | +enum mt76_qsel { |
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| 32 | + MT_QSEL_MGMT, |
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| 33 | + MT_QSEL_HCCA, |
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| 34 | + MT_QSEL_EDCA, |
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| 35 | + MT_QSEL_EDCA_2, |
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| 76 | 36 | }; |
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| 77 | 37 | |
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| 78 | | -int mt76_dma_attach(struct mt76_dev *dev); |
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| 38 | +enum mt76_mcu_evt_type { |
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| 39 | + EVT_CMD_DONE, |
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| 40 | + EVT_CMD_ERROR, |
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| 41 | + EVT_CMD_RETRY, |
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| 42 | + EVT_EVENT_PWR_RSP, |
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| 43 | + EVT_EVENT_WOW_RSP, |
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| 44 | + EVT_EVENT_CARRIER_DETECT_RSP, |
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| 45 | + EVT_EVENT_DFS_DETECT_RSP, |
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| 46 | +}; |
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| 47 | + |
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| 48 | +void mt76_dma_attach(struct mt76_dev *dev); |
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| 79 | 49 | void mt76_dma_cleanup(struct mt76_dev *dev); |
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| 80 | 50 | |
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| 81 | 51 | #endif |
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