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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/net/wireless/marvell/mwifiex/pcie.h
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@@ -3,10 +3,10 @@
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  * @brief This file contains definitions for PCI-E interface.
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  * driver.
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  *
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- * Copyright (C) 2011-2014, Marvell International Ltd.
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+ * Copyright 2011-2020 NXP
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  *
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- * This software file (the "File") is distributed by Marvell International
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- * Ltd. under the terms of the GNU General Public License Version 2, June 1991
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+ * This software file (the "File") is distributed by NXP
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+ * under the terms of the GNU General Public License Version 2, June 1991
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  * (the "License").  You may use, redistribute and/or modify this File in
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  * accordance with the terms and conditions of the License, a copy of which
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  * is available by writing to the Free Software Foundation, Inc.,
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@@ -158,127 +158,6 @@
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 	u8 msix_support;
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 };
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-static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
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-	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
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-	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
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-	.cmd_size = PCIE_SCRATCH_2_REG,
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-	.fw_status = PCIE_SCRATCH_3_REG,
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-	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
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-	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
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-	.tx_rdptr = PCIE_SCRATCH_6_REG,
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-	.tx_wrptr = PCIE_SCRATCH_7_REG,
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-	.rx_rdptr = PCIE_SCRATCH_8_REG,
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-	.rx_wrptr = PCIE_SCRATCH_9_REG,
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-	.evt_rdptr = PCIE_SCRATCH_10_REG,
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-	.evt_wrptr = PCIE_SCRATCH_11_REG,
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-	.drv_rdy = PCIE_SCRATCH_12_REG,
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-	.tx_start_ptr = 0,
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-	.tx_mask = MWIFIEX_TXBD_MASK,
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-	.tx_wrap_mask = 0,
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-	.rx_mask = MWIFIEX_RXBD_MASK,
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-	.rx_wrap_mask = 0,
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-	.tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
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-	.rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
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-	.evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
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-	.ring_flag_sop = 0,
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-	.ring_flag_eop = 0,
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-	.ring_flag_xs_sop = 0,
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-	.ring_flag_xs_eop = 0,
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-	.ring_tx_start_ptr = 0,
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-	.pfu_enabled = 0,
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-	.sleep_cookie = 1,
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-	.msix_support = 0,
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-};
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-
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-static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
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-	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
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-	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
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-	.cmd_size = PCIE_SCRATCH_2_REG,
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-	.fw_status = PCIE_SCRATCH_3_REG,
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-	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
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-	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
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-	.tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
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-	.tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
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-	.rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
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-	.rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
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-	.evt_rdptr = PCIE_SCRATCH_10_REG,
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-	.evt_wrptr = PCIE_SCRATCH_11_REG,
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-	.drv_rdy = PCIE_SCRATCH_12_REG,
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-	.tx_start_ptr = 16,
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-	.tx_mask = 0x03FF0000,
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-	.tx_wrap_mask = 0x07FF0000,
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-	.rx_mask = 0x000003FF,
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-	.rx_wrap_mask = 0x000007FF,
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-	.tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
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-	.rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
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-	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
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-	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
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-	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
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-	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
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-	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
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-	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
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-	.pfu_enabled = 1,
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-	.sleep_cookie = 0,
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-	.fw_dump_ctrl = PCIE_SCRATCH_13_REG,
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-	.fw_dump_start = PCIE_SCRATCH_14_REG,
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-	.fw_dump_end = 0xcff,
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-	.fw_dump_host_ready = 0xee,
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-	.fw_dump_read_done = 0xfe,
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-	.msix_support = 0,
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-};
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-
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-static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
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-	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
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-	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
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-	.cmd_size = PCIE_SCRATCH_2_REG,
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-	.fw_status = PCIE_SCRATCH_3_REG,
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-	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
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-	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
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-	.tx_rdptr = 0xC1A4,
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-	.tx_wrptr = 0xC174,
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-	.rx_rdptr = 0xC174,
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-	.rx_wrptr = 0xC1A4,
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-	.evt_rdptr = PCIE_SCRATCH_10_REG,
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-	.evt_wrptr = PCIE_SCRATCH_11_REG,
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-	.drv_rdy = PCIE_SCRATCH_12_REG,
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-	.tx_start_ptr = 16,
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-	.tx_mask = 0x0FFF0000,
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-	.tx_wrap_mask = 0x1FFF0000,
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-	.rx_mask = 0x00000FFF,
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-	.rx_wrap_mask = 0x00001FFF,
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-	.tx_rollover_ind = BIT(28),
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-	.rx_rollover_ind = BIT(12),
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-	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
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-	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
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-	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
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-	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
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-	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
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-	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
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-	.pfu_enabled = 1,
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-	.sleep_cookie = 0,
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-	.fw_dump_ctrl = PCIE_SCRATCH_13_REG,
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-	.fw_dump_start = PCIE_SCRATCH_14_REG,
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-	.fw_dump_end = 0xcff,
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-	.fw_dump_host_ready = 0xcc,
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-	.fw_dump_read_done = 0xdd,
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-	.msix_support = 0,
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-};
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-
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-static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
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-	{"ITCM", NULL, 0, 0xF0},
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-	{"DTCM", NULL, 0, 0xF1},
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-	{"SQRAM", NULL, 0, 0xF2},
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-	{"IRAM", NULL, 0, 0xF3},
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-	{"APU", NULL, 0, 0xF4},
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-	{"CIU", NULL, 0, 0xF5},
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-	{"ICU", NULL, 0, 0xF6},
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-	{"MAC", NULL, 0, 0xF7},
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-};
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-
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-static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
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-	{"DUMP", NULL, 0, 0xDD},
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-};
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-
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 struct mwifiex_pcie_device {
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 	const struct mwifiex_pcie_card_reg *reg;
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 	u16 blksz_fw_dl;
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@@ -287,34 +166,6 @@
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 	struct memory_type_mapping *mem_type_mapping_tbl;
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 	u8 num_mem_types;
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 	bool can_ext_scan;
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-};
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-
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-static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
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-	.reg            = &mwifiex_reg_8766,
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-	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
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-	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
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-	.can_dump_fw = false,
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-	.can_ext_scan = true,
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-};
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-
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-static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
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-	.reg            = &mwifiex_reg_8897,
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-	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
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-	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
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-	.can_dump_fw = true,
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-	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
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-	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
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-	.can_ext_scan = true,
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-};
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-
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-static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
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-	.reg            = &mwifiex_reg_8997,
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-	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
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-	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
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-	.can_dump_fw = true,
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-	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
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-	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
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-	.can_ext_scan = true,
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 };
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 struct mwifiex_evt_buf_desc {