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6 | 6 | * GPL LICENSE SUMMARY |
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7 | 7 | * |
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8 | 8 | * Copyright(c) 2017 Intel Deutschland GmbH |
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| 9 | + * Copyright(c) 2019 - 2020 Intel Corporation |
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9 | 10 | * |
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10 | 11 | * This program is free software; you can redistribute it and/or modify |
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11 | 12 | * it under the terms of version 2 of the GNU General Public License as |
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.. | .. |
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26 | 27 | * BSD LICENSE |
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27 | 28 | * |
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28 | 29 | * Copyright(c) 2017 Intel Deutschland GmbH |
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| 30 | + * Copyright(c) 2019 - 2020 Intel Corporation |
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29 | 31 | * All rights reserved. |
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30 | 32 | * |
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31 | 33 | * Redistribution and use in source and binary forms, with or without |
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60 | 62 | #include "dbg.h" |
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61 | 63 | #include "debugfs.h" |
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62 | 64 | |
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| 65 | +#include "fw/api/soc.h" |
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| 66 | +#include "fw/api/commands.h" |
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| 67 | + |
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63 | 68 | void iwl_fw_runtime_init(struct iwl_fw_runtime *fwrt, struct iwl_trans *trans, |
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64 | 69 | const struct iwl_fw *fw, |
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65 | 70 | const struct iwl_fw_runtime_ops *ops, void *ops_ctx, |
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66 | 71 | struct dentry *dbgfs_dir) |
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67 | 72 | { |
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| 73 | + int i; |
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| 74 | + |
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68 | 75 | memset(fwrt, 0, sizeof(*fwrt)); |
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69 | 76 | fwrt->trans = trans; |
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70 | 77 | fwrt->fw = fw; |
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.. | .. |
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72 | 79 | fwrt->dump.conf = FW_DBG_INVALID; |
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73 | 80 | fwrt->ops = ops; |
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74 | 81 | fwrt->ops_ctx = ops_ctx; |
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75 | | - INIT_DELAYED_WORK(&fwrt->dump.wk, iwl_fw_error_dump_wk); |
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| 82 | + for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) { |
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| 83 | + fwrt->dump.wks[i].idx = i; |
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| 84 | + INIT_DELAYED_WORK(&fwrt->dump.wks[i].wk, iwl_fw_error_dump_wk); |
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| 85 | + } |
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76 | 86 | iwl_fwrt_dbgfs_register(fwrt, dbgfs_dir); |
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77 | 87 | } |
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78 | 88 | IWL_EXPORT_SYMBOL(iwl_fw_runtime_init); |
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.. | .. |
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88 | 98 | iwl_fw_resume_timestamp(fwrt); |
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89 | 99 | } |
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90 | 100 | IWL_EXPORT_SYMBOL(iwl_fw_runtime_resume); |
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| 101 | + |
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| 102 | +/* set device type and latency */ |
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| 103 | +int iwl_set_soc_latency(struct iwl_fw_runtime *fwrt) |
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| 104 | +{ |
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| 105 | + struct iwl_soc_configuration_cmd cmd = {}; |
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| 106 | + struct iwl_host_cmd hcmd = { |
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| 107 | + .id = iwl_cmd_id(SOC_CONFIGURATION_CMD, SYSTEM_GROUP, 0), |
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| 108 | + .data[0] = &cmd, |
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| 109 | + .len[0] = sizeof(cmd), |
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| 110 | + }; |
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| 111 | + int ret; |
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| 112 | + |
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| 113 | + /* |
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| 114 | + * In VER_1 of this command, the discrete value is considered |
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| 115 | + * an integer; In VER_2, it's a bitmask. Since we have only 2 |
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| 116 | + * values in VER_1, this is backwards-compatible with VER_2, |
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| 117 | + * as long as we don't set any other bits. |
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| 118 | + */ |
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| 119 | + if (!fwrt->trans->trans_cfg->integrated) |
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| 120 | + cmd.flags = cpu_to_le32(SOC_CONFIG_CMD_FLAGS_DISCRETE); |
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| 121 | + |
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| 122 | + BUILD_BUG_ON(IWL_CFG_TRANS_LTR_DELAY_NONE != |
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| 123 | + SOC_FLAGS_LTR_APPLY_DELAY_NONE); |
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| 124 | + BUILD_BUG_ON(IWL_CFG_TRANS_LTR_DELAY_200US != |
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| 125 | + SOC_FLAGS_LTR_APPLY_DELAY_200); |
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| 126 | + BUILD_BUG_ON(IWL_CFG_TRANS_LTR_DELAY_2500US != |
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| 127 | + SOC_FLAGS_LTR_APPLY_DELAY_2500); |
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| 128 | + BUILD_BUG_ON(IWL_CFG_TRANS_LTR_DELAY_1820US != |
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| 129 | + SOC_FLAGS_LTR_APPLY_DELAY_1820); |
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| 130 | + |
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| 131 | + if (fwrt->trans->trans_cfg->ltr_delay != IWL_CFG_TRANS_LTR_DELAY_NONE && |
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| 132 | + !WARN_ON(!fwrt->trans->trans_cfg->integrated)) |
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| 133 | + cmd.flags |= le32_encode_bits(fwrt->trans->trans_cfg->ltr_delay, |
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| 134 | + SOC_FLAGS_LTR_APPLY_DELAY_MASK); |
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| 135 | + |
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| 136 | + if (iwl_fw_lookup_cmd_ver(fwrt->fw, IWL_ALWAYS_LONG_GROUP, |
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| 137 | + SCAN_REQ_UMAC, |
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| 138 | + IWL_FW_CMD_VER_UNKNOWN) >= 2 && |
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| 139 | + fwrt->trans->trans_cfg->low_latency_xtal) |
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| 140 | + cmd.flags |= cpu_to_le32(SOC_CONFIG_CMD_FLAGS_LOW_LATENCY); |
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| 141 | + |
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| 142 | + cmd.latency = cpu_to_le32(fwrt->trans->trans_cfg->xtal_latency); |
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| 143 | + |
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| 144 | + ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); |
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| 145 | + if (ret) |
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| 146 | + IWL_ERR(fwrt, "Failed to set soc latency: %d\n", ret); |
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| 147 | + return ret; |
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| 148 | +} |
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| 149 | +IWL_EXPORT_SYMBOL(iwl_set_soc_latency); |
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