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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/net/phy/microchip.c
....@@ -1,18 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0+
12 /*
23  * Copyright (C) 2015 Microchip Technology
3
- *
4
- * This program is free software; you can redistribute it and/or
5
- * modify it under the terms of the GNU General Public License
6
- * as published by the Free Software Foundation; either version 2
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- * of the License, or (at your option) any later version.
8
- *
9
- * This program is distributed in the hope that it will be useful,
10
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
- * GNU General Public License for more details.
13
- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, see <http://www.gnu.org/licenses/>.
164  */
175 #include <linux/kernel.h>
186 #include <linux/module.h>
....@@ -88,7 +76,7 @@
8876 	/* Save current page */
8977 	save_page = phy_save_page(phydev);
9078 	if (save_page < 0) {
91
-		pr_warn("Failed to get current page\n");
79
+		phydev_warn(phydev, "Failed to get current page\n");
9280 		goto err;
9381 	}
9482 
....@@ -98,14 +86,14 @@
9886 	ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
9987 			  (data & 0xFFFF));
10088 	if (ret < 0) {
101
-		pr_warn("Failed to write TR low data\n");
89
+		phydev_warn(phydev, "Failed to write TR low data\n");
10290 		goto err;
10391 	}
10492 
10593 	ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
10694 			  (data & 0x00FF0000) >> 16);
10795 	if (ret < 0) {
108
-		pr_warn("Failed to write TR high data\n");
96
+		phydev_warn(phydev, "Failed to write TR high data\n");
10997 		goto err;
11098 	}
11199 
....@@ -115,14 +103,15 @@
115103 
116104 	ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
117105 	if (ret < 0) {
118
-		pr_warn("Failed to write data in reg\n");
106
+		phydev_warn(phydev, "Failed to write data in reg\n");
119107 		goto err;
120108 	}
121109 
122110 	usleep_range(1000, 2000);/* Wait for Data to be written */
123111 	val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
124112 	if (!(val & 0x8000))
125
-		pr_warn("TR Register[0x%X] configuration failed\n", regaddr);
113
+		phydev_warn(phydev, "TR Register[0x%X] configuration failed\n",
114
+			    regaddr);
126115 err:
127116 	return phy_restore_page(phydev, save_page, ret);
128117 }
....@@ -137,7 +126,7 @@
137126 	 */
138127 	err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
139128 	if (err < 0)
140
-		pr_warn("Failed to Set Register[0x0F82]\n");
129
+		phydev_warn(phydev, "Failed to Set Register[0x0F82]\n");
141130 
142131 	/* Get access to Channel b'10, Node b'1101, Register 0x06.
143132 	 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv,
....@@ -145,7 +134,7 @@
145134 	 */
146135 	err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
147136 	if (err < 0)
148
-		pr_warn("Failed to Set Register[0x168C]\n");
137
+		phydev_warn(phydev, "Failed to Set Register[0x168C]\n");
149138 
150139 	/* Get access to Channel b'10, Node b'1111, Register 0x11.
151140 	 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh
....@@ -153,7 +142,7 @@
153142 	 */
154143 	err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
155144 	if (err < 0)
156
-		pr_warn("Failed to Set Register[0x17A2]\n");
145
+		phydev_warn(phydev, "Failed to Set Register[0x17A2]\n");
157146 
158147 	/* Get access to Channel b'10, Node b'1101, Register 0x10.
159148 	 * Write 24-bit value 0xEEFFDD to register. Setting
....@@ -162,7 +151,7 @@
162151 	 */
163152 	err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
164153 	if (err < 0)
165
-		pr_warn("Failed to Set Register[0x16A0]\n");
154
+		phydev_warn(phydev, "Failed to Set Register[0x16A0]\n");
166155 
167156 	/* Get access to Channel b'10, Node b'1101, Register 0x13.
168157 	 * Write 24-bit value 0x071448 to register. Setting
....@@ -170,7 +159,7 @@
170159 	 */
171160 	err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
172161 	if (err < 0)
173
-		pr_warn("Failed to Set Register[0x16A6]\n");
162
+		phydev_warn(phydev, "Failed to Set Register[0x16A6]\n");
174163 
175164 	/* Get access to Channel b'10, Node b'1101, Register 0x12.
176165 	 * Write 24-bit value 0x13132F to register. Setting
....@@ -178,7 +167,7 @@
178167 	 */
179168 	err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
180169 	if (err < 0)
181
-		pr_warn("Failed to Set Register[0x16A4]\n");
170
+		phydev_warn(phydev, "Failed to Set Register[0x16A4]\n");
182171 
183172 	/* Get access to Channel b'10, Node b'1101, Register 0x14.
184173 	 * Write 24-bit value 0x0 to register. Setting eee_3level_delay,
....@@ -186,7 +175,7 @@
186175 	 */
187176 	err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
188177 	if (err < 0)
189
-		pr_warn("Failed to Set Register[0x16A8]\n");
178
+		phydev_warn(phydev, "Failed to Set Register[0x16A8]\n");
190179 
191180 	/* Get access to Channel b'01, Node b'1111, Register 0x34.
192181 	 * Write 24-bit value 0x91B06C to register. Setting
....@@ -195,7 +184,7 @@
195184 	 */
196185 	err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
197186 	if (err < 0)
198
-		pr_warn("Failed to Set Register[0x0FE8]\n");
187
+		phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n");
199188 
200189 	/* Get access to Channel b'01, Node b'1111, Register 0x3E.
201190 	 * Write 24-bit value 0xC0A028 to register. Setting
....@@ -204,7 +193,7 @@
204193 	 */
205194 	err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
206195 	if (err < 0)
207
-		pr_warn("Failed to Set Register[0x0FFC]\n");
196
+		phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n");
208197 
209198 	/* Get access to Channel b'01, Node b'1111, Register 0x35.
210199 	 * Write 24-bit value 0x041600 to register. Setting
....@@ -213,14 +202,14 @@
213202 	 */
214203 	err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
215204 	if (err < 0)
216
-		pr_warn("Failed to Set Register[0x0FEA]\n");
205
+		phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n");
217206 
218207 	/* Get access to Channel b'10, Node b'1101, Register 0x03.
219208 	 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits.
220209 	 */
221210 	err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
222211 	if (err < 0)
223
-		pr_warn("Failed to Set Register[0x1686]\n");
212
+		phydev_warn(phydev, "Failed to Set Register[0x1686]\n");
224213 }
225214 
226215 static int lan88xx_probe(struct phy_device *phydev)
....@@ -316,7 +305,6 @@
316305 {
317306 	int val;
318307 
319
-	genphy_config_init(phydev);
320308 	/*Zerodetect delay enable */
321309 	val = phy_read_mmd(phydev, MDIO_MMD_PCS,
322310 			   PHY_ARDENNES_MMD_DEV_3_PHY_CFG);
....@@ -344,8 +332,7 @@
344332 	.phy_id_mask	= 0xfffffff0,
345333 	.name		= "Microchip LAN88xx",
346334 
347
-	.features	= PHY_GBIT_FEATURES,
348
-	.flags		= PHY_HAS_INTERRUPT,
335
+	/* PHY_GBIT_FEATURES */
349336 
350337 	.probe		= lan88xx_probe,
351338 	.remove		= lan88xx_remove,