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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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1 | 2 | /**************************************************************************** |
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2 | 3 | * Driver for Solarflare network controllers and boards |
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3 | 4 | * Copyright 2005-2006 Fen Systems Ltd. |
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4 | 5 | * Copyright 2006-2013 Solarflare Communications Inc. |
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5 | | - * |
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6 | | - * This program is free software; you can redistribute it and/or modify it |
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7 | | - * under the terms of the GNU General Public License version 2 as published |
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8 | | - * by the Free Software Foundation, incorporated herein by reference. |
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9 | 6 | */ |
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10 | 7 | |
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11 | 8 | #ifndef EFX_NIC_H |
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12 | 9 | #define EFX_NIC_H |
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13 | 10 | |
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14 | | -#include <linux/net_tstamp.h> |
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15 | | -#include <linux/i2c-algo-bit.h> |
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16 | | -#include "net_driver.h" |
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| 11 | +#include "nic_common.h" |
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17 | 12 | #include "efx.h" |
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18 | | -#include "mcdi.h" |
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19 | | - |
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20 | | -enum { |
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21 | | - /* Revisions 0-2 were Falcon A0, A1 and B0 respectively. |
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22 | | - * They are not supported by this driver but these revision numbers |
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23 | | - * form part of the ethtool API for register dumping. |
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24 | | - */ |
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25 | | - EFX_REV_SIENA_A0 = 3, |
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26 | | - EFX_REV_HUNT_A0 = 4, |
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27 | | -}; |
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28 | | - |
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29 | | -static inline int efx_nic_rev(struct efx_nic *efx) |
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30 | | -{ |
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31 | | - return efx->type->revision; |
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32 | | -} |
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33 | 13 | |
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34 | 14 | u32 efx_farch_fpga_ver(struct efx_nic *efx); |
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35 | | - |
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36 | | -/* Read the current event from the event queue */ |
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37 | | -static inline efx_qword_t *efx_event(struct efx_channel *channel, |
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38 | | - unsigned int index) |
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39 | | -{ |
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40 | | - return ((efx_qword_t *) (channel->eventq.buf.addr)) + |
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41 | | - (index & channel->eventq_mask); |
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42 | | -} |
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43 | | - |
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44 | | -/* See if an event is present |
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45 | | - * |
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46 | | - * We check both the high and low dword of the event for all ones. We |
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47 | | - * wrote all ones when we cleared the event, and no valid event can |
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48 | | - * have all ones in either its high or low dwords. This approach is |
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49 | | - * robust against reordering. |
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50 | | - * |
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51 | | - * Note that using a single 64-bit comparison is incorrect; even |
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52 | | - * though the CPU read will be atomic, the DMA write may not be. |
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53 | | - */ |
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54 | | -static inline int efx_event_present(efx_qword_t *event) |
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55 | | -{ |
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56 | | - return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | |
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57 | | - EFX_DWORD_IS_ALL_ONES(event->dword[1])); |
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58 | | -} |
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59 | | - |
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60 | | -/* Returns a pointer to the specified transmit descriptor in the TX |
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61 | | - * descriptor queue belonging to the specified channel. |
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62 | | - */ |
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63 | | -static inline efx_qword_t * |
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64 | | -efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index) |
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65 | | -{ |
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66 | | - return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index; |
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67 | | -} |
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68 | | - |
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69 | | -/* Get partner of a TX queue, seen as part of the same net core queue */ |
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70 | | -static struct efx_tx_queue *efx_tx_queue_partner(struct efx_tx_queue *tx_queue) |
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71 | | -{ |
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72 | | - if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) |
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73 | | - return tx_queue - EFX_TXQ_TYPE_OFFLOAD; |
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74 | | - else |
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75 | | - return tx_queue + EFX_TXQ_TYPE_OFFLOAD; |
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76 | | -} |
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77 | | - |
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78 | | -/* Report whether this TX queue would be empty for the given write_count. |
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79 | | - * May return false negative. |
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80 | | - */ |
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81 | | -static inline bool __efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue, |
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82 | | - unsigned int write_count) |
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83 | | -{ |
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84 | | - unsigned int empty_read_count = READ_ONCE(tx_queue->empty_read_count); |
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85 | | - |
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86 | | - if (empty_read_count == 0) |
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87 | | - return false; |
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88 | | - |
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89 | | - return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0; |
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90 | | -} |
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91 | | - |
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92 | | -/* Report whether the NIC considers this TX queue empty, using |
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93 | | - * packet_write_count (the write count recorded for the last completable |
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94 | | - * doorbell push). May return false negative. EF10 only, which is OK |
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95 | | - * because only EF10 supports PIO. |
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96 | | - */ |
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97 | | -static inline bool efx_nic_tx_is_empty(struct efx_tx_queue *tx_queue) |
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98 | | -{ |
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99 | | - EFX_WARN_ON_ONCE_PARANOID(!tx_queue->efx->type->option_descriptors); |
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100 | | - return __efx_nic_tx_is_empty(tx_queue, tx_queue->packet_write_count); |
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101 | | -} |
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102 | | - |
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103 | | -/* Decide whether we can use TX PIO, ie. write packet data directly into |
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104 | | - * a buffer on the device. This can reduce latency at the expense of |
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105 | | - * throughput, so we only do this if both hardware and software TX rings |
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106 | | - * are empty. This also ensures that only one packet at a time can be |
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107 | | - * using the PIO buffer. |
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108 | | - */ |
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109 | | -static inline bool efx_nic_may_tx_pio(struct efx_tx_queue *tx_queue) |
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110 | | -{ |
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111 | | - struct efx_tx_queue *partner = efx_tx_queue_partner(tx_queue); |
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112 | | - |
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113 | | - return tx_queue->piobuf && efx_nic_tx_is_empty(tx_queue) && |
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114 | | - efx_nic_tx_is_empty(partner); |
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115 | | -} |
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116 | | - |
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117 | | -/* Decide whether to push a TX descriptor to the NIC vs merely writing |
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118 | | - * the doorbell. This can reduce latency when we are adding a single |
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119 | | - * descriptor to an empty queue, but is otherwise pointless. Further, |
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120 | | - * Falcon and Siena have hardware bugs (SF bug 33851) that may be |
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121 | | - * triggered if we don't check this. |
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122 | | - * We use the write_count used for the last doorbell push, to get the |
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123 | | - * NIC's view of the tx queue. |
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124 | | - */ |
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125 | | -static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue, |
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126 | | - unsigned int write_count) |
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127 | | -{ |
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128 | | - bool was_empty = __efx_nic_tx_is_empty(tx_queue, write_count); |
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129 | | - |
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130 | | - tx_queue->empty_read_count = 0; |
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131 | | - return was_empty && tx_queue->write_count - write_count == 1; |
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132 | | -} |
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133 | | - |
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134 | | -/* Returns a pointer to the specified descriptor in the RX descriptor queue */ |
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135 | | -static inline efx_qword_t * |
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136 | | -efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) |
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137 | | -{ |
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138 | | - return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index; |
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139 | | -} |
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140 | 15 | |
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141 | 16 | enum { |
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142 | 17 | PHY_TYPE_NONE = 0, |
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.. | .. |
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148 | 23 | PHY_TYPE_SFT9001A = 8, |
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149 | 24 | PHY_TYPE_QT2025C = 9, |
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150 | 25 | PHY_TYPE_SFT9001B = 10, |
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151 | | -}; |
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152 | | - |
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153 | | -/* Alignment of PCIe DMA boundaries (4KB) */ |
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154 | | -#define EFX_PAGE_SIZE 4096 |
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155 | | -/* Size and alignment of buffer table entries (same) */ |
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156 | | -#define EFX_BUF_SIZE EFX_PAGE_SIZE |
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157 | | - |
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158 | | -/* NIC-generic software stats */ |
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159 | | -enum { |
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160 | | - GENERIC_STAT_rx_noskb_drops, |
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161 | | - GENERIC_STAT_rx_nodesc_trunc, |
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162 | | - GENERIC_STAT_COUNT |
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163 | 26 | }; |
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164 | 27 | |
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165 | 28 | enum { |
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.. | .. |
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363 | 226 | * @warm_boot_count: Last seen MC warm boot count |
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364 | 227 | * @vi_base: Absolute index of first VI in this function |
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365 | 228 | * @n_allocated_vis: Number of VIs allocated to this function |
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366 | | - * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot |
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367 | | - * @must_restore_rss_contexts: Flag: RSS contexts have yet to be restored after |
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368 | | - * MC reboot |
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369 | | - * @must_restore_filters: Flag: filters have yet to be restored after MC reboot |
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370 | 229 | * @n_piobufs: Number of PIO buffers allocated to this function |
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371 | 230 | * @wc_membase: Base address of write-combining mapping of the memory BAR |
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372 | 231 | * @pio_write_base: Base address for writing PIO buffers |
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.. | .. |
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375 | 234 | * @piobuf_size: size of a single PIO buffer |
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376 | 235 | * @must_restore_piobufs: Flag: PIO buffers have yet to be restored after MC |
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377 | 236 | * reboot |
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378 | | - * @rx_rss_context_exclusive: Whether our RSS context is exclusive or shared |
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| 237 | + * @mc_stats: Scratch buffer for converting statistics to the kernel's format |
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379 | 238 | * @stats: Hardware statistics |
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380 | 239 | * @workaround_35388: Flag: firmware supports workaround for bug 35388 |
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381 | 240 | * @workaround_26807: Flag: firmware supports workaround for bug 26807 |
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.. | .. |
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388 | 247 | * %MC_CMD_GET_CAPABILITIES response) |
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389 | 248 | * @rx_dpcpu_fw_id: Firmware ID of the RxDPCPU |
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390 | 249 | * @tx_dpcpu_fw_id: Firmware ID of the TxDPCPU |
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391 | | - * @vport_id: The function's vport ID, only relevant for PFs |
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392 | 250 | * @must_probe_vswitching: Flag: vswitching has yet to be setup after MC reboot |
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393 | 251 | * @pf_index: The number for this PF, or the parent PF if this is a VF |
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394 | 252 | #ifdef CONFIG_SFC_SRIOV |
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.. | .. |
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407 | 265 | u16 warm_boot_count; |
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408 | 266 | unsigned int vi_base; |
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409 | 267 | unsigned int n_allocated_vis; |
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410 | | - bool must_realloc_vis; |
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411 | | - bool must_restore_rss_contexts; |
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412 | | - bool must_restore_filters; |
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413 | 268 | unsigned int n_piobufs; |
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414 | 269 | void __iomem *wc_membase, *pio_write_base; |
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415 | 270 | unsigned int pio_write_vi_base; |
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416 | 271 | unsigned int piobuf_handle[EF10_TX_PIOBUF_COUNT]; |
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417 | 272 | u16 piobuf_size; |
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418 | 273 | bool must_restore_piobufs; |
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419 | | - bool rx_rss_context_exclusive; |
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| 274 | + __le64 *mc_stats; |
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420 | 275 | u64 stats[EF10_STAT_COUNT]; |
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421 | 276 | bool workaround_35388; |
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422 | 277 | bool workaround_26807; |
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.. | .. |
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426 | 281 | u32 datapath_caps2; |
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427 | 282 | unsigned int rx_dpcpu_fw_id; |
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428 | 283 | unsigned int tx_dpcpu_fw_id; |
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429 | | - unsigned int vport_id; |
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430 | 284 | bool must_probe_vswitching; |
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431 | 285 | unsigned int pf_index; |
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432 | 286 | u8 port_id[ETH_ALEN]; |
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.. | .. |
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443 | 297 | u64 licensed_features; |
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444 | 298 | }; |
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445 | 299 | |
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| 300 | +/* TSOv2 */ |
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| 301 | +int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb, |
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| 302 | + bool *data_mapped); |
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| 303 | + |
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446 | 304 | int efx_init_sriov(void); |
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447 | 305 | void efx_fini_sriov(void); |
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448 | 306 | |
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449 | | -struct ethtool_ts_info; |
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450 | | -int efx_ptp_probe(struct efx_nic *efx, struct efx_channel *channel); |
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451 | | -void efx_ptp_defer_probe_with_channel(struct efx_nic *efx); |
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452 | | -struct efx_channel *efx_ptp_channel(struct efx_nic *efx); |
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453 | | -void efx_ptp_remove(struct efx_nic *efx); |
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454 | | -int efx_ptp_set_ts_config(struct efx_nic *efx, struct ifreq *ifr); |
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455 | | -int efx_ptp_get_ts_config(struct efx_nic *efx, struct ifreq *ifr); |
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456 | | -void efx_ptp_get_ts_info(struct efx_nic *efx, struct ethtool_ts_info *ts_info); |
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457 | | -bool efx_ptp_is_ptp_tx(struct efx_nic *efx, struct sk_buff *skb); |
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458 | | -int efx_ptp_get_mode(struct efx_nic *efx); |
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459 | | -int efx_ptp_change_mode(struct efx_nic *efx, bool enable_wanted, |
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460 | | - unsigned int new_mode); |
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461 | | -int efx_ptp_tx(struct efx_nic *efx, struct sk_buff *skb); |
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462 | | -void efx_ptp_event(struct efx_nic *efx, efx_qword_t *ev); |
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463 | | -size_t efx_ptp_describe_stats(struct efx_nic *efx, u8 *strings); |
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464 | | -size_t efx_ptp_update_stats(struct efx_nic *efx, u64 *stats); |
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465 | | -void efx_time_sync_event(struct efx_channel *channel, efx_qword_t *ev); |
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466 | | -void __efx_rx_skb_attach_timestamp(struct efx_channel *channel, |
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467 | | - struct sk_buff *skb); |
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468 | | -static inline void efx_rx_skb_attach_timestamp(struct efx_channel *channel, |
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469 | | - struct sk_buff *skb) |
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470 | | -{ |
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471 | | - if (channel->sync_events_state == SYNC_EVENTS_VALID) |
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472 | | - __efx_rx_skb_attach_timestamp(channel, skb); |
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473 | | -} |
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474 | | -void efx_ptp_start_datapath(struct efx_nic *efx); |
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475 | | -void efx_ptp_stop_datapath(struct efx_nic *efx); |
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476 | | -bool efx_ptp_use_mac_tx_timestamps(struct efx_nic *efx); |
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477 | | -ktime_t efx_ptp_nic_to_kernel_time(struct efx_tx_queue *tx_queue); |
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478 | | - |
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479 | | -extern const struct efx_nic_type falcon_a1_nic_type; |
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480 | | -extern const struct efx_nic_type falcon_b0_nic_type; |
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481 | 307 | extern const struct efx_nic_type siena_a0_nic_type; |
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482 | 308 | extern const struct efx_nic_type efx_hunt_a0_nic_type; |
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483 | 309 | extern const struct efx_nic_type efx_hunt_a0_vf_nic_type; |
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484 | 310 | |
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485 | | -/************************************************************************** |
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486 | | - * |
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487 | | - * Externs |
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488 | | - * |
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489 | | - ************************************************************************** |
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490 | | - */ |
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491 | | - |
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492 | 311 | int falcon_probe_board(struct efx_nic *efx, u16 revision_info); |
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493 | | - |
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494 | | -/* TX data path */ |
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495 | | -static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue) |
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496 | | -{ |
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497 | | - return tx_queue->efx->type->tx_probe(tx_queue); |
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498 | | -} |
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499 | | -static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue) |
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500 | | -{ |
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501 | | - tx_queue->efx->type->tx_init(tx_queue); |
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502 | | -} |
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503 | | -static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue) |
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504 | | -{ |
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505 | | - tx_queue->efx->type->tx_remove(tx_queue); |
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506 | | -} |
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507 | | -static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue) |
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508 | | -{ |
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509 | | - tx_queue->efx->type->tx_write(tx_queue); |
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510 | | -} |
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511 | | - |
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512 | | -/* RX data path */ |
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513 | | -static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue) |
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514 | | -{ |
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515 | | - return rx_queue->efx->type->rx_probe(rx_queue); |
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516 | | -} |
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517 | | -static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue) |
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518 | | -{ |
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519 | | - rx_queue->efx->type->rx_init(rx_queue); |
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520 | | -} |
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521 | | -static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue) |
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522 | | -{ |
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523 | | - rx_queue->efx->type->rx_remove(rx_queue); |
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524 | | -} |
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525 | | -static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue) |
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526 | | -{ |
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527 | | - rx_queue->efx->type->rx_write(rx_queue); |
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528 | | -} |
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529 | | -static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue) |
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530 | | -{ |
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531 | | - rx_queue->efx->type->rx_defer_refill(rx_queue); |
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532 | | -} |
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533 | | - |
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534 | | -/* Event data path */ |
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535 | | -static inline int efx_nic_probe_eventq(struct efx_channel *channel) |
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536 | | -{ |
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537 | | - return channel->efx->type->ev_probe(channel); |
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538 | | -} |
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539 | | -static inline int efx_nic_init_eventq(struct efx_channel *channel) |
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540 | | -{ |
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541 | | - return channel->efx->type->ev_init(channel); |
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542 | | -} |
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543 | | -static inline void efx_nic_fini_eventq(struct efx_channel *channel) |
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544 | | -{ |
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545 | | - channel->efx->type->ev_fini(channel); |
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546 | | -} |
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547 | | -static inline void efx_nic_remove_eventq(struct efx_channel *channel) |
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548 | | -{ |
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549 | | - channel->efx->type->ev_remove(channel); |
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550 | | -} |
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551 | | -static inline int |
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552 | | -efx_nic_process_eventq(struct efx_channel *channel, int quota) |
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553 | | -{ |
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554 | | - return channel->efx->type->ev_process(channel, quota); |
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555 | | -} |
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556 | | -static inline void efx_nic_eventq_read_ack(struct efx_channel *channel) |
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557 | | -{ |
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558 | | - channel->efx->type->ev_read_ack(channel); |
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559 | | -} |
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560 | | -void efx_nic_event_test_start(struct efx_channel *channel); |
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561 | 312 | |
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562 | 313 | /* Falcon/Siena queue operations */ |
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563 | 314 | int efx_farch_tx_probe(struct efx_tx_queue *tx_queue); |
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.. | .. |
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608 | 359 | #endif |
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609 | 360 | void efx_farch_filter_sync_rx_mode(struct efx_nic *efx); |
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610 | 361 | |
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611 | | -bool efx_nic_event_present(struct efx_channel *channel); |
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612 | | - |
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613 | | -/* Some statistics are computed as A - B where A and B each increase |
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614 | | - * linearly with some hardware counter(s) and the counters are read |
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615 | | - * asynchronously. If the counters contributing to B are always read |
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616 | | - * after those contributing to A, the computed value may be lower than |
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617 | | - * the true value by some variable amount, and may decrease between |
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618 | | - * subsequent computations. |
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619 | | - * |
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620 | | - * We should never allow statistics to decrease or to exceed the true |
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621 | | - * value. Since the computed value will never be greater than the |
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622 | | - * true value, we can achieve this by only storing the computed value |
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623 | | - * when it increases. |
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624 | | - */ |
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625 | | -static inline void efx_update_diff_stat(u64 *stat, u64 diff) |
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626 | | -{ |
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627 | | - if ((s64)(diff - *stat) > 0) |
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628 | | - *stat = diff; |
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629 | | -} |
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630 | | - |
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631 | | -/* Interrupts */ |
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632 | | -int efx_nic_init_interrupt(struct efx_nic *efx); |
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633 | | -int efx_nic_irq_test_start(struct efx_nic *efx); |
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634 | | -void efx_nic_fini_interrupt(struct efx_nic *efx); |
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635 | | - |
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636 | 362 | /* Falcon/Siena interrupts */ |
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637 | 363 | void efx_farch_irq_enable_master(struct efx_nic *efx); |
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638 | 364 | int efx_farch_irq_test_generate(struct efx_nic *efx); |
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.. | .. |
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641 | 367 | irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id); |
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642 | 368 | irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx); |
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643 | 369 | |
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644 | | -static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel) |
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645 | | -{ |
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646 | | - return READ_ONCE(channel->event_test_cpu); |
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647 | | -} |
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648 | | -static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx) |
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649 | | -{ |
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650 | | - return READ_ONCE(efx->last_irq_cpu); |
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651 | | -} |
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652 | | - |
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653 | 370 | /* Global Resources */ |
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654 | | -int efx_nic_flush_queues(struct efx_nic *efx); |
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655 | 371 | void siena_prepare_flush(struct efx_nic *efx); |
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656 | 372 | int efx_farch_fini_dmaq(struct efx_nic *efx); |
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657 | 373 | void efx_farch_finish_flr(struct efx_nic *efx); |
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.. | .. |
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661 | 377 | int falcon_reset_xaui(struct efx_nic *efx); |
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662 | 378 | void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw); |
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663 | 379 | void efx_farch_init_common(struct efx_nic *efx); |
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664 | | -void efx_ef10_handle_drain_event(struct efx_nic *efx); |
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665 | 380 | void efx_farch_rx_push_indir_table(struct efx_nic *efx); |
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666 | 381 | void efx_farch_rx_pull_indir_table(struct efx_nic *efx); |
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667 | | - |
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668 | | -int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, |
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669 | | - unsigned int len, gfp_t gfp_flags); |
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670 | | -void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer); |
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671 | 382 | |
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672 | 383 | /* Tests */ |
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673 | 384 | struct efx_farch_register_test { |
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674 | 385 | unsigned address; |
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675 | 386 | efx_oword_t mask; |
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676 | 387 | }; |
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| 388 | + |
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677 | 389 | int efx_farch_test_registers(struct efx_nic *efx, |
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678 | 390 | const struct efx_farch_register_test *regs, |
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679 | 391 | size_t n_regs); |
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680 | | - |
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681 | | -size_t efx_nic_get_regs_len(struct efx_nic *efx); |
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682 | | -void efx_nic_get_regs(struct efx_nic *efx, void *buf); |
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683 | | - |
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684 | | -size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count, |
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685 | | - const unsigned long *mask, u8 *names); |
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686 | | -void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count, |
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687 | | - const unsigned long *mask, u64 *stats, |
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688 | | - const void *dma_buf, bool accumulate); |
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689 | | -void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *stat); |
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690 | | - |
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691 | | -#define EFX_MAX_FLUSH_TIME 5000 |
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692 | 392 | |
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693 | 393 | void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq, |
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694 | 394 | efx_qword_t *event); |
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