~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,33 +1,7 @@
	1	+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
1	2	/* QLogic qed NIC Driver
2	3	* Copyright (c) 2015-2017 QLogic Corporation
3		- *
4		- * This software is available to you under a choice of one of two
5		- * licenses. You may choose to be licensed under the terms of the GNU
6		- * General Public License (GPL) Version 2, available from the file
7		- * COPYING in the main directory of this source tree, or the
8		- * OpenIB.org BSD license below:
9		- *
10		- * Redistribution and use in source and binary forms, with or
11		- * without modification, are permitted provided that the following
12		- * conditions are met:
13		- *
14		- * - Redistributions of source code must retain the above
15		- * copyright notice, this list of conditions and the following
16		- * disclaimer.
17		- *
18		- * - Redistributions in binary form must reproduce the above
19		- * copyright notice, this list of conditions and the following
20		- * disclaimer in the documentation and /or other materials
21		- * provided with the distribution.
22		- *
23		- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24		- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25		- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26		- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27		- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28		- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29		- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30		- * SOFTWARE.
	4	+ * Copyright (c) 2019-2020 Marvell International Ltd.
31	5	*/
32	6
33	7	#ifndef _QED_HSI_H
..	..	@@ -98,6 +72,7 @@
98	72	CORE_EVENT_RX_QUEUE_STOP,
99	73	CORE_EVENT_RX_QUEUE_FLUSH,
100	74	CORE_EVENT_TX_QUEUE_UPDATE,
	75	+ CORE_EVENT_QUEUE_STATS_QUERY,
101	76	MAX_CORE_EVENT_OPCODE
102	77	};
103	78
..	..	@@ -116,7 +91,7 @@
116	91	struct regpair gsi_crcchksm_error;
117	92	};
118	93
119		-/* Ethernet TX Per Queue Stats */
	94	+/* LL2 TX Per Queue Stats */
120	95	struct core_ll2_pstorm_per_queue_stat {
121	96	struct regpair sent_ucast_bytes;
122	97	struct regpair sent_mcast_bytes;
..	..	@@ -124,13 +99,13 @@
124	99	struct regpair sent_ucast_pkts;
125	100	struct regpair sent_mcast_pkts;
126	101	struct regpair sent_bcast_pkts;
	102	+ struct regpair error_drop_pkts;
127	103	};
128	104
129	105	/* Light-L2 RX Producers in Tstorm RAM */
130	106	struct core_ll2_rx_prod {
131	107	__le16 bd_prod;
132	108	__le16 cqe_prod;
133		- __le32 reserved;
134	109	};
135	110
136	111	struct core_ll2_tstorm_per_queue_stat {
..	..	@@ -147,6 +122,18 @@
147	122	struct regpair rcv_bcast_pkts;
148	123	};
149	124
	125	+/* Structure for doorbell data, in PWM mode, for RX producers update. */
	126	+struct core_pwm_prod_update_data {
	127	+ __le16 icid; /* internal CID */
	128	+ u8 reserved0;
	129	+ u8 params;
	130	+#define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
	131	+#define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0
	132	+#define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0 */
	133	+#define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_SHIFT 2
	134	+ struct core_ll2_rx_prod prod; /* Producers */
	135	+};
	136	+
150	137	/* Core Ramrod Command IDs (light L2) */
151	138	enum core_ramrod_cmd_id {
152	139	CORE_RAMROD_UNUSED,
..	..	@@ -156,6 +143,7 @@
156	143	CORE_RAMROD_TX_QUEUE_STOP,
157	144	CORE_RAMROD_RX_QUEUE_FLUSH,
158	145	CORE_RAMROD_TX_QUEUE_UPDATE,
	146	+ CORE_RAMROD_QUEUE_STATS_QUERY,
159	147	MAX_CORE_RAMROD_CMD_ID
160	148	};
161	149
..	..	@@ -236,7 +224,8 @@
236	224	__le16 src_mac_addrlo;
237	225	__le16 qp_id;
238	226	__le32 src_qp;
239		- __le32 reserved[3];
	227	+ struct core_rx_cqe_opaque_data opaque_data;
	228	+ __le32 reserved;
240	229	};
241	230
242	231	/* Core RX CQE for Light L2 */
..	..	@@ -274,7 +263,11 @@
274	263	u8 mf_si_mcast_accept_all;
275	264	struct core_rx_action_on_error action_on_error;
276	265	u8 gsi_offload_flag;
277		- u8 reserved[6];
	266	+ u8 vport_id_valid;
	267	+ u8 vport_id;
	268	+ u8 zero_prod_flg;
	269	+ u8 wipe_inner_vlan_pri_en;
	270	+ u8 reserved[2];
278	271	};
279	272
280	273	/* Ramrod data for rx queue stop ramrod */
..	..	@@ -351,7 +344,11 @@
351	344	__le16 pbl_size;
352	345	__le16 qm_pq_id;
353	346	u8 gsi_offload_flag;
354		- u8 resrved[3];
	347	+ u8 ctx_stats_en;
	348	+ u8 vport_id_valid;
	349	+ u8 vport_id;
	350	+ u8 enforce_security_flag;
	351	+ u8 reserved[7];
355	352	};
356	353
357	354	/* Ramrod data for tx queue stop ramrod */
..	..	@@ -364,7 +361,7 @@
364	361	u8 update_qm_pq_id_flg;
365	362	u8 reserved0;
366	363	__le16 qm_pq_id;
367		- __le32 reserved1[1];
	364	+ __le32 reserved1;
368	365	};
369	366
370	367	/* Enum flag for what type of dcb data to update */
..	..	@@ -383,7 +380,7 @@
383	380
384	381	/* The core storm context for the Pstorm */
385	382	struct pstorm_core_conn_st_ctx {
386		- __le32 reserved[4];
	383	+ __le32 reserved[20];
387	384	};
388	385
389	386	/* Core Slowpath Connection storm context of Xstorm */
..	..	@@ -759,7 +756,7 @@
759	756	__le16 word1;
760	757	__le16 word2;
761	758	__le16 word3;
762		- __le32 reg9;
	759	+ __le32 ll2_rx_prod;
763	760	__le32 reg10;
764	761	};
765	762
..	..	@@ -834,11 +831,16 @@
834	831
835	832	/* The core storm context for the Mstorm */
836	833	struct mstorm_core_conn_st_ctx {
837		- __le32 reserved[24];
	834	+ __le32 reserved[40];
838	835	};
839	836
840	837	/* The core storm context for the Ustorm */
841	838	struct ustorm_core_conn_st_ctx {
	839	+ __le32 reserved[20];
	840	+};
	841	+
	842	+/* The core storm context for the Tstorm */
	843	+struct tstorm_core_conn_st_ctx {
842	844	__le32 reserved[4];
843	845	};
844	846
..	..	@@ -855,6 +857,8 @@
855	857	struct mstorm_core_conn_st_ctx mstorm_st_context;
856	858	struct ustorm_core_conn_st_ctx ustorm_st_context;
857	859	struct regpair ustorm_st_padding[2];
	860	+ struct tstorm_core_conn_st_ctx tstorm_st_context;
	861	+ struct regpair tstorm_st_padding[2];
858	862	};
859	863
860	864	struct eth_mstorm_per_pf_stat {
..	..	@@ -886,12 +890,21 @@
886	890	struct regpair sent_gre_bytes;
887	891	struct regpair sent_vxlan_bytes;
888	892	struct regpair sent_geneve_bytes;
	893	+ struct regpair sent_mpls_bytes;
	894	+ struct regpair sent_gre_mpls_bytes;
	895	+ struct regpair sent_udp_mpls_bytes;
889	896	struct regpair sent_gre_pkts;
890	897	struct regpair sent_vxlan_pkts;
891	898	struct regpair sent_geneve_pkts;
	899	+ struct regpair sent_mpls_pkts;
	900	+ struct regpair sent_gre_mpls_pkts;
	901	+ struct regpair sent_udp_mpls_pkts;
892	902	struct regpair gre_drop_pkts;
893	903	struct regpair vxlan_drop_pkts;
894	904	struct regpair geneve_drop_pkts;
	905	+ struct regpair mpls_drop_pkts;
	906	+ struct regpair gre_mpls_drop_pkts;
	907	+ struct regpair udp_mpls_drop_pkts;
895	908	};
896	909
897	910	/* Ethernet TX Per Queue Stats */
..	..	@@ -911,6 +924,16 @@
911	924	__le16 cnst;
912	925	u8 add_sub_cnst;
913	926	u8 reserved0;
	927	+ __le16 reserved1;
	928	+};
	929	+
	930	+/* Update RSS indirection table entry command */
	931	+struct eth_tstorm_rss_update_data {
	932	+ u8 valid;
	933	+ u8 vport_id;
	934	+ u8 ind_table_index;
	935	+ u8 reserved;
	936	+ __le16 ind_table_value;
914	937	__le16 reserved1;
915	938	};
916	939
..	..	@@ -971,7 +994,8 @@
971	994	struct event_ring_entry {
972	995	u8 protocol_id;
973	996	u8 opcode;
974		- __le16 reserved0;
	997	+ u8 reserved0;
	998	+ u8 vf_id;
975	999	__le16 echo;
976	1000	u8 fw_return_code;
977	1001	u8 flags;
..	..	@@ -1049,7 +1073,20 @@
1049	1073	ETH_CONTROL_PACKET_VIOLATION,
1050	1074	ETH_ANTI_SPOOFING_ERR,
1051	1075	ETH_PACKET_SIZE_TOO_LARGE,
1052		- MAX_MALICIOUS_VF_ERROR_ID
	1076	+ CORE_ILLEGAL_VLAN_MODE,
	1077	+ CORE_ILLEGAL_NBDS,
	1078	+ CORE_FIRST_BD_WO_SOP,
	1079	+ CORE_INSUFFICIENT_BDS,
	1080	+ CORE_PACKET_TOO_SMALL,
	1081	+ CORE_ILLEGAL_INBAND_TAGS,
	1082	+ CORE_VLAN_INSERT_AND_INBAND_VLAN,
	1083	+ CORE_MTU_VIOLATION,
	1084	+ CORE_CONTROL_PACKET_VIOLATION,
	1085	+ CORE_ANTI_SPOOFING_ERR,
	1086	+ CORE_PACKET_SIZE_TOO_LARGE,
	1087	+ CORE_ILLEGAL_BD_FLAGS,
	1088	+ CORE_GSI_PACKET_VIOLATION,
	1089	+ MAX_MALICIOUS_VF_ERROR_ID,
1053	1090	};
1054	1091
1055	1092	/* Mstorm non-triggering VF zone */
..	..	@@ -1241,6 +1278,10 @@
1241	1278	u8 rl_id_first;
1242	1279	u8 rl_id_last;
1243	1280	u8 rl_dc_qcn_flg;
	1281	+ u8 dcqcn_reset_alpha_on_idle;
	1282	+ u8 rl_bc_stage_th;
	1283	+ u8 rl_timer_stage_th;
	1284	+ u8 reserved1;
1244	1285	__le32 rl_bc_rate;
1245	1286	__le16 rl_max_rate;
1246	1287	__le16 rl_r_ai;
..	..	@@ -1249,7 +1290,7 @@
1249	1290	__le32 dcqcn_k_us;
1250	1291	__le32 dcqcn_timeuot_us;
1251	1292	__le32 qcn_timeuot_us;
1252		- __le32 reserved[2];
	1293	+ __le32 reserved2;
1253	1294	};
1254	1295
1255	1296	/* Slowpath Element (SPQE) */
..	..	@@ -1351,6 +1392,16 @@
1351	1392	MAX_VF_ZONE_SIZE_MODE
1352	1393	};
1353	1394
	1395	+/* Xstorm non-triggering VF zone */
	1396	+struct xstorm_non_trigger_vf_zone {
	1397	+ struct regpair non_edpm_ack_pkts;
	1398	+};
	1399	+
	1400	+/* Tstorm VF zone */
	1401	+struct xstorm_vf_zone {
	1402	+ struct xstorm_non_trigger_vf_zone non_trigger;
	1403	+};
	1404	+
1354	1405	/* Attentions status block */
1355	1406	struct atten_status_block {
1356	1407	__le32 atten_bits;
..	..	@@ -1419,7 +1470,11 @@
1419	1470	__le16 crc16;
1420	1471	__le16 crc16_c;
1421	1472	__le16 crc10;
1422		- __le16 reserved;
	1473	+ __le16 error_bit_reserved;
	1474	+#define DMAE_CMD_ERROR_BIT_MASK 0x1
	1475	+#define DMAE_CMD_ERROR_BIT_SHIFT 0
	1476	+#define DMAE_CMD_RESERVED_MASK 0x7FFF
	1477	+#define DMAE_CMD_RESERVED_SHIFT 1
1423	1478	__le16 xsum16;
1424	1479	__le16 xsum8;
1425	1480	};
..	..	@@ -1548,6 +1603,41 @@
1548	1603	__le16 word4;
1549	1604	__le32 reg2;
1550	1605	__le32 reg3;
	1606	+};
	1607	+
	1608	+/* DMAE parameters */
	1609	+struct qed_dmae_params {
	1610	+ u32 flags;
	1611	+/* If QED_DMAE_PARAMS_RW_REPL_SRC flag is set and the
	1612	+ * source is a block of length DMAE_MAX_RW_SIZE and the
	1613	+ * destination is larger, the source block will be duplicated as
	1614	+ * many times as required to fill the destination block. This is
	1615	+ * used mostly to write a zeroed buffer to destination address
	1616	+ * using DMA
	1617	+ */
	1618	+#define QED_DMAE_PARAMS_RW_REPL_SRC_MASK 0x1
	1619	+#define QED_DMAE_PARAMS_RW_REPL_SRC_SHIFT 0
	1620	+#define QED_DMAE_PARAMS_SRC_VF_VALID_MASK 0x1
	1621	+#define QED_DMAE_PARAMS_SRC_VF_VALID_SHIFT 1
	1622	+#define QED_DMAE_PARAMS_DST_VF_VALID_MASK 0x1
	1623	+#define QED_DMAE_PARAMS_DST_VF_VALID_SHIFT 2
	1624	+#define QED_DMAE_PARAMS_COMPLETION_DST_MASK 0x1
	1625	+#define QED_DMAE_PARAMS_COMPLETION_DST_SHIFT 3
	1626	+#define QED_DMAE_PARAMS_PORT_VALID_MASK 0x1
	1627	+#define QED_DMAE_PARAMS_PORT_VALID_SHIFT 4
	1628	+#define QED_DMAE_PARAMS_SRC_PF_VALID_MASK 0x1
	1629	+#define QED_DMAE_PARAMS_SRC_PF_VALID_SHIFT 5
	1630	+#define QED_DMAE_PARAMS_DST_PF_VALID_MASK 0x1
	1631	+#define QED_DMAE_PARAMS_DST_PF_VALID_SHIFT 6
	1632	+#define QED_DMAE_PARAMS_RESERVED_MASK 0x1FFFFFF
	1633	+#define QED_DMAE_PARAMS_RESERVED_SHIFT 7
	1634	+ u8 src_vfid;
	1635	+ u8 dst_vfid;
	1636	+ u8 port_id;
	1637	+ u8 src_pfid;
	1638	+ u8 dst_pfid;
	1639	+ u8 reserved1;
	1640	+ __le16 reserved2;
1551	1641	};
1552	1642
1553	1643	/* IGU cleanup command */
..	..	@@ -1727,101 +1817,22 @@
1727	1817	#define SDM_OP_GEN_RESERVED_SHIFT 20
1728	1818	};
1729	1819
	1820	+/* Physical memory descriptor */
	1821	+struct phys_mem_desc {
	1822	+ dma_addr_t phys_addr;
	1823	+ void *virt_addr;
	1824	+ u32 size; /* In bytes */
	1825	+};
	1826	+
	1827	+/* Virtual memory descriptor */
	1828	+struct virt_mem_desc {
	1829	+ void *ptr;
	1830	+ u32 size; /* In bytes */
	1831	+};
	1832	+
1730	1833	/****************************************/
1731	1834	/* Debug Tools HSI constants and macros */
1732	1835	/****************************************/
1733		-
1734		-enum block_addr {
1735		- GRCBASE_GRC = 0x50000,
1736		- GRCBASE_MISCS = 0x9000,
1737		- GRCBASE_MISC = 0x8000,
1738		- GRCBASE_DBU = 0xa000,
1739		- GRCBASE_PGLUE_B = 0x2a8000,
1740		- GRCBASE_CNIG = 0x218000,
1741		- GRCBASE_CPMU = 0x30000,
1742		- GRCBASE_NCSI = 0x40000,
1743		- GRCBASE_OPTE = 0x53000,
1744		- GRCBASE_BMB = 0x540000,
1745		- GRCBASE_PCIE = 0x54000,
1746		- GRCBASE_MCP = 0xe00000,
1747		- GRCBASE_MCP2 = 0x52000,
1748		- GRCBASE_PSWHST = 0x2a0000,
1749		- GRCBASE_PSWHST2 = 0x29e000,
1750		- GRCBASE_PSWRD = 0x29c000,
1751		- GRCBASE_PSWRD2 = 0x29d000,
1752		- GRCBASE_PSWWR = 0x29a000,
1753		- GRCBASE_PSWWR2 = 0x29b000,
1754		- GRCBASE_PSWRQ = 0x280000,
1755		- GRCBASE_PSWRQ2 = 0x240000,
1756		- GRCBASE_PGLCS = 0x0,
1757		- GRCBASE_DMAE = 0xc000,
1758		- GRCBASE_PTU = 0x560000,
1759		- GRCBASE_TCM = 0x1180000,
1760		- GRCBASE_MCM = 0x1200000,
1761		- GRCBASE_UCM = 0x1280000,
1762		- GRCBASE_XCM = 0x1000000,
1763		- GRCBASE_YCM = 0x1080000,
1764		- GRCBASE_PCM = 0x1100000,
1765		- GRCBASE_QM = 0x2f0000,
1766		- GRCBASE_TM = 0x2c0000,
1767		- GRCBASE_DORQ = 0x100000,
1768		- GRCBASE_BRB = 0x340000,
1769		- GRCBASE_SRC = 0x238000,
1770		- GRCBASE_PRS = 0x1f0000,
1771		- GRCBASE_TSDM = 0xfb0000,
1772		- GRCBASE_MSDM = 0xfc0000,
1773		- GRCBASE_USDM = 0xfd0000,
1774		- GRCBASE_XSDM = 0xf80000,
1775		- GRCBASE_YSDM = 0xf90000,
1776		- GRCBASE_PSDM = 0xfa0000,
1777		- GRCBASE_TSEM = 0x1700000,
1778		- GRCBASE_MSEM = 0x1800000,
1779		- GRCBASE_USEM = 0x1900000,
1780		- GRCBASE_XSEM = 0x1400000,
1781		- GRCBASE_YSEM = 0x1500000,
1782		- GRCBASE_PSEM = 0x1600000,
1783		- GRCBASE_RSS = 0x238800,
1784		- GRCBASE_TMLD = 0x4d0000,
1785		- GRCBASE_MULD = 0x4e0000,
1786		- GRCBASE_YULD = 0x4c8000,
1787		- GRCBASE_XYLD = 0x4c0000,
1788		- GRCBASE_PTLD = 0x5a0000,
1789		- GRCBASE_YPLD = 0x5c0000,
1790		- GRCBASE_PRM = 0x230000,
1791		- GRCBASE_PBF_PB1 = 0xda0000,
1792		- GRCBASE_PBF_PB2 = 0xda4000,
1793		- GRCBASE_RPB = 0x23c000,
1794		- GRCBASE_BTB = 0xdb0000,
1795		- GRCBASE_PBF = 0xd80000,
1796		- GRCBASE_RDIF = 0x300000,
1797		- GRCBASE_TDIF = 0x310000,
1798		- GRCBASE_CDU = 0x580000,
1799		- GRCBASE_CCFC = 0x2e0000,
1800		- GRCBASE_TCFC = 0x2d0000,
1801		- GRCBASE_IGU = 0x180000,
1802		- GRCBASE_CAU = 0x1c0000,
1803		- GRCBASE_RGFS = 0xf00000,
1804		- GRCBASE_RGSRC = 0x320000,
1805		- GRCBASE_TGFS = 0xd00000,
1806		- GRCBASE_TGSRC = 0x322000,
1807		- GRCBASE_UMAC = 0x51000,
1808		- GRCBASE_XMAC = 0x210000,
1809		- GRCBASE_DBG = 0x10000,
1810		- GRCBASE_NIG = 0x500000,
1811		- GRCBASE_WOL = 0x600000,
1812		- GRCBASE_BMBN = 0x610000,
1813		- GRCBASE_IPC = 0x20000,
1814		- GRCBASE_NWM = 0x800000,
1815		- GRCBASE_NWS = 0x700000,
1816		- GRCBASE_MS = 0x6a0000,
1817		- GRCBASE_PHY_PCIE = 0x620000,
1818		- GRCBASE_LED = 0x6b8000,
1819		- GRCBASE_AVS_WRAP = 0x6b0000,
1820		- GRCBASE_PXPREQBUS = 0x56000,
1821		- GRCBASE_MISC_AEU = 0x8000,
1822		- GRCBASE_BAR0_MAP = 0x1c00000,
1823		- MAX_BLOCK_ADDR
1824		-};
1825	1836
1826	1837	enum block_id {
1827	1838	BLOCK_GRC,
..	..	@@ -1877,8 +1888,6 @@
1877	1888	BLOCK_MULD,
1878	1889	BLOCK_YULD,
1879	1890	BLOCK_XYLD,
1880		- BLOCK_PTLD,
1881		- BLOCK_YPLD,
1882	1891	BLOCK_PRM,
1883	1892	BLOCK_PBF_PB1,
1884	1893	BLOCK_PBF_PB2,
..	..	@@ -1892,12 +1901,9 @@
1892	1901	BLOCK_TCFC,
1893	1902	BLOCK_IGU,
1894	1903	BLOCK_CAU,
1895		- BLOCK_RGFS,
1896		- BLOCK_RGSRC,
1897		- BLOCK_TGFS,
1898		- BLOCK_TGSRC,
1899	1904	BLOCK_UMAC,
1900	1905	BLOCK_XMAC,
	1906	+ BLOCK_MSTAT,
1901	1907	BLOCK_DBG,
1902	1908	BLOCK_NIG,
1903	1909	BLOCK_WOL,
..	..	@@ -1910,8 +1916,17 @@
1910	1916	BLOCK_LED,
1911	1917	BLOCK_AVS_WRAP,
1912	1918	BLOCK_PXPREQBUS,
1913		- BLOCK_MISC_AEU,
1914	1919	BLOCK_BAR0_MAP,
	1920	+ BLOCK_MCP_FIO,
	1921	+ BLOCK_LAST_INIT,
	1922	+ BLOCK_PRS_FC,
	1923	+ BLOCK_PBF_FC,
	1924	+ BLOCK_NIG_LB_FC,
	1925	+ BLOCK_NIG_LB_FC_PLLH,
	1926	+ BLOCK_NIG_TX_FC_PLLH,
	1927	+ BLOCK_NIG_TX_FC,
	1928	+ BLOCK_NIG_RX_FC_PLLH,
	1929	+ BLOCK_NIG_RX_FC,
1915	1930	MAX_BLOCK_ID
1916	1931	};
1917	1932
..	..	@@ -1928,10 +1943,13 @@
1928	1943	BIN_BUF_DBG_ATTN_REGS,
1929	1944	BIN_BUF_DBG_ATTN_INDEXES,
1930	1945	BIN_BUF_DBG_ATTN_NAME_OFFSETS,
1931		- BIN_BUF_DBG_BUS_BLOCKS,
	1946	+ BIN_BUF_DBG_BLOCKS,
	1947	+ BIN_BUF_DBG_BLOCKS_CHIP_DATA,
1932	1948	BIN_BUF_DBG_BUS_LINES,
1933		- BIN_BUF_DBG_BUS_BLOCKS_USER_DATA,
	1949	+ BIN_BUF_DBG_BLOCKS_USER_DATA,
	1950	+ BIN_BUF_DBG_BLOCKS_CHIP_USER_DATA,
1934	1951	BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS,
	1952	+ BIN_BUF_DBG_RESET_REGS,
1935	1953	BIN_BUF_DBG_PARSING_STRINGS,
1936	1954	MAX_BIN_DBG_BUFFER_TYPE
1937	1955	};
..	..	@@ -2015,18 +2033,52 @@
2015	2033	MAX_DBG_ATTN_TYPE
2016	2034	};
2017	2035
2018		-/* Debug Bus block data */
2019		-struct dbg_bus_block {
2020		- u8 num_of_lines;
2021		- u8 has_latency_events;
2022		- u16 lines_offset;
	2036	+/* Block debug data */
	2037	+struct dbg_block {
	2038	+ u8 name[15];
	2039	+ u8 associated_storm_letter;
2023	2040	};
2024	2041
2025		-/* Debug Bus block user data */
2026		-struct dbg_bus_block_user_data {
2027		- u8 num_of_lines;
	2042	+/* Chip-specific block debug data */
	2043	+struct dbg_block_chip {
	2044	+ u8 flags;
	2045	+#define DBG_BLOCK_CHIP_IS_REMOVED_MASK 0x1
	2046	+#define DBG_BLOCK_CHIP_IS_REMOVED_SHIFT 0
	2047	+#define DBG_BLOCK_CHIP_HAS_RESET_REG_MASK 0x1
	2048	+#define DBG_BLOCK_CHIP_HAS_RESET_REG_SHIFT 1
	2049	+#define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_MASK 0x1
	2050	+#define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_SHIFT 2
	2051	+#define DBG_BLOCK_CHIP_HAS_DBG_BUS_MASK 0x1
	2052	+#define DBG_BLOCK_CHIP_HAS_DBG_BUS_SHIFT 3
	2053	+#define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_MASK 0x1
	2054	+#define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_SHIFT 4
	2055	+#define DBG_BLOCK_CHIP_RESERVED0_MASK 0x7
	2056	+#define DBG_BLOCK_CHIP_RESERVED0_SHIFT 5
	2057	+ u8 dbg_client_id;
	2058	+ u8 reset_reg_id;
	2059	+ u8 reset_reg_bit_offset;
	2060	+ struct dbg_mode_hdr dbg_bus_mode;
	2061	+ u16 reserved1;
	2062	+ u8 reserved2;
	2063	+ u8 num_of_dbg_bus_lines;
	2064	+ u16 dbg_bus_lines_offset;
	2065	+ u32 dbg_select_reg_addr;
	2066	+ u32 dbg_dword_enable_reg_addr;
	2067	+ u32 dbg_shift_reg_addr;
	2068	+ u32 dbg_force_valid_reg_addr;
	2069	+ u32 dbg_force_frame_reg_addr;
	2070	+};
	2071	+
	2072	+/* Chip-specific block user debug data */
	2073	+struct dbg_block_chip_user {
	2074	+ u8 num_of_dbg_bus_lines;
2028	2075	u8 has_latency_events;
2029	2076	u16 names_offset;
	2077	+};
	2078	+
	2079	+/* Block user debug data */
	2080	+struct dbg_block_user {
	2081	+ u8 name[16];
2030	2082	};
2031	2083
2032	2084	/* Block Debug line data */
..	..	@@ -2181,22 +2233,33 @@
2181	2233	MAX_DBG_IDLE_CHK_SEVERITY_TYPES
2182	2234	};
2183	2235
2184		-/* Debug Bus block data */
2185		-struct dbg_bus_block_data {
2186		- u16 data;
2187		-#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF
2188		-#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0
2189		-#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF
2190		-#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4
2191		-#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF
2192		-#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8
2193		-#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF
2194		-#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12
2195		- u8 line_num;
2196		- u8 hw_id;
	2236	+/* Reset register */
	2237	+struct dbg_reset_reg {
	2238	+ u32 data;
	2239	+#define DBG_RESET_REG_ADDR_MASK 0xFFFFFF
	2240	+#define DBG_RESET_REG_ADDR_SHIFT 0
	2241	+#define DBG_RESET_REG_IS_REMOVED_MASK 0x1
	2242	+#define DBG_RESET_REG_IS_REMOVED_SHIFT 24
	2243	+#define DBG_RESET_REG_RESERVED_MASK 0x7F
	2244	+#define DBG_RESET_REG_RESERVED_SHIFT 25
2197	2245	};
2198	2246
2199		-/* Debug Bus Clients */
	2247	+/* Debug Bus block data */
	2248	+struct dbg_bus_block_data {
	2249	+ u8 enable_mask;
	2250	+ u8 right_shift;
	2251	+ u8 force_valid_mask;
	2252	+ u8 force_frame_mask;
	2253	+ u8 dword_mask;
	2254	+ u8 line_num;
	2255	+ u8 hw_id;
	2256	+ u8 flags;
	2257	+#define DBG_BUS_BLOCK_DATA_IS_256B_LINE_MASK 0x1
	2258	+#define DBG_BUS_BLOCK_DATA_IS_256B_LINE_SHIFT 0
	2259	+#define DBG_BUS_BLOCK_DATA_RESERVED_MASK 0x7F
	2260	+#define DBG_BUS_BLOCK_DATA_RESERVED_SHIFT 1
	2261	+};
	2262	+
2200	2263	enum dbg_bus_clients {
2201	2264	DBG_BUS_CLIENT_RBCN,
2202	2265	DBG_BUS_CLIENT_RBCP,
..	..	@@ -2237,11 +2300,10 @@
2237	2300
2238	2301	/* Debug Bus trigger state data */
2239	2302	struct dbg_bus_trigger_state_data {
2240		- u8 data;
2241		-#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF
2242		-#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0
2243		-#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF
2244		-#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4
	2303	+ u8 msg_len;
	2304	+ u8 constraint_dword_mask;
	2305	+ u8 storm_id;
	2306	+ u8 reserved;
2245	2307	};
2246	2308
2247	2309	/* Debug Bus memory address */
..	..	@@ -2291,8 +2353,7 @@
2291	2353	struct dbg_bus_data {
2292	2354	u32 app_version;
2293	2355	u8 state;
2294		- u8 hw_dwords;
2295		- u16 hw_id_mask;
	2356	+ u8 mode_256b_en;
2296	2357	u8 num_enabled_blocks;
2297	2358	u8 num_enabled_storms;
2298	2359	u8 target;
..	..	@@ -2303,65 +2364,19 @@
2303	2364	u8 adding_filter;
2304	2365	u8 filter_pre_trigger;
2305	2366	u8 filter_post_trigger;
2306		- u16 reserved;
2307	2367	u8 trigger_en;
2308		- struct dbg_bus_trigger_state_data trigger_states[3];
	2368	+ u8 filter_constraint_dword_mask;
2309	2369	u8 next_trigger_state;
2310	2370	u8 next_constraint_id;
2311		- u8 unify_inputs;
	2371	+ struct dbg_bus_trigger_state_data trigger_states[3];
	2372	+ u8 filter_msg_len;
2312	2373	u8 rcv_from_other_engine;
	2374	+ u8 blocks_dword_mask;
	2375	+ u8 blocks_dword_overlap;
	2376	+ u32 hw_id_mask;
2313	2377	struct dbg_bus_pci_buf_data pci_buf;
2314		- struct dbg_bus_block_data blocks[88];
	2378	+ struct dbg_bus_block_data blocks[132];
2315	2379	struct dbg_bus_storm_data storms[6];
2316		-};
2317		-
2318		-/* Debug bus filter types */
2319		-enum dbg_bus_filter_types {
2320		- DBG_BUS_FILTER_TYPE_OFF,
2321		- DBG_BUS_FILTER_TYPE_PRE,
2322		- DBG_BUS_FILTER_TYPE_POST,
2323		- DBG_BUS_FILTER_TYPE_ON,
2324		- MAX_DBG_BUS_FILTER_TYPES
2325		-};
2326		-
2327		-/* Debug bus frame modes */
2328		-enum dbg_bus_frame_modes {
2329		- DBG_BUS_FRAME_MODE_0HW_4ST = 0, /* 0 HW dwords, 4 Storm dwords */
2330		- DBG_BUS_FRAME_MODE_4HW_0ST = 3, /* 4 HW dwords, 0 Storm dwords */
2331		- DBG_BUS_FRAME_MODE_8HW_0ST = 4, /* 8 HW dwords, 0 Storm dwords */
2332		- MAX_DBG_BUS_FRAME_MODES
2333		-};
2334		-
2335		-/* Debug bus other engine mode */
2336		-enum dbg_bus_other_engine_modes {
2337		- DBG_BUS_OTHER_ENGINE_MODE_NONE,
2338		- DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
2339		- DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,
2340		- DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,
2341		- DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,
2342		- MAX_DBG_BUS_OTHER_ENGINE_MODES
2343		-};
2344		-
2345		-/* Debug bus post-trigger recording types */
2346		-enum dbg_bus_post_trigger_types {
2347		- DBG_BUS_POST_TRIGGER_RECORD,
2348		- DBG_BUS_POST_TRIGGER_DROP,
2349		- MAX_DBG_BUS_POST_TRIGGER_TYPES
2350		-};
2351		-
2352		-/* Debug bus pre-trigger recording types */
2353		-enum dbg_bus_pre_trigger_types {
2354		- DBG_BUS_PRE_TRIGGER_START_FROM_ZERO,
2355		- DBG_BUS_PRE_TRIGGER_NUM_CHUNKS,
2356		- DBG_BUS_PRE_TRIGGER_DROP,
2357		- MAX_DBG_BUS_PRE_TRIGGER_TYPES
2358		-};
2359		-
2360		-/* Debug bus SEMI frame modes */
2361		-enum dbg_bus_semi_frame_modes {
2362		- DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0,
2363		- DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3,
2364		- MAX_DBG_BUS_SEMI_FRAME_MODES
2365	2380	};
2366	2381
2367	2382	/* Debug bus states */
..	..	@@ -2381,7 +2396,9 @@
2381	2396	DBG_BUS_STORM_MODE_DRA_W,
2382	2397	DBG_BUS_STORM_MODE_LD_ST_ADDR,
2383	2398	DBG_BUS_STORM_MODE_DRA_FSM,
	2399	+ DBG_BUS_STORM_MODE_FAST_DBGMUX,
2384	2400	DBG_BUS_STORM_MODE_RH,
	2401	+ DBG_BUS_STORM_MODE_RH_WITH_STORE,
2385	2402	DBG_BUS_STORM_MODE_FOC,
2386	2403	DBG_BUS_STORM_MODE_EXT_STORE,
2387	2404	MAX_DBG_BUS_STORM_MODES
..	..	@@ -2422,13 +2439,13 @@
2422	2439	DBG_GRC_PARAM_DUMP_CAU,
2423	2440	DBG_GRC_PARAM_DUMP_QM,
2424	2441	DBG_GRC_PARAM_DUMP_MCP,
2425		- DBG_GRC_PARAM_MCP_TRACE_META_SIZE,
	2442	+ DBG_GRC_PARAM_DUMP_DORQ,
2426	2443	DBG_GRC_PARAM_DUMP_CFC,
2427	2444	DBG_GRC_PARAM_DUMP_IGU,
2428	2445	DBG_GRC_PARAM_DUMP_BRB,
2429	2446	DBG_GRC_PARAM_DUMP_BTB,
2430	2447	DBG_GRC_PARAM_DUMP_BMB,
2431		- DBG_GRC_PARAM_DUMP_NIG,
	2448	+ DBG_GRC_PARAM_RESERVD1,
2432	2449	DBG_GRC_PARAM_DUMP_MULD,
2433	2450	DBG_GRC_PARAM_DUMP_PRS,
2434	2451	DBG_GRC_PARAM_DUMP_DMAE,
..	..	@@ -2437,8 +2454,8 @@
2437	2454	DBG_GRC_PARAM_DUMP_DIF,
2438	2455	DBG_GRC_PARAM_DUMP_STATIC,
2439	2456	DBG_GRC_PARAM_UNSTALL,
2440		- DBG_GRC_PARAM_NUM_LCIDS,
2441		- DBG_GRC_PARAM_NUM_LTIDS,
	2457	+ DBG_GRC_PARAM_RESERVED2,
	2458	+ DBG_GRC_PARAM_MCP_TRACE_META_SIZE,
2442	2459	DBG_GRC_PARAM_EXCLUDE_ALL,
2443	2460	DBG_GRC_PARAM_CRASH,
2444	2461	DBG_GRC_PARAM_PARITY_SAFE,
..	..	@@ -2446,20 +2463,12 @@
2446	2463	DBG_GRC_PARAM_DUMP_PHY,
2447	2464	DBG_GRC_PARAM_NO_MCP,
2448	2465	DBG_GRC_PARAM_NO_FW_VER,
	2466	+ DBG_GRC_PARAM_RESERVED3,
	2467	+ DBG_GRC_PARAM_DUMP_MCP_HW_DUMP,
	2468	+ DBG_GRC_PARAM_DUMP_ILT_CDUC,
	2469	+ DBG_GRC_PARAM_DUMP_ILT_CDUT,
	2470	+ DBG_GRC_PARAM_DUMP_CAU_EXT,
2449	2471	MAX_DBG_GRC_PARAMS
2450		-};
2451		-
2452		-/* Debug reset registers */
2453		-enum dbg_reset_regs {
2454		- DBG_RESET_REG_MISCS_PL_UA,
2455		- DBG_RESET_REG_MISCS_PL_HV,
2456		- DBG_RESET_REG_MISCS_PL_HV_2,
2457		- DBG_RESET_REG_MISC_PL_UA,
2458		- DBG_RESET_REG_MISC_PL_HV,
2459		- DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
2460		- DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
2461		- DBG_RESET_REG_MISC_PL_PDA_VAUX,
2462		- MAX_DBG_RESET_REGS
2463	2472	};
2464	2473
2465	2474	/* Debug status codes */
..	..	@@ -2473,15 +2482,15 @@
2473	2482	DBG_STATUS_INVALID_PCI_BUF_SIZE,
2474	2483	DBG_STATUS_PCI_BUF_ALLOC_FAILED,
2475	2484	DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
2476		- DBG_STATUS_TOO_MANY_INPUTS,
2477		- DBG_STATUS_INPUT_OVERLAP,
2478		- DBG_STATUS_HW_ONLY_RECORDING,
	2485	+ DBG_STATUS_INVALID_FILTER_TRIGGER_DWORDS,
	2486	+ DBG_STATUS_NO_MATCHING_FRAMING_MODE,
	2487	+ DBG_STATUS_VFC_READ_ERROR,
2479	2488	DBG_STATUS_STORM_ALREADY_ENABLED,
2480	2489	DBG_STATUS_STORM_NOT_ENABLED,
2481	2490	DBG_STATUS_BLOCK_ALREADY_ENABLED,
2482	2491	DBG_STATUS_BLOCK_NOT_ENABLED,
2483	2492	DBG_STATUS_NO_INPUT_ENABLED,
2484		- DBG_STATUS_NO_FILTER_TRIGGER_64B,
	2493	+ DBG_STATUS_NO_FILTER_TRIGGER_256B,
2485	2494	DBG_STATUS_FILTER_ALREADY_ENABLED,
2486	2495	DBG_STATUS_TRIGGER_ALREADY_ENABLED,
2487	2496	DBG_STATUS_TRIGGER_NOT_ENABLED,
..	..	@@ -2506,7 +2515,7 @@
2506	2515	DBG_STATUS_MCP_TRACE_NO_META,
2507	2516	DBG_STATUS_MCP_COULD_NOT_HALT,
2508	2517	DBG_STATUS_MCP_COULD_NOT_RESUME,
2509		- DBG_STATUS_RESERVED2,
	2518	+ DBG_STATUS_RESERVED0,
2510	2519	DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
2511	2520	DBG_STATUS_IGU_FIFO_BAD_DATA,
2512	2521	DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
..	..	@@ -2514,10 +2523,15 @@
2514	2523	DBG_STATUS_REG_FIFO_BAD_DATA,
2515	2524	DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
2516	2525	DBG_STATUS_DBG_ARRAY_NOT_SET,
2517		- DBG_STATUS_FILTER_BUG,
	2526	+ DBG_STATUS_RESERVED1,
2518	2527	DBG_STATUS_NON_MATCHING_LINES,
2519		- DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET,
	2528	+ DBG_STATUS_INSUFFICIENT_HW_IDS,
2520	2529	DBG_STATUS_DBG_BUS_IN_USE,
	2530	+ DBG_STATUS_INVALID_STORM_DBG_MODE,
	2531	+ DBG_STATUS_OTHER_ENGINE_BB_ONLY,
	2532	+ DBG_STATUS_FILTER_SINGLE_HW_ID,
	2533	+ DBG_STATUS_TRIGGER_SINGLE_HW_ID,
	2534	+ DBG_STATUS_MISSING_TRIGGER_STATE_STORM,
2521	2535	MAX_DBG_STATUS
2522	2536	};
2523	2537
..	..	@@ -2553,9 +2567,9 @@
2553	2567	struct dbg_bus_data bus;
2554	2568	struct idle_chk_data idle_chk;
2555	2569	u8 mode_enable[40];
2556		- u8 block_in_reset[88];
	2570	+ u8 block_in_reset[132];
2557	2571	u8 chip_id;
2558		- u8 platform_id;
	2572	+ u8 hw_type;
2559	2573	u8 num_ports;
2560	2574	u8 num_pfs_per_port;
2561	2575	u8 num_vfs;
..	..	@@ -2564,6 +2578,19 @@
2564	2578	u8 reserved;
2565	2579	struct pretend_params pretend;
2566	2580	u32 num_regs_read;
	2581	+};
	2582	+
	2583	+/* ILT Clients */
	2584	+enum ilt_clients {
	2585	+ ILT_CLI_CDUC,
	2586	+ ILT_CLI_CDUT,
	2587	+ ILT_CLI_QM,
	2588	+ ILT_CLI_TM,
	2589	+ ILT_CLI_SRC,
	2590	+ ILT_CLI_TSDM,
	2591	+ ILT_CLI_RGFS,
	2592	+ ILT_CLI_TGFS,
	2593	+ MAX_ILT_CLIENTS
2567	2594	};
2568	2595
2569	2596	/********************************/
..	..	@@ -2614,13 +2641,18 @@
2614	2641	struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
2615	2642	};
2616	2643
	2644	+/* QM per global RL init parameters */
	2645	+struct init_qm_global_rl_params {
	2646	+ u32 rate_limit;
	2647	+};
	2648	+
2617	2649	/* QM per-port init parameters */
2618	2650	struct init_qm_port_params {
2619		- u8 active;
2620		- u8 active_phys_tcs;
	2651	+ u16 active_phys_tcs;
2621	2652	u16 num_pbf_cmd_lines;
2622	2653	u16 num_btb_blocks;
2623		- u16 reserved;
	2654	+ u8 active;
	2655	+ u8 reserved;
2624	2656	};
2625	2657
2626	2658	/* QM per-PQ init parameters */
..	..	@@ -2629,15 +2661,14 @@
2629	2661	u8 tc_id;
2630	2662	u8 wrr_group;
2631	2663	u8 rl_valid;
	2664	+ u16 rl_id;
2632	2665	u8 port_id;
2633		- u8 reserved0;
2634		- u16 reserved1;
	2666	+ u8 reserved;
2635	2667	};
2636	2668
2637	2669	/* QM per-vport init parameters */
2638	2670	struct init_qm_vport_params {
2639		- u32 vport_rl;
2640		- u16 vport_wfq;
	2671	+ u16 wfq;
2641	2672	u16 first_tx_pq_id[NUM_OF_TCS];
2642	2673	};
2643	2674
..	..	@@ -2657,13 +2688,12 @@
2657	2688	enum chip_ids {
2658	2689	CHIP_BB,
2659	2690	CHIP_K2,
2660		- CHIP_RESERVED,
2661	2691	MAX_CHIP_IDS
2662	2692	};
2663	2693
2664	2694	struct fw_asserts_ram_section {
2665		- u16 section_ram_line_offset;
2666		- u16 section_ram_line_size;
	2695	+ __le16 section_ram_line_offset;
	2696	+ __le16 section_ram_line_size;
2667	2697	u8 list_dword_offset;
2668	2698	u8 list_element_dword_size;
2669	2699	u8 list_num_elements;
..	..	@@ -2713,6 +2743,7 @@
2713	2743	MODE_PORTS_PER_ENG_4,
2714	2744	MODE_100G,
2715	2745	MODE_RESERVED6,
	2746	+ MODE_RESERVED7,
2716	2747	MAX_INIT_MODES
2717	2748	};
2718	2749
..	..	@@ -2747,39 +2778,49 @@
2747	2778	BIN_BUF_INIT_VAL,
2748	2779	BIN_BUF_INIT_MODE_TREE,
2749	2780	BIN_BUF_INIT_IRO,
	2781	+ BIN_BUF_INIT_OVERLAYS,
2750	2782	MAX_BIN_INIT_BUFFER_TYPE
	2783	+};
	2784	+
	2785	+/* FW overlay buffer header */
	2786	+struct fw_overlay_buf_hdr {
	2787	+ u32 data;
	2788	+#define FW_OVERLAY_BUF_HDR_STORM_ID_MASK 0xFF
	2789	+#define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0
	2790	+#define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK 0xFFFFFF
	2791	+#define FW_OVERLAY_BUF_HDR_BUF_SIZE_SHIFT 8
2751	2792	};
2752	2793
2753	2794	/* init array header: raw */
2754	2795	struct init_array_raw_hdr {
2755		- u32 data;
2756		-#define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
2757		-#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
2758		-#define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
2759		-#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
	2796	+ __le32 data;
	2797	+#define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
	2798	+#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
	2799	+#define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
	2800	+#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
2760	2801	};
2761	2802
2762	2803	/* init array header: standard */
2763	2804	struct init_array_standard_hdr {
2764		- u32 data;
2765		-#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
2766		-#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
2767		-#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
2768		-#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
	2805	+ __le32 data;
	2806	+#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
	2807	+#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
	2808	+#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
	2809	+#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
2769	2810	};
2770	2811
2771	2812	/* init array header: zipped */
2772	2813	struct init_array_zipped_hdr {
2773		- u32 data;
2774		-#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
2775		-#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
2776		-#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
2777		-#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
	2814	+ __le32 data;
	2815	+#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
	2816	+#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
	2817	+#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
	2818	+#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
2778	2819	};
2779	2820
2780	2821	/* init array header: pattern */
2781	2822	struct init_array_pattern_hdr {
2782		- u32 data;
	2823	+ __le32 data;
2783	2824	#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
2784	2825	#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
2785	2826	#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
..	..	@@ -2790,10 +2831,10 @@
2790	2831
2791	2832	/* init array header union */
2792	2833	union init_array_hdr {
2793		- struct init_array_raw_hdr raw;
2794		- struct init_array_standard_hdr standard;
2795		- struct init_array_zipped_hdr zipped;
2796		- struct init_array_pattern_hdr pattern;
	2834	+ struct init_array_raw_hdr raw;
	2835	+ struct init_array_standard_hdr standard;
	2836	+ struct init_array_zipped_hdr zipped;
	2837	+ struct init_array_pattern_hdr pattern;
2797	2838	};
2798	2839
2799	2840	/* init array types */
..	..	@@ -2806,56 +2847,54 @@
2806	2847
2807	2848	/* init operation: callback */
2808	2849	struct init_callback_op {
2809		- u32 op_data;
2810		-#define INIT_CALLBACK_OP_OP_MASK 0xF
2811		-#define INIT_CALLBACK_OP_OP_SHIFT 0
2812		-#define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
2813		-#define INIT_CALLBACK_OP_RESERVED_SHIFT 4
2814		- u16 callback_id;
2815		- u16 block_id;
	2850	+ __le32 op_data;
	2851	+#define INIT_CALLBACK_OP_OP_MASK 0xF
	2852	+#define INIT_CALLBACK_OP_OP_SHIFT 0
	2853	+#define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
	2854	+#define INIT_CALLBACK_OP_RESERVED_SHIFT 4
	2855	+ __le16 callback_id;
	2856	+ __le16 block_id;
2816	2857	};
2817	2858
2818	2859	/* init operation: delay */
2819	2860	struct init_delay_op {
2820		- u32 op_data;
2821		-#define INIT_DELAY_OP_OP_MASK 0xF
2822		-#define INIT_DELAY_OP_OP_SHIFT 0
2823		-#define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
2824		-#define INIT_DELAY_OP_RESERVED_SHIFT 4
2825		- u32 delay;
	2861	+ __le32 op_data;
	2862	+#define INIT_DELAY_OP_OP_MASK 0xF
	2863	+#define INIT_DELAY_OP_OP_SHIFT 0
	2864	+#define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
	2865	+#define INIT_DELAY_OP_RESERVED_SHIFT 4
	2866	+ __le32 delay;
2826	2867	};
2827	2868
2828	2869	/* init operation: if_mode */
2829	2870	struct init_if_mode_op {
2830		- u32 op_data;
2831		-#define INIT_IF_MODE_OP_OP_MASK 0xF
2832		-#define INIT_IF_MODE_OP_OP_SHIFT 0
2833		-#define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
2834		-#define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
2835		-#define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
2836		-#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
2837		- u16 reserved2;
2838		- u16 modes_buf_offset;
	2871	+ __le32 op_data;
	2872	+#define INIT_IF_MODE_OP_OP_MASK 0xF
	2873	+#define INIT_IF_MODE_OP_OP_SHIFT 0
	2874	+#define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
	2875	+#define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
	2876	+#define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
	2877	+#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
	2878	+ __le16 reserved2;
	2879	+ __le16 modes_buf_offset;
2839	2880	};
2840	2881
2841	2882	/* init operation: if_phase */
2842	2883	struct init_if_phase_op {
2843		- u32 op_data;
2844		-#define INIT_IF_PHASE_OP_OP_MASK 0xF
2845		-#define INIT_IF_PHASE_OP_OP_SHIFT 0
2846		-#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
2847		-#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
2848		-#define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
2849		-#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
2850		-#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
2851		-#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
2852		- u32 phase_data;
2853		-#define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
2854		-#define INIT_IF_PHASE_OP_PHASE_SHIFT 0
2855		-#define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
2856		-#define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
2857		-#define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
2858		-#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
	2884	+ __le32 op_data;
	2885	+#define INIT_IF_PHASE_OP_OP_MASK 0xF
	2886	+#define INIT_IF_PHASE_OP_OP_SHIFT 0
	2887	+#define INIT_IF_PHASE_OP_RESERVED1_MASK 0xFFF
	2888	+#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 4
	2889	+#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
	2890	+#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
	2891	+ __le32 phase_data;
	2892	+#define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
	2893	+#define INIT_IF_PHASE_OP_PHASE_SHIFT 0
	2894	+#define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
	2895	+#define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
	2896	+#define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
	2897	+#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
2859	2898	};
2860	2899
2861	2900	/* init mode operators */
..	..	@@ -2868,67 +2907,67 @@
2868	2907
2869	2908	/* init operation: raw */
2870	2909	struct init_raw_op {
2871		- u32 op_data;
2872		-#define INIT_RAW_OP_OP_MASK 0xF
2873		-#define INIT_RAW_OP_OP_SHIFT 0
2874		-#define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
2875		-#define INIT_RAW_OP_PARAM1_SHIFT 4
2876		- u32 param2;
	2910	+ __le32 op_data;
	2911	+#define INIT_RAW_OP_OP_MASK 0xF
	2912	+#define INIT_RAW_OP_OP_SHIFT 0
	2913	+#define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
	2914	+#define INIT_RAW_OP_PARAM1_SHIFT 4
	2915	+ __le32 param2;
2877	2916	};
2878	2917
2879	2918	/* init array params */
2880	2919	struct init_op_array_params {
2881		- u16 size;
2882		- u16 offset;
	2920	+ __le16 size;
	2921	+ __le16 offset;
2883	2922	};
2884	2923
2885	2924	/* Write init operation arguments */
2886	2925	union init_write_args {
2887		- u32 inline_val;
2888		- u32 zeros_count;
2889		- u32 array_offset;
2890		- struct init_op_array_params runtime;
	2926	+ __le32 inline_val;
	2927	+ __le32 zeros_count;
	2928	+ __le32 array_offset;
	2929	+ struct init_op_array_params runtime;
2891	2930	};
2892	2931
2893	2932	/* init operation: write */
2894	2933	struct init_write_op {
2895		- u32 data;
2896		-#define INIT_WRITE_OP_OP_MASK 0xF
2897		-#define INIT_WRITE_OP_OP_SHIFT 0
2898		-#define INIT_WRITE_OP_SOURCE_MASK 0x7
2899		-#define INIT_WRITE_OP_SOURCE_SHIFT 4
2900		-#define INIT_WRITE_OP_RESERVED_MASK 0x1
2901		-#define INIT_WRITE_OP_RESERVED_SHIFT 7
2902		-#define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
2903		-#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
2904		-#define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
2905		-#define INIT_WRITE_OP_ADDRESS_SHIFT 9
2906		- union init_write_args args;
	2934	+ __le32 data;
	2935	+#define INIT_WRITE_OP_OP_MASK 0xF
	2936	+#define INIT_WRITE_OP_OP_SHIFT 0
	2937	+#define INIT_WRITE_OP_SOURCE_MASK 0x7
	2938	+#define INIT_WRITE_OP_SOURCE_SHIFT 4
	2939	+#define INIT_WRITE_OP_RESERVED_MASK 0x1
	2940	+#define INIT_WRITE_OP_RESERVED_SHIFT 7
	2941	+#define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
	2942	+#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
	2943	+#define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
	2944	+#define INIT_WRITE_OP_ADDRESS_SHIFT 9
	2945	+ union init_write_args args;
2907	2946	};
2908	2947
2909	2948	/* init operation: read */
2910	2949	struct init_read_op {
2911		- u32 op_data;
2912		-#define INIT_READ_OP_OP_MASK 0xF
2913		-#define INIT_READ_OP_OP_SHIFT 0
2914		-#define INIT_READ_OP_POLL_TYPE_MASK 0xF
2915		-#define INIT_READ_OP_POLL_TYPE_SHIFT 4
2916		-#define INIT_READ_OP_RESERVED_MASK 0x1
2917		-#define INIT_READ_OP_RESERVED_SHIFT 8
2918		-#define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
2919		-#define INIT_READ_OP_ADDRESS_SHIFT 9
2920		- u32 expected_val;
	2950	+ __le32 op_data;
	2951	+#define INIT_READ_OP_OP_MASK 0xF
	2952	+#define INIT_READ_OP_OP_SHIFT 0
	2953	+#define INIT_READ_OP_POLL_TYPE_MASK 0xF
	2954	+#define INIT_READ_OP_POLL_TYPE_SHIFT 4
	2955	+#define INIT_READ_OP_RESERVED_MASK 0x1
	2956	+#define INIT_READ_OP_RESERVED_SHIFT 8
	2957	+#define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
	2958	+#define INIT_READ_OP_ADDRESS_SHIFT 9
	2959	+ __le32 expected_val;
2921	2960	};
2922	2961
2923	2962	/* Init operations union */
2924	2963	union init_op {
2925		- struct init_raw_op raw;
2926		- struct init_write_op write;
2927		- struct init_read_op read;
2928		- struct init_if_mode_op if_mode;
2929		- struct init_if_phase_op if_phase;
2930		- struct init_callback_op callback;
2931		- struct init_delay_op delay;
	2964	+ struct init_raw_op raw;
	2965	+ struct init_write_op write;
	2966	+ struct init_read_op read;
	2967	+ struct init_if_mode_op if_mode;
	2968	+ struct init_if_phase_op if_phase;
	2969	+ struct init_callback_op callback;
	2970	+ struct init_delay_op delay;
2932	2971	};
2933	2972
2934	2973	/* Init command operation types */
..	..	@@ -2975,9 +3014,11 @@
2975	3014	* @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
2976	3015	* arrays.
2977	3016	*
	3017	+ * @param p_hwfn - HW device data
2978	3018	* @param bin_ptr - a pointer to the binary data with debug arrays.
2979	3019	*/
2980		-enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr);
	3020	+enum dbg_status qed_dbg_set_bin_ptr(struct qed_hwfn *p_hwfn,
	3021	+ const u8 * const bin_ptr);
2981	3022
2982	3023	/**
2983	3024	* @brief qed_read_regs - Reads registers into a buffer (using GRC).
..	..	@@ -3008,6 +3049,20 @@
3008	3049	*/
3009	3050	bool qed_read_fw_info(struct qed_hwfn *p_hwfn,
3010	3051	struct qed_ptt p_ptt, struct fw_info fw_info);
	3052	+/**
	3053	+ * @brief qed_dbg_grc_config - Sets the value of a GRC parameter.
	3054	+ *
	3055	+ * @param p_hwfn - HW device data
	3056	+ * @param grc_param - GRC parameter
	3057	+ * @param val - Value to set.
	3058	+ *
	3059	+ * @return error if one of the following holds:
	3060	+ * - the version wasn't set
	3061	+ * - grc_param is invalid
	3062	+ * - val is outside the allowed boundaries
	3063	+ */
	3064	+enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn,
	3065	+ enum dbg_grc_params grc_param, u32 val);
3011	3066
3012	3067	/**
3013	3068	* @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
..	..	@@ -3322,6 +3377,41 @@
3322	3377	enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
3323	3378	struct dbg_attn_block_result *results);
3324	3379
	3380	+/***************************** Data Types ********************************/
	3381	+
	3382	+struct mcp_trace_format {
	3383	+ u32 data;
	3384	+#define MCP_TRACE_FORMAT_MODULE_MASK 0x0000ffff
	3385	+#define MCP_TRACE_FORMAT_MODULE_OFFSET 0
	3386	+#define MCP_TRACE_FORMAT_LEVEL_MASK 0x00030000
	3387	+#define MCP_TRACE_FORMAT_LEVEL_OFFSET 16
	3388	+#define MCP_TRACE_FORMAT_P1_SIZE_MASK 0x000c0000
	3389	+#define MCP_TRACE_FORMAT_P1_SIZE_OFFSET 18
	3390	+#define MCP_TRACE_FORMAT_P2_SIZE_MASK 0x00300000
	3391	+#define MCP_TRACE_FORMAT_P2_SIZE_OFFSET 20
	3392	+#define MCP_TRACE_FORMAT_P3_SIZE_MASK 0x00c00000
	3393	+#define MCP_TRACE_FORMAT_P3_SIZE_OFFSET 22
	3394	+#define MCP_TRACE_FORMAT_LEN_MASK 0xff000000
	3395	+#define MCP_TRACE_FORMAT_LEN_OFFSET 24
	3396	+
	3397	+ char *format_str;
	3398	+};
	3399	+
	3400	+/* MCP Trace Meta data structure */
	3401	+struct mcp_trace_meta {
	3402	+ u32 modules_num;
	3403	+ char **modules;
	3404	+ u32 formats_num;
	3405	+ struct mcp_trace_format *formats;
	3406	+ bool is_allocated;
	3407	+};
	3408	+
	3409	+/* Debug Tools user data */
	3410	+struct dbg_tools_user_data {
	3411	+ struct mcp_trace_meta mcp_trace_meta;
	3412	+ const u32 *mcp_trace_user_meta_buf;
	3413	+};
	3414	+
3325	3415	/****************************** Constants ********************************/
3326	3416
3327	3417	#define MAX_NAME_LEN 16
..	..	@@ -3332,9 +3422,20 @@
3332	3422	* @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
3333	3423	* debug arrays.
3334	3424	*
	3425	+ * @param p_hwfn - HW device data
3335	3426	* @param bin_ptr - a pointer to the binary data with debug arrays.
3336	3427	*/
3337		-enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr);
	3428	+enum dbg_status qed_dbg_user_set_bin_ptr(struct qed_hwfn *p_hwfn,
	3429	+ const u8 * const bin_ptr);
	3430	+
	3431	+/**
	3432	+ * @brief qed_dbg_alloc_user_data - Allocates user debug data.
	3433	+ *
	3434	+ * @param p_hwfn - HW device data
	3435	+ * @param user_data_ptr - OUT: a pointer to the allocated memory.
	3436	+ */
	3437	+enum dbg_status qed_dbg_alloc_user_data(struct qed_hwfn *p_hwfn,
	3438	+ void **user_data_ptr);
3338	3439
3339	3440	/**
3340	3441	* @brief qed_dbg_get_status_str - Returns a string for the specified status.
..	..	@@ -3381,8 +3482,7 @@
3381	3482	u32 *num_warnings);
3382	3483
3383	3484	/**
3384		- * @brief qed_dbg_mcp_trace_set_meta_data - Sets a pointer to the MCP Trace
3385		- * meta data.
	3485	+ * @brief qed_dbg_mcp_trace_set_meta_data - Sets the MCP Trace meta data.
3386	3486	*
3387	3487	* Needed in case the MCP Trace dump doesn't contain the meta data (e.g. due to
3388	3488	* no NVRAM access).
..	..	@@ -3390,7 +3490,8 @@
3390	3490	* @param data - pointer to MCP Trace meta data
3391	3491	* @param size - size of MCP Trace meta data in dwords
3392	3492	*/
3393		-void qed_dbg_mcp_trace_set_meta_data(u32 *data, u32 size);
	3493	+void qed_dbg_mcp_trace_set_meta_data(struct qed_hwfn *p_hwfn,
	3494	+ const u32 *meta_buf);
3394	3495
3395	3496	/**
3396	3497	* @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size
..	..	@@ -3425,17 +3526,43 @@
3425	3526	char *results_buf);
3426	3527
3427	3528	/**
	3529	+ * @brief qed_print_mcp_trace_results_cont - Prints MCP Trace results, and
	3530	+ * keeps the MCP trace meta data allocated, to support continuous MCP Trace
	3531	+ * parsing. After the continuous parsing ends, mcp_trace_free_meta_data should
	3532	+ * be called to free the meta data.
	3533	+ *
	3534	+ * @param p_hwfn - HW device data
	3535	+ * @param dump_buf - mcp trace dump buffer, starting from the header.
	3536	+ * @param results_buf - buffer for printing the mcp trace results.
	3537	+ *
	3538	+ * @return error if the parsing fails, ok otherwise.
	3539	+ */
	3540	+enum dbg_status qed_print_mcp_trace_results_cont(struct qed_hwfn *p_hwfn,
	3541	+ u32 *dump_buf,
	3542	+ char *results_buf);
	3543	+
	3544	+/**
3428	3545	* @brief print_mcp_trace_line - Prints MCP Trace results for a single line
3429	3546	*
	3547	+ * @param p_hwfn - HW device data
3430	3548	* @param dump_buf - mcp trace dump buffer, starting from the header.
3431	3549	* @param num_dumped_bytes - number of bytes that were dumped.
3432	3550	* @param results_buf - buffer for printing the mcp trace results.
3433	3551	*
3434	3552	* @return error if the parsing fails, ok otherwise.
3435	3553	*/
3436		-enum dbg_status qed_print_mcp_trace_line(u8 *dump_buf,
	3554	+enum dbg_status qed_print_mcp_trace_line(struct qed_hwfn *p_hwfn,
	3555	+ u8 *dump_buf,
3437	3556	u32 num_dumped_bytes,
3438	3557	char *results_buf);
	3558	+
	3559	+/**
	3560	+ * @brief mcp_trace_free_meta_data - Frees the MCP Trace meta data.
	3561	+ * Should be called after continuous MCP Trace parsing.
	3562	+ *
	3563	+ * @param p_hwfn - HW device data
	3564	+ */
	3565	+void qed_mcp_trace_free_meta_data(struct qed_hwfn *p_hwfn);
3439	3566
3440	3567	/**
3441	3568	* @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size
..	..	@@ -3581,271 +3708,6 @@
3581	3708	enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
3582	3709	struct dbg_attn_block_result *results);
3583	3710
3584		-/* Debug Bus blocks */
3585		-static const u32 dbg_bus_blocks[] = {
3586		- 0x0000000f, /* grc, bb, 15 lines */
3587		- 0x0000000f, /* grc, k2, 15 lines */
3588		- 0x00000000,
3589		- 0x00000000, /* miscs, bb, 0 lines */
3590		- 0x00000000, /* miscs, k2, 0 lines */
3591		- 0x00000000,
3592		- 0x00000000, /* misc, bb, 0 lines */
3593		- 0x00000000, /* misc, k2, 0 lines */
3594		- 0x00000000,
3595		- 0x00000000, /* dbu, bb, 0 lines */
3596		- 0x00000000, /* dbu, k2, 0 lines */
3597		- 0x00000000,
3598		- 0x000f0127, /* pglue_b, bb, 39 lines */
3599		- 0x0036012a, /* pglue_b, k2, 42 lines */
3600		- 0x00000000,
3601		- 0x00000000, /* cnig, bb, 0 lines */
3602		- 0x00120102, /* cnig, k2, 2 lines */
3603		- 0x00000000,
3604		- 0x00000000, /* cpmu, bb, 0 lines */
3605		- 0x00000000, /* cpmu, k2, 0 lines */
3606		- 0x00000000,
3607		- 0x00000001, /* ncsi, bb, 1 lines */
3608		- 0x00000001, /* ncsi, k2, 1 lines */
3609		- 0x00000000,
3610		- 0x00000000, /* opte, bb, 0 lines */
3611		- 0x00000000, /* opte, k2, 0 lines */
3612		- 0x00000000,
3613		- 0x00600085, /* bmb, bb, 133 lines */
3614		- 0x00600085, /* bmb, k2, 133 lines */
3615		- 0x00000000,
3616		- 0x00000000, /* pcie, bb, 0 lines */
3617		- 0x00e50033, /* pcie, k2, 51 lines */
3618		- 0x00000000,
3619		- 0x00000000, /* mcp, bb, 0 lines */
3620		- 0x00000000, /* mcp, k2, 0 lines */
3621		- 0x00000000,
3622		- 0x01180009, /* mcp2, bb, 9 lines */
3623		- 0x01180009, /* mcp2, k2, 9 lines */
3624		- 0x00000000,
3625		- 0x01210104, /* pswhst, bb, 4 lines */
3626		- 0x01210104, /* pswhst, k2, 4 lines */
3627		- 0x00000000,
3628		- 0x01250103, /* pswhst2, bb, 3 lines */
3629		- 0x01250103, /* pswhst2, k2, 3 lines */
3630		- 0x00000000,
3631		- 0x00340101, /* pswrd, bb, 1 lines */
3632		- 0x00340101, /* pswrd, k2, 1 lines */
3633		- 0x00000000,
3634		- 0x01280119, /* pswrd2, bb, 25 lines */
3635		- 0x01280119, /* pswrd2, k2, 25 lines */
3636		- 0x00000000,
3637		- 0x01410109, /* pswwr, bb, 9 lines */
3638		- 0x01410109, /* pswwr, k2, 9 lines */
3639		- 0x00000000,
3640		- 0x00000000, /* pswwr2, bb, 0 lines */
3641		- 0x00000000, /* pswwr2, k2, 0 lines */
3642		- 0x00000000,
3643		- 0x001c0001, /* pswrq, bb, 1 lines */
3644		- 0x001c0001, /* pswrq, k2, 1 lines */
3645		- 0x00000000,
3646		- 0x014a0015, /* pswrq2, bb, 21 lines */
3647		- 0x014a0015, /* pswrq2, k2, 21 lines */
3648		- 0x00000000,
3649		- 0x00000000, /* pglcs, bb, 0 lines */
3650		- 0x00120006, /* pglcs, k2, 6 lines */
3651		- 0x00000000,
3652		- 0x00100001, /* dmae, bb, 1 lines */
3653		- 0x00100001, /* dmae, k2, 1 lines */
3654		- 0x00000000,
3655		- 0x015f0105, /* ptu, bb, 5 lines */
3656		- 0x015f0105, /* ptu, k2, 5 lines */
3657		- 0x00000000,
3658		- 0x01640120, /* tcm, bb, 32 lines */
3659		- 0x01640120, /* tcm, k2, 32 lines */
3660		- 0x00000000,
3661		- 0x01640120, /* mcm, bb, 32 lines */
3662		- 0x01640120, /* mcm, k2, 32 lines */
3663		- 0x00000000,
3664		- 0x01640120, /* ucm, bb, 32 lines */
3665		- 0x01640120, /* ucm, k2, 32 lines */
3666		- 0x00000000,
3667		- 0x01640120, /* xcm, bb, 32 lines */
3668		- 0x01640120, /* xcm, k2, 32 lines */
3669		- 0x00000000,
3670		- 0x01640120, /* ycm, bb, 32 lines */
3671		- 0x01640120, /* ycm, k2, 32 lines */
3672		- 0x00000000,
3673		- 0x01640120, /* pcm, bb, 32 lines */
3674		- 0x01640120, /* pcm, k2, 32 lines */
3675		- 0x00000000,
3676		- 0x01840062, /* qm, bb, 98 lines */
3677		- 0x01840062, /* qm, k2, 98 lines */
3678		- 0x00000000,
3679		- 0x01e60021, /* tm, bb, 33 lines */
3680		- 0x01e60021, /* tm, k2, 33 lines */
3681		- 0x00000000,
3682		- 0x02070107, /* dorq, bb, 7 lines */
3683		- 0x02070107, /* dorq, k2, 7 lines */
3684		- 0x00000000,
3685		- 0x00600185, /* brb, bb, 133 lines */
3686		- 0x00600185, /* brb, k2, 133 lines */
3687		- 0x00000000,
3688		- 0x020e0019, /* src, bb, 25 lines */
3689		- 0x020c001a, /* src, k2, 26 lines */
3690		- 0x00000000,
3691		- 0x02270104, /* prs, bb, 4 lines */
3692		- 0x02270104, /* prs, k2, 4 lines */
3693		- 0x00000000,
3694		- 0x022b0133, /* tsdm, bb, 51 lines */
3695		- 0x022b0133, /* tsdm, k2, 51 lines */
3696		- 0x00000000,
3697		- 0x022b0133, /* msdm, bb, 51 lines */
3698		- 0x022b0133, /* msdm, k2, 51 lines */
3699		- 0x00000000,
3700		- 0x022b0133, /* usdm, bb, 51 lines */
3701		- 0x022b0133, /* usdm, k2, 51 lines */
3702		- 0x00000000,
3703		- 0x022b0133, /* xsdm, bb, 51 lines */
3704		- 0x022b0133, /* xsdm, k2, 51 lines */
3705		- 0x00000000,
3706		- 0x022b0133, /* ysdm, bb, 51 lines */
3707		- 0x022b0133, /* ysdm, k2, 51 lines */
3708		- 0x00000000,
3709		- 0x022b0133, /* psdm, bb, 51 lines */
3710		- 0x022b0133, /* psdm, k2, 51 lines */
3711		- 0x00000000,
3712		- 0x025e010c, /* tsem, bb, 12 lines */
3713		- 0x025e010c, /* tsem, k2, 12 lines */
3714		- 0x00000000,
3715		- 0x025e010c, /* msem, bb, 12 lines */
3716		- 0x025e010c, /* msem, k2, 12 lines */
3717		- 0x00000000,
3718		- 0x025e010c, /* usem, bb, 12 lines */
3719		- 0x025e010c, /* usem, k2, 12 lines */
3720		- 0x00000000,
3721		- 0x025e010c, /* xsem, bb, 12 lines */
3722		- 0x025e010c, /* xsem, k2, 12 lines */
3723		- 0x00000000,
3724		- 0x025e010c, /* ysem, bb, 12 lines */
3725		- 0x025e010c, /* ysem, k2, 12 lines */
3726		- 0x00000000,
3727		- 0x025e010c, /* psem, bb, 12 lines */
3728		- 0x025e010c, /* psem, k2, 12 lines */
3729		- 0x00000000,
3730		- 0x026a000d, /* rss, bb, 13 lines */
3731		- 0x026a000d, /* rss, k2, 13 lines */
3732		- 0x00000000,
3733		- 0x02770106, /* tmld, bb, 6 lines */
3734		- 0x02770106, /* tmld, k2, 6 lines */
3735		- 0x00000000,
3736		- 0x027d0106, /* muld, bb, 6 lines */
3737		- 0x027d0106, /* muld, k2, 6 lines */
3738		- 0x00000000,
3739		- 0x02770005, /* yuld, bb, 5 lines */
3740		- 0x02770005, /* yuld, k2, 5 lines */
3741		- 0x00000000,
3742		- 0x02830107, /* xyld, bb, 7 lines */
3743		- 0x027d0107, /* xyld, k2, 7 lines */
3744		- 0x00000000,
3745		- 0x00000000, /* ptld, bb, 0 lines */
3746		- 0x00000000, /* ptld, k2, 0 lines */
3747		- 0x00000000,
3748		- 0x00000000, /* ypld, bb, 0 lines */
3749		- 0x00000000, /* ypld, k2, 0 lines */
3750		- 0x00000000,
3751		- 0x028a010e, /* prm, bb, 14 lines */
3752		- 0x02980110, /* prm, k2, 16 lines */
3753		- 0x00000000,
3754		- 0x02a8000d, /* pbf_pb1, bb, 13 lines */
3755		- 0x02a8000d, /* pbf_pb1, k2, 13 lines */
3756		- 0x00000000,
3757		- 0x02a8000d, /* pbf_pb2, bb, 13 lines */
3758		- 0x02a8000d, /* pbf_pb2, k2, 13 lines */
3759		- 0x00000000,
3760		- 0x02a8000d, /* rpb, bb, 13 lines */
3761		- 0x02a8000d, /* rpb, k2, 13 lines */
3762		- 0x00000000,
3763		- 0x00600185, /* btb, bb, 133 lines */
3764		- 0x00600185, /* btb, k2, 133 lines */
3765		- 0x00000000,
3766		- 0x02b50117, /* pbf, bb, 23 lines */
3767		- 0x02b50117, /* pbf, k2, 23 lines */
3768		- 0x00000000,
3769		- 0x02cc0006, /* rdif, bb, 6 lines */
3770		- 0x02cc0006, /* rdif, k2, 6 lines */
3771		- 0x00000000,
3772		- 0x02d20006, /* tdif, bb, 6 lines */
3773		- 0x02d20006, /* tdif, k2, 6 lines */
3774		- 0x00000000,
3775		- 0x02d80003, /* cdu, bb, 3 lines */
3776		- 0x02db000e, /* cdu, k2, 14 lines */
3777		- 0x00000000,
3778		- 0x02e9010d, /* ccfc, bb, 13 lines */
3779		- 0x02f60117, /* ccfc, k2, 23 lines */
3780		- 0x00000000,
3781		- 0x02e9010d, /* tcfc, bb, 13 lines */
3782		- 0x02f60117, /* tcfc, k2, 23 lines */
3783		- 0x00000000,
3784		- 0x030d0133, /* igu, bb, 51 lines */
3785		- 0x030d0133, /* igu, k2, 51 lines */
3786		- 0x00000000,
3787		- 0x03400106, /* cau, bb, 6 lines */
3788		- 0x03400106, /* cau, k2, 6 lines */
3789		- 0x00000000,
3790		- 0x00000000, /* rgfs, bb, 0 lines */
3791		- 0x00000000, /* rgfs, k2, 0 lines */
3792		- 0x00000000,
3793		- 0x00000000, /* rgsrc, bb, 0 lines */
3794		- 0x00000000, /* rgsrc, k2, 0 lines */
3795		- 0x00000000,
3796		- 0x00000000, /* tgfs, bb, 0 lines */
3797		- 0x00000000, /* tgfs, k2, 0 lines */
3798		- 0x00000000,
3799		- 0x00000000, /* tgsrc, bb, 0 lines */
3800		- 0x00000000, /* tgsrc, k2, 0 lines */
3801		- 0x00000000,
3802		- 0x00000000, /* umac, bb, 0 lines */
3803		- 0x00120006, /* umac, k2, 6 lines */
3804		- 0x00000000,
3805		- 0x00000000, /* xmac, bb, 0 lines */
3806		- 0x00000000, /* xmac, k2, 0 lines */
3807		- 0x00000000,
3808		- 0x00000000, /* dbg, bb, 0 lines */
3809		- 0x00000000, /* dbg, k2, 0 lines */
3810		- 0x00000000,
3811		- 0x0346012b, /* nig, bb, 43 lines */
3812		- 0x0346011d, /* nig, k2, 29 lines */
3813		- 0x00000000,
3814		- 0x00000000, /* wol, bb, 0 lines */
3815		- 0x001c0002, /* wol, k2, 2 lines */
3816		- 0x00000000,
3817		- 0x00000000, /* bmbn, bb, 0 lines */
3818		- 0x00210008, /* bmbn, k2, 8 lines */
3819		- 0x00000000,
3820		- 0x00000000, /* ipc, bb, 0 lines */
3821		- 0x00000000, /* ipc, k2, 0 lines */
3822		- 0x00000000,
3823		- 0x00000000, /* nwm, bb, 0 lines */
3824		- 0x0371000b, /* nwm, k2, 11 lines */
3825		- 0x00000000,
3826		- 0x00000000, /* nws, bb, 0 lines */
3827		- 0x037c0009, /* nws, k2, 9 lines */
3828		- 0x00000000,
3829		- 0x00000000, /* ms, bb, 0 lines */
3830		- 0x00120004, /* ms, k2, 4 lines */
3831		- 0x00000000,
3832		- 0x00000000, /* phy_pcie, bb, 0 lines */
3833		- 0x00e5001a, /* phy_pcie, k2, 26 lines */
3834		- 0x00000000,
3835		- 0x00000000, /* led, bb, 0 lines */
3836		- 0x00000000, /* led, k2, 0 lines */
3837		- 0x00000000,
3838		- 0x00000000, /* avs_wrap, bb, 0 lines */
3839		- 0x00000000, /* avs_wrap, k2, 0 lines */
3840		- 0x00000000,
3841		- 0x00000000, /* bar0_map, bb, 0 lines */
3842		- 0x00000000, /* bar0_map, k2, 0 lines */
3843		- 0x00000000,
3844		- 0x00000000, /* bar0_map, bb, 0 lines */
3845		- 0x00000000, /* bar0_map, k2, 0 lines */
3846		- 0x00000000,
3847		-};
3848		-
3849	3711	/* Win 2 */
3850	3712	#define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
3851	3713
..	..	@@ -3859,22 +3721,28 @@
3859	3721	#define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
3860	3722
3861	3723	/* Win 6 */
3862		-#define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL
	3724	+#define GTT_BAR0_MAP_REG_MSDM_RAM_2048 0x013000UL
3863	3725
3864	3726	/* Win 7 */
3865		-#define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL
	3727	+#define GTT_BAR0_MAP_REG_USDM_RAM 0x014000UL
3866	3728
3867	3729	/* Win 8 */
3868		-#define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL
	3730	+#define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x015000UL
3869	3731
3870	3732	/* Win 9 */
3871		-#define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL
	3733	+#define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x016000UL
3872	3734
3873	3735	/* Win 10 */
3874		-#define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL
	3736	+#define GTT_BAR0_MAP_REG_XSDM_RAM 0x017000UL
3875	3737
3876	3738	/* Win 11 */
3877		-#define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL
	3739	+#define GTT_BAR0_MAP_REG_XSDM_RAM_1024 0x018000UL
	3740	+
	3741	+/* Win 12 */
	3742	+#define GTT_BAR0_MAP_REG_YSDM_RAM 0x019000UL
	3743	+
	3744	+/* Win 13 */
	3745	+#define GTT_BAR0_MAP_REG_PSDM_RAM 0x01a000UL
3878	3746
3879	3747	/**
3880	3748	* @brief qed_qm_pf_mem_size - prepare QM ILT sizes
..	..	@@ -3899,7 +3767,7 @@
3899	3767	u8 max_phys_tcs_per_port;
3900	3768	bool pf_rl_en;
3901	3769	bool pf_wfq_en;
3902		- bool vport_rl_en;
	3770	+ bool global_rl_en;
3903	3771	bool vport_wfq_en;
3904	3772	struct init_qm_port_params *port_params;
3905	3773	};
..	..	@@ -3918,11 +3786,10 @@
3918	3786	u16 start_pq;
3919	3787	u16 num_pf_pqs;
3920	3788	u16 num_vf_pqs;
3921		- u8 start_vport;
3922		- u8 num_vports;
	3789	+ u16 start_vport;
	3790	+ u16 num_vports;
3923	3791	u16 pf_wfq;
3924	3792	u32 pf_rl;
3925		- u32 link_speed;
3926	3793	struct init_qm_pq_params *pq_params;
3927	3794	struct init_qm_vport_params *vport_params;
3928	3795	};
..	..	@@ -3971,22 +3838,22 @@
3971	3838	*/
3972	3839	int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
3973	3840	struct qed_ptt *p_ptt,
3974		- u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);
	3841	+ u16 first_tx_pq_id[NUM_OF_TCS], u16 wfq);
3975	3842
3976	3843	/**
3977		- * @brief qed_init_vport_rl - Initializes the rate limit of the specified VPORT
	3844	+ * @brief qed_init_global_rl - Initializes the rate limit of the specified
	3845	+ * rate limiter
3978	3846	*
3979	3847	* @param p_hwfn
3980	3848	* @param p_ptt - ptt window used for writing the registers
3981		- * @param vport_id - VPORT ID
3982		- * @param vport_rl - rate limit in Mb/sec units
3983		- * @param link_speed - link speed in Mbps.
	3849	+ * @param rl_id - RL ID
	3850	+ * @param rate_limit - rate limit in Mb/sec units
3984	3851	*
3985	3852	* @return 0 on success, -1 on error.
3986	3853	*/
3987		-int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
3988		- struct qed_ptt *p_ptt,
3989		- u8 vport_id, u32 vport_rl, u32 link_speed);
	3854	+int qed_init_global_rl(struct qed_hwfn *p_hwfn,
	3855	+ struct qed_ptt *p_ptt,
	3856	+ u16 rl_id, u32 rate_limit);
3990	3857
3991	3858	/**
3992	3859	* @brief qed_send_qm_stop_cmd Sends a stop command to the QM
..	..	@@ -4074,7 +3941,7 @@
4074	3941	/**
4075	3942	* @brief qed_gft_config - Enable and configure HW for GFT
4076	3943	*
4077		- * @param p_hwfn
	3944	+ * @param p_hwfn - HW device data
4078	3945	* @param p_ptt - ptt window used for writing the registers.
4079	3946	* @param pf_id - pf on which to enable GFT.
4080	3947	* @param tcp - set profile tcp packets.
..	..	@@ -4159,6 +4026,42 @@
4159	4026	void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn,
4160	4027	struct qed_ptt *p_ptt,
4161	4028	u8 assert_level[NUM_STORMS]);
	4029	+/**
	4030	+ * @brief qed_fw_overlay_mem_alloc - Allocates and fills the FW overlay memory.
	4031	+ *
	4032	+ * @param p_hwfn - HW device data
	4033	+ * @param fw_overlay_in_buf - the input FW overlay buffer.
	4034	+ * @param buf_size - the size of the input FW overlay buffer in bytes.
	4035	+ * must be aligned to dwords.
	4036	+ * @param fw_overlay_out_mem - OUT: a pointer to the allocated overlays memory.
	4037	+ *
	4038	+ * @return a pointer to the allocated overlays memory,
	4039	+ * or NULL in case of failures.
	4040	+ */
	4041	+struct phys_mem_desc *
	4042	+qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn,
	4043	+ const u32 * const fw_overlay_in_buf,
	4044	+ u32 buf_size_in_bytes);
	4045	+
	4046	+/**
	4047	+ * @brief qed_fw_overlay_init_ram - Initializes the FW overlay RAM.
	4048	+ *
	4049	+ * @param p_hwfn - HW device data.
	4050	+ * @param p_ptt - ptt window used for writing the registers.
	4051	+ * @param fw_overlay_mem - the allocated FW overlay memory.
	4052	+ */
	4053	+void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn,
	4054	+ struct qed_ptt *p_ptt,
	4055	+ struct phys_mem_desc *fw_overlay_mem);
	4056	+
	4057	+/**
	4058	+ * @brief qed_fw_overlay_mem_free - Frees the FW overlay memory.
	4059	+ *
	4060	+ * @param p_hwfn - HW device data.
	4061	+ * @param fw_overlay_mem - the allocated FW overlay memory to free.
	4062	+ */
	4063	+void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn,
	4064	+ struct phys_mem_desc *fw_overlay_mem);
4162	4065
4163	4066	/* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
4164	4067	#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
..	..	@@ -4199,843 +4102,734 @@
4199	4102	(IRO[7].base + ((queue_zone_id) * IRO[7].m1))
4200	4103	#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
4201	4104
	4105	+/* Xstorm common PQ info */
	4106	+#define XSTORM_PQ_INFO_OFFSET(pq_id) \
	4107	+ (IRO[8].base + ((pq_id) * IRO[8].m1))
	4108	+#define XSTORM_PQ_INFO_SIZE (IRO[8].size)
	4109	+
4202	4110	/* Xstorm Integration Test Data */
4203		-#define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[8].base)
4204		-#define XSTORM_INTEG_TEST_DATA_SIZE (IRO[8].size)
	4111	+#define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
	4112	+#define XSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size)
4205	4113
4206	4114	/* Ystorm Integration Test Data */
4207		-#define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
4208		-#define YSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size)
	4115	+#define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
	4116	+#define YSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size)
4209	4117
4210	4118	/* Pstorm Integration Test Data */
4211		-#define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
4212		-#define PSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size)
	4119	+#define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
	4120	+#define PSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size)
4213	4121
4214	4122	/* Tstorm Integration Test Data */
4215		-#define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
4216		-#define TSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size)
	4123	+#define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base)
	4124	+#define TSTORM_INTEG_TEST_DATA_SIZE (IRO[12].size)
4217	4125
4218	4126	/* Mstorm Integration Test Data */
4219		-#define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base)
4220		-#define MSTORM_INTEG_TEST_DATA_SIZE (IRO[12].size)
	4127	+#define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[13].base)
	4128	+#define MSTORM_INTEG_TEST_DATA_SIZE (IRO[13].size)
4221	4129
4222	4130	/* Ustorm Integration Test Data */
4223		-#define USTORM_INTEG_TEST_DATA_OFFSET (IRO[13].base)
4224		-#define USTORM_INTEG_TEST_DATA_SIZE (IRO[13].size)
	4131	+#define USTORM_INTEG_TEST_DATA_OFFSET (IRO[14].base)
	4132	+#define USTORM_INTEG_TEST_DATA_SIZE (IRO[14].size)
	4133	+
	4134	+/* Xstorm overlay buffer host address */
	4135	+#define XSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[15].base)
	4136	+#define XSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[15].size)
	4137	+
	4138	+/* Ystorm overlay buffer host address */
	4139	+#define YSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[16].base)
	4140	+#define YSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[16].size)
	4141	+
	4142	+/* Pstorm overlay buffer host address */
	4143	+#define PSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[17].base)
	4144	+#define PSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[17].size)
	4145	+
	4146	+/* Tstorm overlay buffer host address */
	4147	+#define TSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[18].base)
	4148	+#define TSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[18].size)
	4149	+
	4150	+/* Mstorm overlay buffer host address */
	4151	+#define MSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[19].base)
	4152	+#define MSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[19].size)
	4153	+
	4154	+/* Ustorm overlay buffer host address */
	4155	+#define USTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[20].base)
	4156	+#define USTORM_OVERLAY_BUF_ADDR_SIZE (IRO[20].size)
4225	4157
4226	4158	/* Tstorm producers */
4227	4159	#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
4228		- (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
4229		-#define TSTORM_LL2_RX_PRODS_SIZE (IRO[14].size)
	4160	+ (IRO[21].base + ((core_rx_queue_id) * IRO[21].m1))
	4161	+#define TSTORM_LL2_RX_PRODS_SIZE (IRO[21].size)
4230	4162
4231	4163	/* Tstorm LightL2 queue statistics */
4232	4164	#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4233		- (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
4234		-#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[15].size)
	4165	+ (IRO[22].base + ((core_rx_queue_id) * IRO[22].m1))
	4166	+#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[22].size)
4235	4167
4236	4168	/* Ustorm LiteL2 queue statistics */
4237	4169	#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4238		- (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1))
4239		-#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[16].size)
	4170	+ (IRO[23].base + ((core_rx_queue_id) * IRO[23].m1))
	4171	+#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[23].size)
4240	4172
4241	4173	/* Pstorm LiteL2 queue statistics */
4242	4174	#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
4243		- (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1))
4244		-#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[17].size)
	4175	+ (IRO[24].base + ((core_tx_stats_id) * IRO[24].m1))
	4176	+#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[24].size)
4245	4177
4246	4178	/* Mstorm queue statistics */
4247	4179	#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4248		- (IRO[18].base + ((stat_counter_id) * IRO[18].m1))
4249		-#define MSTORM_QUEUE_STAT_SIZE (IRO[18].size)
	4180	+ (IRO[25].base + ((stat_counter_id) * IRO[25].m1))
	4181	+#define MSTORM_QUEUE_STAT_SIZE (IRO[25].size)
	4182	+
	4183	+/* TPA agregation timeout in us resolution (on ASIC) */
	4184	+#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[26].base)
	4185	+#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[26].size)
	4186	+
	4187	+/* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
	4188	+ * mode
	4189	+ */
	4190	+#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
	4191	+ (IRO[27].base + ((vf_id) * IRO[27].m1) + ((vf_queue_id) * IRO[27].m2))
	4192	+#define MSTORM_ETH_VF_PRODS_SIZE (IRO[27].size)
4250	4193
4251	4194	/* Mstorm ETH PF queues producers */
4252	4195	#define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
4253		- (IRO[19].base + ((queue_id) * IRO[19].m1))
4254		-#define MSTORM_ETH_PF_PRODS_SIZE (IRO[19].size)
4255		-
4256		-/* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
4257		- * mode.
4258		- */
4259		-#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
4260		- (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2))
4261		-#define MSTORM_ETH_VF_PRODS_SIZE (IRO[20].size)
4262		-
4263		-/* TPA agregation timeout in us resolution (on ASIC) */
4264		-#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base)
4265		-#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[21].size)
	4196	+ (IRO[28].base + ((queue_id) * IRO[28].m1))
	4197	+#define MSTORM_ETH_PF_PRODS_SIZE (IRO[28].size)
4266	4198
4267	4199	/* Mstorm pf statistics */
4268	4200	#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4269		- (IRO[22].base + ((pf_id) * IRO[22].m1))
4270		-#define MSTORM_ETH_PF_STAT_SIZE (IRO[22].size)
	4201	+ (IRO[29].base + ((pf_id) * IRO[29].m1))
	4202	+#define MSTORM_ETH_PF_STAT_SIZE (IRO[29].size)
4271	4203
4272	4204	/* Ustorm queue statistics */
4273	4205	#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4274		- (IRO[23].base + ((stat_counter_id) * IRO[23].m1))
4275		-#define USTORM_QUEUE_STAT_SIZE (IRO[23].size)
	4206	+ (IRO[30].base + ((stat_counter_id) * IRO[30].m1))
	4207	+#define USTORM_QUEUE_STAT_SIZE (IRO[30].size)
4276	4208
4277	4209	/* Ustorm pf statistics */
4278		-#define USTORM_ETH_PF_STAT_OFFSET(pf_id)\
4279		- (IRO[24].base + ((pf_id) * IRO[24].m1))
4280		-#define USTORM_ETH_PF_STAT_SIZE (IRO[24].size)
	4210	+#define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
	4211	+ (IRO[31].base + ((pf_id) * IRO[31].m1))
	4212	+#define USTORM_ETH_PF_STAT_SIZE (IRO[31].size)
4281	4213
4282	4214	/* Pstorm queue statistics */
4283		-#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4284		- (IRO[25].base + ((stat_counter_id) * IRO[25].m1))
4285		-#define PSTORM_QUEUE_STAT_SIZE (IRO[25].size)
	4215	+#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
	4216	+ (IRO[32].base + ((stat_counter_id) * IRO[32].m1))
	4217	+#define PSTORM_QUEUE_STAT_SIZE (IRO[32].size)
4286	4218
4287	4219	/* Pstorm pf statistics */
4288	4220	#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4289		- (IRO[26].base + ((pf_id) * IRO[26].m1))
4290		-#define PSTORM_ETH_PF_STAT_SIZE (IRO[26].size)
	4221	+ (IRO[33].base + ((pf_id) * IRO[33].m1))
	4222	+#define PSTORM_ETH_PF_STAT_SIZE (IRO[33].size)
4291	4223
4292	4224	/* Control frame's EthType configuration for TX control frame security */
4293		-#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(eth_type_id) \
4294		- (IRO[27].base + ((eth_type_id) * IRO[27].m1))
4295		-#define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[27].size)
	4225	+#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(eth_type_id) \
	4226	+ (IRO[34].base + ((eth_type_id) * IRO[34].m1))
	4227	+#define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[34].size)
4296	4228
4297	4229	/* Tstorm last parser message */
4298		-#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base)
4299		-#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[28].size)
	4230	+#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[35].base)
	4231	+#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[35].size)
4300	4232
4301	4233	/* Tstorm Eth limit Rx rate */
4302		-#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
4303		- (IRO[29].base + ((pf_id) * IRO[29].m1))
4304		-#define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size)
	4234	+#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
	4235	+ (IRO[36].base + ((pf_id) * IRO[36].m1))
	4236	+#define ETH_RX_RATE_LIMIT_SIZE (IRO[36].size)
	4237	+
	4238	+/* RSS indirection table entry update command per PF offset in TSTORM PF BAR0.
	4239	+ * Use eth_tstorm_rss_update_data for update
	4240	+ */
	4241	+#define TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id) \
	4242	+ (IRO[37].base + ((pf_id) * IRO[37].m1))
	4243	+#define TSTORM_ETH_RSS_UPDATE_SIZE (IRO[37].size)
4305	4244
4306	4245	/* Xstorm queue zone */
4307	4246	#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
4308		- (IRO[30].base + ((queue_id) * IRO[30].m1))
4309		-#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size)
	4247	+ (IRO[38].base + ((queue_id) * IRO[38].m1))
	4248	+#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[38].size)
4310	4249
4311	4250	/* Ystorm cqe producer */
4312	4251	#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
4313		- (IRO[31].base + ((rss_id) * IRO[31].m1))
4314		-#define YSTORM_TOE_CQ_PROD_SIZE (IRO[31].size)
	4252	+ (IRO[39].base + ((rss_id) * IRO[39].m1))
	4253	+#define YSTORM_TOE_CQ_PROD_SIZE (IRO[39].size)
4315	4254
4316	4255	/* Ustorm cqe producer */
4317	4256	#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
4318		- (IRO[32].base + ((rss_id) * IRO[32].m1))
4319		-#define USTORM_TOE_CQ_PROD_SIZE (IRO[32].size)
	4257	+ (IRO[40].base + ((rss_id) * IRO[40].m1))
	4258	+#define USTORM_TOE_CQ_PROD_SIZE (IRO[40].size)
4320	4259
4321	4260	/* Ustorm grq producer */
4322	4261	#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
4323		- (IRO[33].base + ((pf_id) * IRO[33].m1))
4324		-#define USTORM_TOE_GRQ_PROD_SIZE (IRO[33].size)
	4262	+ (IRO[41].base + ((pf_id) * IRO[41].m1))
	4263	+#define USTORM_TOE_GRQ_PROD_SIZE (IRO[41].size)
4325	4264
4326	4265	/* Tstorm cmdq-cons of given command queue-id */
4327	4266	#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
4328		- (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1))
4329		-#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size)
	4267	+ (IRO[42].base + ((cmdq_queue_id) * IRO[42].m1))
	4268	+#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[42].size)
4330	4269
4331	4270	/* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
4332		- * BDqueue-id.
	4271	+ * BDqueue-id
4333	4272	*/
4334		-#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
4335		- (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2))
4336		-#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size)
	4273	+#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
	4274	+ (IRO[43].base + ((storage_func_id) * IRO[43].m1) + \
	4275	+ ((bdq_id) * IRO[43].m2))
	4276	+#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[43].size)
4337	4277
4338	4278	/* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
4339		-#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
4340		- (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))
4341		-#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size)
	4279	+#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
	4280	+ (IRO[44].base + ((storage_func_id) * IRO[44].m1) + \
	4281	+ ((bdq_id) * IRO[44].m2))
	4282	+#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[44].size)
4342	4283
4343	4284	/* Tstorm iSCSI RX stats */
4344		-#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
4345		- (IRO[37].base + ((pf_id) * IRO[37].m1))
4346		-#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size)
	4285	+#define TSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
	4286	+ (IRO[45].base + ((storage_func_id) * IRO[45].m1))
	4287	+#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[45].size)
4347	4288
4348	4289	/* Mstorm iSCSI RX stats */
4349		-#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
4350		- (IRO[38].base + ((pf_id) * IRO[38].m1))
4351		-#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size)
	4290	+#define MSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
	4291	+ (IRO[46].base + ((storage_func_id) * IRO[46].m1))
	4292	+#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[46].size)
4352	4293
4353	4294	/* Ustorm iSCSI RX stats */
4354		-#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
4355		- (IRO[39].base + ((pf_id) * IRO[39].m1))
4356		-#define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size)
	4295	+#define USTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
	4296	+ (IRO[47].base + ((storage_func_id) * IRO[47].m1))
	4297	+#define USTORM_ISCSI_RX_STATS_SIZE (IRO[47].size)
4357	4298
4358	4299	/* Xstorm iSCSI TX stats */
4359		-#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
4360		- (IRO[40].base + ((pf_id) * IRO[40].m1))
4361		-#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size)
	4300	+#define XSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
	4301	+ (IRO[48].base + ((storage_func_id) * IRO[48].m1))
	4302	+#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[48].size)
4362	4303
4363	4304	/* Ystorm iSCSI TX stats */
4364		-#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
4365		- (IRO[41].base + ((pf_id) * IRO[41].m1))
4366		-#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size)
	4305	+#define YSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
	4306	+ (IRO[49].base + ((storage_func_id) * IRO[49].m1))
	4307	+#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[49].size)
4367	4308
4368	4309	/* Pstorm iSCSI TX stats */
4369		-#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
4370		- (IRO[42].base + ((pf_id) * IRO[42].m1))
4371		-#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size)
	4310	+#define PSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
	4311	+ (IRO[50].base + ((storage_func_id) * IRO[50].m1))
	4312	+#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[50].size)
4372	4313
4373	4314	/* Tstorm FCoE RX stats */
4374	4315	#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
4375		- (IRO[43].base + ((pf_id) * IRO[43].m1))
4376		-#define TSTORM_FCOE_RX_STATS_SIZE (IRO[43].size)
	4316	+ (IRO[51].base + ((pf_id) * IRO[51].m1))
	4317	+#define TSTORM_FCOE_RX_STATS_SIZE (IRO[51].size)
4377	4318
4378	4319	/* Pstorm FCoE TX stats */
4379	4320	#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
4380		- (IRO[44].base + ((pf_id) * IRO[44].m1))
4381		-#define PSTORM_FCOE_TX_STATS_SIZE (IRO[44].size)
	4321	+ (IRO[52].base + ((pf_id) * IRO[52].m1))
	4322	+#define PSTORM_FCOE_TX_STATS_SIZE (IRO[52].size)
4382	4323
4383	4324	/* Pstorm RDMA queue statistics */
4384	4325	#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4385		- (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1))
4386		-#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size)
	4326	+ (IRO[53].base + ((rdma_stat_counter_id) * IRO[53].m1))
	4327	+#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[53].size)
4387	4328
4388	4329	/* Tstorm RDMA queue statistics */
4389	4330	#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4390		- (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
4391		-#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size)
	4331	+ (IRO[54].base + ((rdma_stat_counter_id) * IRO[54].m1))
	4332	+#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[54].size)
4392	4333
4393	4334	/* Xstorm error level for assert */
4394	4335	#define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4395		- (IRO[47].base + ((pf_id) * IRO[47].m1))
4396		-#define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[47].size)
	4336	+ (IRO[55].base + ((pf_id) * IRO[55].m1))
	4337	+#define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[55].size)
4397	4338
4398	4339	/* Ystorm error level for assert */
4399	4340	#define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4400		- (IRO[48].base + ((pf_id) * IRO[48].m1))
4401		-#define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[48].size)
	4341	+ (IRO[56].base + ((pf_id) * IRO[56].m1))
	4342	+#define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[56].size)
4402	4343
4403	4344	/* Pstorm error level for assert */
4404	4345	#define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4405		- (IRO[49].base + ((pf_id) * IRO[49].m1))
4406		-#define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[49].size)
	4346	+ (IRO[57].base + ((pf_id) * IRO[57].m1))
	4347	+#define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[57].size)
4407	4348
4408	4349	/* Tstorm error level for assert */
4409	4350	#define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4410		- (IRO[50].base + ((pf_id) * IRO[50].m1))
4411		-#define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[50].size)
	4351	+ (IRO[58].base + ((pf_id) * IRO[58].m1))
	4352	+#define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[58].size)
4412	4353
4413	4354	/* Mstorm error level for assert */
4414	4355	#define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4415		- (IRO[51].base + ((pf_id) * IRO[51].m1))
4416		-#define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[51].size)
	4356	+ (IRO[59].base + ((pf_id) * IRO[59].m1))
	4357	+#define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[59].size)
4417	4358
4418	4359	/* Ustorm error level for assert */
4419	4360	#define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4420		- (IRO[52].base + ((pf_id) * IRO[52].m1))
4421		-#define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[52].size)
	4361	+ (IRO[60].base + ((pf_id) * IRO[60].m1))
	4362	+#define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[60].size)
4422	4363
4423	4364	/* Xstorm iWARP rxmit stats */
4424	4365	#define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) \
4425		- (IRO[53].base + ((pf_id) * IRO[53].m1))
4426		-#define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[53].size)
	4366	+ (IRO[61].base + ((pf_id) * IRO[61].m1))
	4367	+#define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[61].size)
4427	4368
4428	4369	/* Tstorm RoCE Event Statistics */
4429		-#define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) \
4430		- (IRO[54].base + ((roce_pf_id) * IRO[54].m1))
4431		-#define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[54].size)
	4370	+#define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) \
	4371	+ (IRO[62].base + ((roce_pf_id) * IRO[62].m1))
	4372	+#define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[62].size)
4432	4373
4433	4374	/* DCQCN Received Statistics */
4434		-#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) \
4435		- (IRO[55].base + ((roce_pf_id) * IRO[55].m1))
4436		-#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE (IRO[55].size)
	4375	+#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id)\
	4376	+ (IRO[63].base + ((roce_pf_id) * IRO[63].m1))
	4377	+#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE (IRO[63].size)
4437	4378
4438	4379	/* RoCE Error Statistics */
4439		-#define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) \
4440		- (IRO[56].base + ((roce_pf_id) * IRO[56].m1))
4441		-#define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[56].size)
	4380	+#define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) \
	4381	+ (IRO[64].base + ((roce_pf_id) * IRO[64].m1))
	4382	+#define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[64].size)
4442	4383
4443	4384	/* DCQCN Sent Statistics */
4444		-#define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) \
4445		- (IRO[57].base + ((roce_pf_id) * IRO[57].m1))
4446		-#define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE (IRO[57].size)
	4385	+#define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) \
	4386	+ (IRO[65].base + ((roce_pf_id) * IRO[65].m1))
	4387	+#define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE (IRO[65].size)
4447	4388
4448	4389	/* RoCE CQEs Statistics */
4449		-#define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) \
4450		- (IRO[58].base + ((roce_pf_id) * IRO[58].m1))
4451		-#define USTORM_ROCE_CQE_STATS_SIZE (IRO[58].size)
4452		-
4453		-static const struct iro iro_arr[59] = {
4454		- {0x0, 0x0, 0x0, 0x0, 0x8},
4455		- {0x4cb8, 0x88, 0x0, 0x0, 0x88},
4456		- {0x6530, 0x20, 0x0, 0x0, 0x20},
4457		- {0xb00, 0x8, 0x0, 0x0, 0x4},
4458		- {0xa80, 0x8, 0x0, 0x0, 0x4},
4459		- {0x0, 0x8, 0x0, 0x0, 0x2},
4460		- {0x80, 0x8, 0x0, 0x0, 0x4},
4461		- {0x84, 0x8, 0x0, 0x0, 0x2},
4462		- {0x4c48, 0x0, 0x0, 0x0, 0x78},
4463		- {0x3e38, 0x0, 0x0, 0x0, 0x78},
4464		- {0x2b78, 0x0, 0x0, 0x0, 0x78},
4465		- {0x4c40, 0x0, 0x0, 0x0, 0x78},
4466		- {0x4998, 0x0, 0x0, 0x0, 0x78},
4467		- {0x7f50, 0x0, 0x0, 0x0, 0x78},
4468		- {0xa28, 0x8, 0x0, 0x0, 0x8},
4469		- {0x6210, 0x10, 0x0, 0x0, 0x10},
4470		- {0xb820, 0x30, 0x0, 0x0, 0x30},
4471		- {0x96c0, 0x30, 0x0, 0x0, 0x30},
4472		- {0x4b68, 0x80, 0x0, 0x0, 0x40},
4473		- {0x1f8, 0x4, 0x0, 0x0, 0x4},
4474		- {0x53a8, 0x80, 0x4, 0x0, 0x4},
4475		- {0xc7d0, 0x0, 0x0, 0x0, 0x4},
4476		- {0x4ba8, 0x80, 0x0, 0x0, 0x20},
4477		- {0x8158, 0x40, 0x0, 0x0, 0x30},
4478		- {0xe770, 0x60, 0x0, 0x0, 0x60},
4479		- {0x2d10, 0x80, 0x0, 0x0, 0x38},
4480		- {0xf2b8, 0x78, 0x0, 0x0, 0x78},
4481		- {0x1f8, 0x4, 0x0, 0x0, 0x4},
4482		- {0xaf20, 0x0, 0x0, 0x0, 0xf0},
4483		- {0xb010, 0x8, 0x0, 0x0, 0x8},
4484		- {0x1f8, 0x8, 0x0, 0x0, 0x8},
4485		- {0xac0, 0x8, 0x0, 0x0, 0x8},
4486		- {0x2578, 0x8, 0x0, 0x0, 0x8},
4487		- {0x24f8, 0x8, 0x0, 0x0, 0x8},
4488		- {0x0, 0x8, 0x0, 0x0, 0x8},
4489		- {0x400, 0x18, 0x8, 0x0, 0x8},
4490		- {0xb78, 0x18, 0x8, 0x0, 0x2},
4491		- {0xd898, 0x50, 0x0, 0x0, 0x3c},
4492		- {0x12908, 0x18, 0x0, 0x0, 0x10},
4493		- {0x11aa8, 0x40, 0x0, 0x0, 0x18},
4494		- {0xa588, 0x50, 0x0, 0x0, 0x20},
4495		- {0x8700, 0x40, 0x0, 0x0, 0x28},
4496		- {0x10300, 0x18, 0x0, 0x0, 0x10},
4497		- {0xde48, 0x48, 0x0, 0x0, 0x38},
4498		- {0x10768, 0x20, 0x0, 0x0, 0x20},
4499		- {0x2d48, 0x80, 0x0, 0x0, 0x10},
4500		- {0x5048, 0x10, 0x0, 0x0, 0x10},
4501		- {0xc748, 0x8, 0x0, 0x0, 0x1},
4502		- {0xa128, 0x8, 0x0, 0x0, 0x1},
4503		- {0x10f00, 0x8, 0x0, 0x0, 0x1},
4504		- {0xf030, 0x8, 0x0, 0x0, 0x1},
4505		- {0x13028, 0x8, 0x0, 0x0, 0x1},
4506		- {0x12c58, 0x8, 0x0, 0x0, 0x1},
4507		- {0xc9b8, 0x30, 0x0, 0x0, 0x10},
4508		- {0xed90, 0x28, 0x0, 0x0, 0x28},
4509		- {0xa520, 0x18, 0x0, 0x0, 0x18},
4510		- {0xa6a0, 0x8, 0x0, 0x0, 0x8},
4511		- {0x13108, 0x8, 0x0, 0x0, 0x8},
4512		- {0x13c50, 0x18, 0x0, 0x0, 0x18},
4513		-};
	4390	+#define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) \
	4391	+ (IRO[66].base + ((roce_pf_id) * IRO[66].m1))
	4392	+#define USTORM_ROCE_CQE_STATS_SIZE (IRO[66].size)
4514	4393
4515	4394	/* Runtime array offsets */
4516		-#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
4517		-#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
4518		-#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
4519		-#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
4520		-#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
4521		-#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
4522		-#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
4523		-#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
4524		-#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
4525		-#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
4526		-#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
4527		-#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
4528		-#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
4529		-#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
4530		-#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
4531		-#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
4532		-#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
4533		-#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
4534		-#define DORQ_REG_GLB_MAX_ICID_0_RT_OFFSET 18
4535		-#define DORQ_REG_GLB_MAX_ICID_1_RT_OFFSET 19
4536		-#define DORQ_REG_GLB_RANGE2CONN_TYPE_0_RT_OFFSET 20
4537		-#define DORQ_REG_GLB_RANGE2CONN_TYPE_1_RT_OFFSET 21
4538		-#define DORQ_REG_PRV_PF_MAX_ICID_2_RT_OFFSET 22
4539		-#define DORQ_REG_PRV_PF_MAX_ICID_3_RT_OFFSET 23
4540		-#define DORQ_REG_PRV_PF_MAX_ICID_4_RT_OFFSET 24
4541		-#define DORQ_REG_PRV_PF_MAX_ICID_5_RT_OFFSET 25
4542		-#define DORQ_REG_PRV_VF_MAX_ICID_2_RT_OFFSET 26
4543		-#define DORQ_REG_PRV_VF_MAX_ICID_3_RT_OFFSET 27
4544		-#define DORQ_REG_PRV_VF_MAX_ICID_4_RT_OFFSET 28
4545		-#define DORQ_REG_PRV_VF_MAX_ICID_5_RT_OFFSET 29
4546		-#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_2_RT_OFFSET 30
4547		-#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_3_RT_OFFSET 31
4548		-#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_4_RT_OFFSET 32
4549		-#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_5_RT_OFFSET 33
4550		-#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_2_RT_OFFSET 34
4551		-#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_3_RT_OFFSET 35
4552		-#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_4_RT_OFFSET 36
4553		-#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_5_RT_OFFSET 37
4554		-#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 38
4555		-#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 39
4556		-#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 40
4557		-#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 41
4558		-#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 42
4559		-#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 43
4560		-#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 44
4561		-#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 45
4562		-#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 1024
4563		-#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1069
4564		-#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 1024
4565		-#define CAU_REG_PI_MEMORY_RT_OFFSET 2093
4566		-#define CAU_REG_PI_MEMORY_RT_SIZE 4416
4567		-#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6509
4568		-#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6510
4569		-#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6511
4570		-#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6512
4571		-#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6513
4572		-#define PRS_REG_SEARCH_TCP_RT_OFFSET 6514
4573		-#define PRS_REG_SEARCH_FCOE_RT_OFFSET 6515
4574		-#define PRS_REG_SEARCH_ROCE_RT_OFFSET 6516
4575		-#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6517
4576		-#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6518
4577		-#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6519
4578		-#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6520
4579		-#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6521
4580		-#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6522
4581		-#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6523
4582		-#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6524
4583		-#define SRC_REG_FIRSTFREE_RT_OFFSET 6525
4584		-#define SRC_REG_FIRSTFREE_RT_SIZE 2
4585		-#define SRC_REG_LASTFREE_RT_OFFSET 6527
4586		-#define SRC_REG_LASTFREE_RT_SIZE 2
4587		-#define SRC_REG_COUNTFREE_RT_OFFSET 6529
4588		-#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6530
4589		-#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6531
4590		-#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6532
4591		-#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6533
4592		-#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6534
4593		-#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6535
4594		-#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6536
4595		-#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6537
4596		-#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6538
4597		-#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6539
4598		-#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6540
4599		-#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6541
4600		-#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6542
4601		-#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6543
4602		-#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6544
4603		-#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6545
4604		-#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6546
4605		-#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6547
4606		-#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6548
4607		-#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6549
4608		-#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6550
4609		-#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6551
4610		-#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6552
4611		-#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6553
4612		-#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6554
4613		-#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6555
4614		-#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6556
4615		-#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6557
4616		-#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6558
4617		-#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6559
4618		-#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6560
4619		-#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6561
4620		-#define PSWRQ2_REG_TGSRC_FIRST_ILT_RT_OFFSET 6562
4621		-#define PSWRQ2_REG_RGSRC_FIRST_ILT_RT_OFFSET 6563
4622		-#define PSWRQ2_REG_TGSRC_LAST_ILT_RT_OFFSET 6564
4623		-#define PSWRQ2_REG_RGSRC_LAST_ILT_RT_OFFSET 6565
4624		-#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6566
4625		-#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 26414
4626		-#define PGLUE_REG_B_VF_BASE_RT_OFFSET 32980
4627		-#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 32981
4628		-#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 32982
4629		-#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 32983
4630		-#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 32984
4631		-#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 32985
4632		-#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 32986
4633		-#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 32987
4634		-#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 32988
4635		-#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 32989
4636		-#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 32990
4637		-#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 32991
4638		-#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 32992
4639		-#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
4640		-#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 33408
4641		-#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 608
4642		-#define QM_REG_MAXPQSIZE_0_RT_OFFSET 34016
4643		-#define QM_REG_MAXPQSIZE_1_RT_OFFSET 34017
4644		-#define QM_REG_MAXPQSIZE_2_RT_OFFSET 34018
4645		-#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 34019
4646		-#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 34020
4647		-#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 34021
4648		-#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 34022
4649		-#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 34023
4650		-#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 34024
4651		-#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 34025
4652		-#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 34026
4653		-#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 34027
4654		-#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 34028
4655		-#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 34029
4656		-#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 34030
4657		-#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 34031
4658		-#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 34032
4659		-#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 34033
4660		-#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 34034
4661		-#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 34035
4662		-#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 34036
4663		-#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 34037
4664		-#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 34038
4665		-#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 34039
4666		-#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 34040
4667		-#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 34041
4668		-#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 34042
4669		-#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 34043
4670		-#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 34044
4671		-#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 34045
4672		-#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 34046
4673		-#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 34047
4674		-#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 34048
4675		-#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 34049
4676		-#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 34050
4677		-#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 34051
4678		-#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 34052
4679		-#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 34053
4680		-#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 34054
4681		-#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 34055
4682		-#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 34056
4683		-#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 34057
4684		-#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 34058
4685		-#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 34059
4686		-#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 34060
4687		-#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 34061
4688		-#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 34062
4689		-#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 34063
4690		-#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 34064
4691		-#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 34065
4692		-#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 34066
4693		-#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 34067
4694		-#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 34068
4695		-#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 34069
4696		-#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 34070
4697		-#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 34071
4698		-#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 34072
4699		-#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 34073
4700		-#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 34074
4701		-#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 34075
4702		-#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 34076
4703		-#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 34077
4704		-#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 34078
4705		-#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 34079
4706		-#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 34080
4707		-#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 34081
4708		-#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 34082
4709		-#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 34083
4710		-#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
4711		-#define QM_REG_PTRTBLOTHER_RT_OFFSET 34211
4712		-#define QM_REG_PTRTBLOTHER_RT_SIZE 256
4713		-#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 34467
4714		-#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 34468
4715		-#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 34469
4716		-#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 34470
4717		-#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 34471
4718		-#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 34472
4719		-#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 34473
4720		-#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 34474
4721		-#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 34475
4722		-#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 34476
4723		-#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 34477
4724		-#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 34478
4725		-#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 34479
4726		-#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 34480
4727		-#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 34481
4728		-#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 34482
4729		-#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 34483
4730		-#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 34484
4731		-#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 34485
4732		-#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 34486
4733		-#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 34487
4734		-#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 34488
4735		-#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 34489
4736		-#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 34490
4737		-#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 34491
4738		-#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 34492
4739		-#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 34493
4740		-#define QM_REG_PQTX2PF_0_RT_OFFSET 34494
4741		-#define QM_REG_PQTX2PF_1_RT_OFFSET 34495
4742		-#define QM_REG_PQTX2PF_2_RT_OFFSET 34496
4743		-#define QM_REG_PQTX2PF_3_RT_OFFSET 34497
4744		-#define QM_REG_PQTX2PF_4_RT_OFFSET 34498
4745		-#define QM_REG_PQTX2PF_5_RT_OFFSET 34499
4746		-#define QM_REG_PQTX2PF_6_RT_OFFSET 34500
4747		-#define QM_REG_PQTX2PF_7_RT_OFFSET 34501
4748		-#define QM_REG_PQTX2PF_8_RT_OFFSET 34502
4749		-#define QM_REG_PQTX2PF_9_RT_OFFSET 34503
4750		-#define QM_REG_PQTX2PF_10_RT_OFFSET 34504
4751		-#define QM_REG_PQTX2PF_11_RT_OFFSET 34505
4752		-#define QM_REG_PQTX2PF_12_RT_OFFSET 34506
4753		-#define QM_REG_PQTX2PF_13_RT_OFFSET 34507
4754		-#define QM_REG_PQTX2PF_14_RT_OFFSET 34508
4755		-#define QM_REG_PQTX2PF_15_RT_OFFSET 34509
4756		-#define QM_REG_PQTX2PF_16_RT_OFFSET 34510
4757		-#define QM_REG_PQTX2PF_17_RT_OFFSET 34511
4758		-#define QM_REG_PQTX2PF_18_RT_OFFSET 34512
4759		-#define QM_REG_PQTX2PF_19_RT_OFFSET 34513
4760		-#define QM_REG_PQTX2PF_20_RT_OFFSET 34514
4761		-#define QM_REG_PQTX2PF_21_RT_OFFSET 34515
4762		-#define QM_REG_PQTX2PF_22_RT_OFFSET 34516
4763		-#define QM_REG_PQTX2PF_23_RT_OFFSET 34517
4764		-#define QM_REG_PQTX2PF_24_RT_OFFSET 34518
4765		-#define QM_REG_PQTX2PF_25_RT_OFFSET 34519
4766		-#define QM_REG_PQTX2PF_26_RT_OFFSET 34520
4767		-#define QM_REG_PQTX2PF_27_RT_OFFSET 34521
4768		-#define QM_REG_PQTX2PF_28_RT_OFFSET 34522
4769		-#define QM_REG_PQTX2PF_29_RT_OFFSET 34523
4770		-#define QM_REG_PQTX2PF_30_RT_OFFSET 34524
4771		-#define QM_REG_PQTX2PF_31_RT_OFFSET 34525
4772		-#define QM_REG_PQTX2PF_32_RT_OFFSET 34526
4773		-#define QM_REG_PQTX2PF_33_RT_OFFSET 34527
4774		-#define QM_REG_PQTX2PF_34_RT_OFFSET 34528
4775		-#define QM_REG_PQTX2PF_35_RT_OFFSET 34529
4776		-#define QM_REG_PQTX2PF_36_RT_OFFSET 34530
4777		-#define QM_REG_PQTX2PF_37_RT_OFFSET 34531
4778		-#define QM_REG_PQTX2PF_38_RT_OFFSET 34532
4779		-#define QM_REG_PQTX2PF_39_RT_OFFSET 34533
4780		-#define QM_REG_PQTX2PF_40_RT_OFFSET 34534
4781		-#define QM_REG_PQTX2PF_41_RT_OFFSET 34535
4782		-#define QM_REG_PQTX2PF_42_RT_OFFSET 34536
4783		-#define QM_REG_PQTX2PF_43_RT_OFFSET 34537
4784		-#define QM_REG_PQTX2PF_44_RT_OFFSET 34538
4785		-#define QM_REG_PQTX2PF_45_RT_OFFSET 34539
4786		-#define QM_REG_PQTX2PF_46_RT_OFFSET 34540
4787		-#define QM_REG_PQTX2PF_47_RT_OFFSET 34541
4788		-#define QM_REG_PQTX2PF_48_RT_OFFSET 34542
4789		-#define QM_REG_PQTX2PF_49_RT_OFFSET 34543
4790		-#define QM_REG_PQTX2PF_50_RT_OFFSET 34544
4791		-#define QM_REG_PQTX2PF_51_RT_OFFSET 34545
4792		-#define QM_REG_PQTX2PF_52_RT_OFFSET 34546
4793		-#define QM_REG_PQTX2PF_53_RT_OFFSET 34547
4794		-#define QM_REG_PQTX2PF_54_RT_OFFSET 34548
4795		-#define QM_REG_PQTX2PF_55_RT_OFFSET 34549
4796		-#define QM_REG_PQTX2PF_56_RT_OFFSET 34550
4797		-#define QM_REG_PQTX2PF_57_RT_OFFSET 34551
4798		-#define QM_REG_PQTX2PF_58_RT_OFFSET 34552
4799		-#define QM_REG_PQTX2PF_59_RT_OFFSET 34553
4800		-#define QM_REG_PQTX2PF_60_RT_OFFSET 34554
4801		-#define QM_REG_PQTX2PF_61_RT_OFFSET 34555
4802		-#define QM_REG_PQTX2PF_62_RT_OFFSET 34556
4803		-#define QM_REG_PQTX2PF_63_RT_OFFSET 34557
4804		-#define QM_REG_PQOTHER2PF_0_RT_OFFSET 34558
4805		-#define QM_REG_PQOTHER2PF_1_RT_OFFSET 34559
4806		-#define QM_REG_PQOTHER2PF_2_RT_OFFSET 34560
4807		-#define QM_REG_PQOTHER2PF_3_RT_OFFSET 34561
4808		-#define QM_REG_PQOTHER2PF_4_RT_OFFSET 34562
4809		-#define QM_REG_PQOTHER2PF_5_RT_OFFSET 34563
4810		-#define QM_REG_PQOTHER2PF_6_RT_OFFSET 34564
4811		-#define QM_REG_PQOTHER2PF_7_RT_OFFSET 34565
4812		-#define QM_REG_PQOTHER2PF_8_RT_OFFSET 34566
4813		-#define QM_REG_PQOTHER2PF_9_RT_OFFSET 34567
4814		-#define QM_REG_PQOTHER2PF_10_RT_OFFSET 34568
4815		-#define QM_REG_PQOTHER2PF_11_RT_OFFSET 34569
4816		-#define QM_REG_PQOTHER2PF_12_RT_OFFSET 34570
4817		-#define QM_REG_PQOTHER2PF_13_RT_OFFSET 34571
4818		-#define QM_REG_PQOTHER2PF_14_RT_OFFSET 34572
4819		-#define QM_REG_PQOTHER2PF_15_RT_OFFSET 34573
4820		-#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 34574
4821		-#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 34575
4822		-#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 34576
4823		-#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 34577
4824		-#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 34578
4825		-#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 34579
4826		-#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 34580
4827		-#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 34581
4828		-#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 34582
4829		-#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 34583
4830		-#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 34584
4831		-#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 34585
4832		-#define QM_REG_RLGLBLINCVAL_RT_OFFSET 34586
4833		-#define QM_REG_RLGLBLINCVAL_RT_SIZE 256
4834		-#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 34842
4835		-#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
4836		-#define QM_REG_RLGLBLCRD_RT_OFFSET 35098
4837		-#define QM_REG_RLGLBLCRD_RT_SIZE 256
4838		-#define QM_REG_RLGLBLENABLE_RT_OFFSET 35354
4839		-#define QM_REG_RLPFPERIOD_RT_OFFSET 35355
4840		-#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 35356
4841		-#define QM_REG_RLPFINCVAL_RT_OFFSET 35357
4842		-#define QM_REG_RLPFINCVAL_RT_SIZE 16
4843		-#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 35373
4844		-#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
4845		-#define QM_REG_RLPFCRD_RT_OFFSET 35389
4846		-#define QM_REG_RLPFCRD_RT_SIZE 16
4847		-#define QM_REG_RLPFENABLE_RT_OFFSET 35405
4848		-#define QM_REG_RLPFVOQENABLE_RT_OFFSET 35406
4849		-#define QM_REG_WFQPFWEIGHT_RT_OFFSET 35407
4850		-#define QM_REG_WFQPFWEIGHT_RT_SIZE 16
4851		-#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 35423
4852		-#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
4853		-#define QM_REG_WFQPFCRD_RT_OFFSET 35439
4854		-#define QM_REG_WFQPFCRD_RT_SIZE 256
4855		-#define QM_REG_WFQPFENABLE_RT_OFFSET 35695
4856		-#define QM_REG_WFQVPENABLE_RT_OFFSET 35696
4857		-#define QM_REG_BASEADDRTXPQ_RT_OFFSET 35697
4858		-#define QM_REG_BASEADDRTXPQ_RT_SIZE 512
4859		-#define QM_REG_TXPQMAP_RT_OFFSET 36209
4860		-#define QM_REG_TXPQMAP_RT_SIZE 512
4861		-#define QM_REG_WFQVPWEIGHT_RT_OFFSET 36721
4862		-#define QM_REG_WFQVPWEIGHT_RT_SIZE 512
4863		-#define QM_REG_WFQVPCRD_RT_OFFSET 37233
4864		-#define QM_REG_WFQVPCRD_RT_SIZE 512
4865		-#define QM_REG_WFQVPMAP_RT_OFFSET 37745
4866		-#define QM_REG_WFQVPMAP_RT_SIZE 512
4867		-#define QM_REG_PTRTBLTX_RT_OFFSET 38257
4868		-#define QM_REG_PTRTBLTX_RT_SIZE 1024
4869		-#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 39281
4870		-#define QM_REG_WFQPFCRD_MSB_RT_SIZE 320
4871		-#define QM_REG_VOQCRDLINE_RT_OFFSET 39601
4872		-#define QM_REG_VOQCRDLINE_RT_SIZE 36
4873		-#define QM_REG_VOQINITCRDLINE_RT_OFFSET 39637
4874		-#define QM_REG_VOQINITCRDLINE_RT_SIZE 36
4875		-#define QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET 39673
4876		-#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 39674
4877		-#define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 39675
4878		-#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 39676
4879		-#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 39677
4880		-#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 39678
4881		-#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 39679
4882		-#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 39680
4883		-#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 39681
4884		-#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
4885		-#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 39685
4886		-#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
4887		-#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 39689
4888		-#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
4889		-#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 39721
4890		-#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
4891		-#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 39737
4892		-#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
4893		-#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 39753
4894		-#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
4895		-#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 39769
4896		-#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
4897		-#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 39785
4898		-#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 39786
4899		-#define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8
4900		-#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 39794
4901		-#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_SIZE 1024
4902		-#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 40818
4903		-#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_SIZE 512
4904		-#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 41330
4905		-#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_SIZE 512
4906		-#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 41842
4907		-#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 512
4908		-#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 42354
4909		-#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_SIZE 512
4910		-#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 42866
4911		-#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_SIZE 32
4912		-#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 42898
4913		-#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 42899
4914		-#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 42900
4915		-#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 42901
4916		-#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 42902
4917		-#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 42903
4918		-#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 42904
4919		-#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 42905
4920		-#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 42906
4921		-#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 42907
4922		-#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 42908
4923		-#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 42909
4924		-#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 42910
4925		-#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 42911
4926		-#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 42912
4927		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 42913
4928		-#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 42914
4929		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 42915
4930		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 42916
4931		-#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 42917
4932		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 42918
4933		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 42919
4934		-#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 42920
4935		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 42921
4936		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 42922
4937		-#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 42923
4938		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 42924
4939		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 42925
4940		-#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 42926
4941		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 42927
4942		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 42928
4943		-#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 42929
4944		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 42930
4945		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 42931
4946		-#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 42932
4947		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 42933
4948		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 42934
4949		-#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 42935
4950		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 42936
4951		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 42937
4952		-#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 42938
4953		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 42939
4954		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 42940
4955		-#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 42941
4956		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 42942
4957		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 42943
4958		-#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 42944
4959		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 42945
4960		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 42946
4961		-#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 42947
4962		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 42948
4963		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 42949
4964		-#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 42950
4965		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 42951
4966		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 42952
4967		-#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 42953
4968		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 42954
4969		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 42955
4970		-#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 42956
4971		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 42957
4972		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 42958
4973		-#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 42959
4974		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 42960
4975		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 42961
4976		-#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 42962
4977		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 42963
4978		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 42964
4979		-#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 42965
4980		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 42966
4981		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 42967
4982		-#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 42968
4983		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 42969
4984		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 42970
4985		-#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 42971
4986		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 42972
4987		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 42973
4988		-#define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 42974
4989		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 42975
4990		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 42976
4991		-#define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 42977
4992		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 42978
4993		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 42979
4994		-#define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 42980
4995		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 42981
4996		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 42982
4997		-#define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 42983
4998		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 42984
4999		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 42985
5000		-#define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 42986
5001		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 42987
5002		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 42988
5003		-#define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 42989
5004		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 42990
5005		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 42991
5006		-#define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 42992
5007		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 42993
5008		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 42994
5009		-#define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 42995
5010		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 42996
5011		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 42997
5012		-#define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 42998
5013		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 42999
5014		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 43000
5015		-#define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 43001
5016		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 43002
5017		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 43003
5018		-#define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 43004
5019		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 43005
5020		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 43006
5021		-#define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 43007
5022		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 43008
5023		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 43009
5024		-#define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 43010
5025		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 43011
5026		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 43012
5027		-#define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 43013
5028		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 43014
5029		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 43015
5030		-#define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 43016
5031		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 43017
5032		-#define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 43018
5033		-#define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 43019
5034		-#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 43020
5035		-#define XCM_REG_CON_PHY_Q3_RT_OFFSET 43021
	4395	+#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
	4396	+#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
	4397	+#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
	4398	+#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
	4399	+#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
	4400	+#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
	4401	+#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
	4402	+#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
	4403	+#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
	4404	+#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
	4405	+#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
	4406	+#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
	4407	+#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
	4408	+#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
	4409	+#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
	4410	+#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
	4411	+#define DORQ_REG_VF_ICID_BIT_SHIFT_NORM_RT_OFFSET 16
	4412	+#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 17
	4413	+#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 18
	4414	+#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 19
	4415	+#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 20
	4416	+#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 21
	4417	+#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 22
	4418	+#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 23
	4419	+#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 24
	4420	+#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 25
	4421	+#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 26
	4422	+#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
	4423	+#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 762
	4424	+#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
	4425	+#define CAU_REG_PI_MEMORY_RT_OFFSET 1498
	4426	+#define CAU_REG_PI_MEMORY_RT_SIZE 4416
	4427	+#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 5914
	4428	+#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 5915
	4429	+#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 5916
	4430	+#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 5917
	4431	+#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 5918
	4432	+#define PRS_REG_SEARCH_TCP_RT_OFFSET 5919
	4433	+#define PRS_REG_SEARCH_FCOE_RT_OFFSET 5920
	4434	+#define PRS_REG_SEARCH_ROCE_RT_OFFSET 5921
	4435	+#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 5922
	4436	+#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 5923
	4437	+#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 5924
	4438	+#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 5925
	4439	+#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 5926
	4440	+#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 5927
	4441	+#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 5928
	4442	+#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 5929
	4443	+#define SRC_REG_FIRSTFREE_RT_OFFSET 5930
	4444	+#define SRC_REG_FIRSTFREE_RT_SIZE 2
	4445	+#define SRC_REG_LASTFREE_RT_OFFSET 5932
	4446	+#define SRC_REG_LASTFREE_RT_SIZE 2
	4447	+#define SRC_REG_COUNTFREE_RT_OFFSET 5934
	4448	+#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 5935
	4449	+#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 5936
	4450	+#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 5937
	4451	+#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 5938
	4452	+#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 5939
	4453	+#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 5940
	4454	+#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 5941
	4455	+#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 5942
	4456	+#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 5943
	4457	+#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 5944
	4458	+#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 5945
	4459	+#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 5946
	4460	+#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 5947
	4461	+#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 5948
	4462	+#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 5949
	4463	+#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 5950
	4464	+#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 5951
	4465	+#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 5952
	4466	+#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 5953
	4467	+#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5954
	4468	+#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5955
	4469	+#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5956
	4470	+#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 5957
	4471	+#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 5958
	4472	+#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 5959
	4473	+#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 5960
	4474	+#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 5961
	4475	+#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 5962
	4476	+#define PSWRQ2_REG_VF_BASE_RT_OFFSET 5963
	4477	+#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 5964
	4478	+#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 5965
	4479	+#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 5966
	4480	+#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 5967
	4481	+#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
	4482	+#define PGLUE_REG_B_VF_BASE_RT_OFFSET 27967
	4483	+#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 27968
	4484	+#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 27969
	4485	+#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 27970
	4486	+#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 27971
	4487	+#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 27972
	4488	+#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 27973
	4489	+#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 27974
	4490	+#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 27975
	4491	+#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 27976
	4492	+#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 27977
	4493	+#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 27978
	4494	+#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 27979
	4495	+#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
	4496	+#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 28395
	4497	+#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
	4498	+#define QM_REG_MAXPQSIZE_0_RT_OFFSET 28907
	4499	+#define QM_REG_MAXPQSIZE_1_RT_OFFSET 28908
	4500	+#define QM_REG_MAXPQSIZE_2_RT_OFFSET 28909
	4501	+#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 28910
	4502	+#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 28911
	4503	+#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 28912
	4504	+#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 28913
	4505	+#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 28914
	4506	+#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 28915
	4507	+#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 28916
	4508	+#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 28917
	4509	+#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 28918
	4510	+#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 28919
	4511	+#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 28920
	4512	+#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 28921
	4513	+#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 28922
	4514	+#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 28923
	4515	+#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 28924
	4516	+#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 28925
	4517	+#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 28926
	4518	+#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 28927
	4519	+#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 28928
	4520	+#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 28929
	4521	+#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 28930
	4522	+#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 28931
	4523	+#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 28932
	4524	+#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 28933
	4525	+#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 28934
	4526	+#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 28935
	4527	+#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 28936
	4528	+#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 28937
	4529	+#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 28938
	4530	+#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 28939
	4531	+#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 28940
	4532	+#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 28941
	4533	+#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 28942
	4534	+#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 28943
	4535	+#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 28944
	4536	+#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 28945
	4537	+#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 28946
	4538	+#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 28947
	4539	+#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 28948
	4540	+#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 28949
	4541	+#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 28950
	4542	+#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 28951
	4543	+#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 28952
	4544	+#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 28953
	4545	+#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 28954
	4546	+#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 28955
	4547	+#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 28956
	4548	+#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 28957
	4549	+#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 28958
	4550	+#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 28959
	4551	+#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 28960
	4552	+#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 28961
	4553	+#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 28962
	4554	+#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 28963
	4555	+#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 28964
	4556	+#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 28965
	4557	+#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 28966
	4558	+#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 28967
	4559	+#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 28968
	4560	+#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 28969
	4561	+#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 28970
	4562	+#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 28971
	4563	+#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 28972
	4564	+#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 28973
	4565	+#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 28974
	4566	+#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
	4567	+#define QM_REG_PTRTBLOTHER_RT_OFFSET 29102
	4568	+#define QM_REG_PTRTBLOTHER_RT_SIZE 256
	4569	+#define QM_REG_VOQCRDLINE_RT_OFFSET 29358
	4570	+#define QM_REG_VOQCRDLINE_RT_SIZE 20
	4571	+#define QM_REG_VOQINITCRDLINE_RT_OFFSET 29378
	4572	+#define QM_REG_VOQINITCRDLINE_RT_SIZE 20
	4573	+#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29398
	4574	+#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29399
	4575	+#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29400
	4576	+#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29401
	4577	+#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29402
	4578	+#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29403
	4579	+#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29404
	4580	+#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29405
	4581	+#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29406
	4582	+#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29407
	4583	+#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29408
	4584	+#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29409
	4585	+#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29410
	4586	+#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29411
	4587	+#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29412
	4588	+#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29413
	4589	+#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29414
	4590	+#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29415
	4591	+#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29416
	4592	+#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29417
	4593	+#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29418
	4594	+#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29419
	4595	+#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29420
	4596	+#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29421
	4597	+#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29422
	4598	+#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29423
	4599	+#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29424
	4600	+#define QM_REG_PQTX2PF_0_RT_OFFSET 29425
	4601	+#define QM_REG_PQTX2PF_1_RT_OFFSET 29426
	4602	+#define QM_REG_PQTX2PF_2_RT_OFFSET 29427
	4603	+#define QM_REG_PQTX2PF_3_RT_OFFSET 29428
	4604	+#define QM_REG_PQTX2PF_4_RT_OFFSET 29429
	4605	+#define QM_REG_PQTX2PF_5_RT_OFFSET 29430
	4606	+#define QM_REG_PQTX2PF_6_RT_OFFSET 29431
	4607	+#define QM_REG_PQTX2PF_7_RT_OFFSET 29432
	4608	+#define QM_REG_PQTX2PF_8_RT_OFFSET 29433
	4609	+#define QM_REG_PQTX2PF_9_RT_OFFSET 29434
	4610	+#define QM_REG_PQTX2PF_10_RT_OFFSET 29435
	4611	+#define QM_REG_PQTX2PF_11_RT_OFFSET 29436
	4612	+#define QM_REG_PQTX2PF_12_RT_OFFSET 29437
	4613	+#define QM_REG_PQTX2PF_13_RT_OFFSET 29438
	4614	+#define QM_REG_PQTX2PF_14_RT_OFFSET 29439
	4615	+#define QM_REG_PQTX2PF_15_RT_OFFSET 29440
	4616	+#define QM_REG_PQTX2PF_16_RT_OFFSET 29441
	4617	+#define QM_REG_PQTX2PF_17_RT_OFFSET 29442
	4618	+#define QM_REG_PQTX2PF_18_RT_OFFSET 29443
	4619	+#define QM_REG_PQTX2PF_19_RT_OFFSET 29444
	4620	+#define QM_REG_PQTX2PF_20_RT_OFFSET 29445
	4621	+#define QM_REG_PQTX2PF_21_RT_OFFSET 29446
	4622	+#define QM_REG_PQTX2PF_22_RT_OFFSET 29447
	4623	+#define QM_REG_PQTX2PF_23_RT_OFFSET 29448
	4624	+#define QM_REG_PQTX2PF_24_RT_OFFSET 29449
	4625	+#define QM_REG_PQTX2PF_25_RT_OFFSET 29450
	4626	+#define QM_REG_PQTX2PF_26_RT_OFFSET 29451
	4627	+#define QM_REG_PQTX2PF_27_RT_OFFSET 29452
	4628	+#define QM_REG_PQTX2PF_28_RT_OFFSET 29453
	4629	+#define QM_REG_PQTX2PF_29_RT_OFFSET 29454
	4630	+#define QM_REG_PQTX2PF_30_RT_OFFSET 29455
	4631	+#define QM_REG_PQTX2PF_31_RT_OFFSET 29456
	4632	+#define QM_REG_PQTX2PF_32_RT_OFFSET 29457
	4633	+#define QM_REG_PQTX2PF_33_RT_OFFSET 29458
	4634	+#define QM_REG_PQTX2PF_34_RT_OFFSET 29459
	4635	+#define QM_REG_PQTX2PF_35_RT_OFFSET 29460
	4636	+#define QM_REG_PQTX2PF_36_RT_OFFSET 29461
	4637	+#define QM_REG_PQTX2PF_37_RT_OFFSET 29462
	4638	+#define QM_REG_PQTX2PF_38_RT_OFFSET 29463
	4639	+#define QM_REG_PQTX2PF_39_RT_OFFSET 29464
	4640	+#define QM_REG_PQTX2PF_40_RT_OFFSET 29465
	4641	+#define QM_REG_PQTX2PF_41_RT_OFFSET 29466
	4642	+#define QM_REG_PQTX2PF_42_RT_OFFSET 29467
	4643	+#define QM_REG_PQTX2PF_43_RT_OFFSET 29468
	4644	+#define QM_REG_PQTX2PF_44_RT_OFFSET 29469
	4645	+#define QM_REG_PQTX2PF_45_RT_OFFSET 29470
	4646	+#define QM_REG_PQTX2PF_46_RT_OFFSET 29471
	4647	+#define QM_REG_PQTX2PF_47_RT_OFFSET 29472
	4648	+#define QM_REG_PQTX2PF_48_RT_OFFSET 29473
	4649	+#define QM_REG_PQTX2PF_49_RT_OFFSET 29474
	4650	+#define QM_REG_PQTX2PF_50_RT_OFFSET 29475
	4651	+#define QM_REG_PQTX2PF_51_RT_OFFSET 29476
	4652	+#define QM_REG_PQTX2PF_52_RT_OFFSET 29477
	4653	+#define QM_REG_PQTX2PF_53_RT_OFFSET 29478
	4654	+#define QM_REG_PQTX2PF_54_RT_OFFSET 29479
	4655	+#define QM_REG_PQTX2PF_55_RT_OFFSET 29480
	4656	+#define QM_REG_PQTX2PF_56_RT_OFFSET 29481
	4657	+#define QM_REG_PQTX2PF_57_RT_OFFSET 29482
	4658	+#define QM_REG_PQTX2PF_58_RT_OFFSET 29483
	4659	+#define QM_REG_PQTX2PF_59_RT_OFFSET 29484
	4660	+#define QM_REG_PQTX2PF_60_RT_OFFSET 29485
	4661	+#define QM_REG_PQTX2PF_61_RT_OFFSET 29486
	4662	+#define QM_REG_PQTX2PF_62_RT_OFFSET 29487
	4663	+#define QM_REG_PQTX2PF_63_RT_OFFSET 29488
	4664	+#define QM_REG_PQOTHER2PF_0_RT_OFFSET 29489
	4665	+#define QM_REG_PQOTHER2PF_1_RT_OFFSET 29490
	4666	+#define QM_REG_PQOTHER2PF_2_RT_OFFSET 29491
	4667	+#define QM_REG_PQOTHER2PF_3_RT_OFFSET 29492
	4668	+#define QM_REG_PQOTHER2PF_4_RT_OFFSET 29493
	4669	+#define QM_REG_PQOTHER2PF_5_RT_OFFSET 29494
	4670	+#define QM_REG_PQOTHER2PF_6_RT_OFFSET 29495
	4671	+#define QM_REG_PQOTHER2PF_7_RT_OFFSET 29496
	4672	+#define QM_REG_PQOTHER2PF_8_RT_OFFSET 29497
	4673	+#define QM_REG_PQOTHER2PF_9_RT_OFFSET 29498
	4674	+#define QM_REG_PQOTHER2PF_10_RT_OFFSET 29499
	4675	+#define QM_REG_PQOTHER2PF_11_RT_OFFSET 29500
	4676	+#define QM_REG_PQOTHER2PF_12_RT_OFFSET 29501
	4677	+#define QM_REG_PQOTHER2PF_13_RT_OFFSET 29502
	4678	+#define QM_REG_PQOTHER2PF_14_RT_OFFSET 29503
	4679	+#define QM_REG_PQOTHER2PF_15_RT_OFFSET 29504
	4680	+#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29505
	4681	+#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29506
	4682	+#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29507
	4683	+#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29508
	4684	+#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29509
	4685	+#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29510
	4686	+#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29511
	4687	+#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29512
	4688	+#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29513
	4689	+#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29514
	4690	+#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29515
	4691	+#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29516
	4692	+#define QM_REG_RLGLBLINCVAL_RT_OFFSET 29517
	4693	+#define QM_REG_RLGLBLINCVAL_RT_SIZE 256
	4694	+#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 29773
	4695	+#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
	4696	+#define QM_REG_RLGLBLCRD_RT_OFFSET 30029
	4697	+#define QM_REG_RLGLBLCRD_RT_SIZE 256
	4698	+#define QM_REG_RLGLBLENABLE_RT_OFFSET 30285
	4699	+#define QM_REG_RLPFPERIOD_RT_OFFSET 30286
	4700	+#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30287
	4701	+#define QM_REG_RLPFINCVAL_RT_OFFSET 30288
	4702	+#define QM_REG_RLPFINCVAL_RT_SIZE 16
	4703	+#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30304
	4704	+#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
	4705	+#define QM_REG_RLPFCRD_RT_OFFSET 30320
	4706	+#define QM_REG_RLPFCRD_RT_SIZE 16
	4707	+#define QM_REG_RLPFENABLE_RT_OFFSET 30336
	4708	+#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30337
	4709	+#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30338
	4710	+#define QM_REG_WFQPFWEIGHT_RT_SIZE 16
	4711	+#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30354
	4712	+#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
	4713	+#define QM_REG_WFQPFCRD_RT_OFFSET 30370
	4714	+#define QM_REG_WFQPFCRD_RT_SIZE 160
	4715	+#define QM_REG_WFQPFENABLE_RT_OFFSET 30530
	4716	+#define QM_REG_WFQVPENABLE_RT_OFFSET 30531
	4717	+#define QM_REG_BASEADDRTXPQ_RT_OFFSET 30532
	4718	+#define QM_REG_BASEADDRTXPQ_RT_SIZE 512
	4719	+#define QM_REG_TXPQMAP_RT_OFFSET 31044
	4720	+#define QM_REG_TXPQMAP_RT_SIZE 512
	4721	+#define QM_REG_WFQVPWEIGHT_RT_OFFSET 31556
	4722	+#define QM_REG_WFQVPWEIGHT_RT_SIZE 512
	4723	+#define QM_REG_WFQVPCRD_RT_OFFSET 32068
	4724	+#define QM_REG_WFQVPCRD_RT_SIZE 512
	4725	+#define QM_REG_WFQVPMAP_RT_OFFSET 32580
	4726	+#define QM_REG_WFQVPMAP_RT_SIZE 512
	4727	+#define QM_REG_PTRTBLTX_RT_OFFSET 33092
	4728	+#define QM_REG_PTRTBLTX_RT_SIZE 1024
	4729	+#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 34116
	4730	+#define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
	4731	+#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34276
	4732	+#define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 34277
	4733	+#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34278
	4734	+#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34279
	4735	+#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34280
	4736	+#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34281
	4737	+#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34282
	4738	+#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34283
	4739	+#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
	4740	+#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34287
	4741	+#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
	4742	+#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34291
	4743	+#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
	4744	+#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34323
	4745	+#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
	4746	+#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34339
	4747	+#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
	4748	+#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34355
	4749	+#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
	4750	+#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34371
	4751	+#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
	4752	+#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34387
	4753	+#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 34388
	4754	+#define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8
	4755	+#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34396
	4756	+#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34397
	4757	+#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34398
	4758	+#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34399
	4759	+#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34400
	4760	+#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34401
	4761	+#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34402
	4762	+#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34403
	4763	+#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34404
	4764	+#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34405
	4765	+#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34406
	4766	+#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34407
	4767	+#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34408
	4768	+#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34409
	4769	+#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34410
	4770	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34411
	4771	+#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34412
	4772	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34413
	4773	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34414
	4774	+#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34415
	4775	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34416
	4776	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34417
	4777	+#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34418
	4778	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34419
	4779	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34420
	4780	+#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34421
	4781	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34422
	4782	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34423
	4783	+#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34424
	4784	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34425
	4785	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34426
	4786	+#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34427
	4787	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34428
	4788	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34429
	4789	+#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34430
	4790	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34431
	4791	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34432
	4792	+#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34433
	4793	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34434
	4794	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34435
	4795	+#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34436
	4796	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34437
	4797	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34438
	4798	+#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34439
	4799	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34440
	4800	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34441
	4801	+#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34442
	4802	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34443
	4803	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34444
	4804	+#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34445
	4805	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34446
	4806	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34447
	4807	+#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34448
	4808	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34449
	4809	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34450
	4810	+#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34451
	4811	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34452
	4812	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34453
	4813	+#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34454
	4814	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34455
	4815	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34456
	4816	+#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34457
	4817	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34458
	4818	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34459
	4819	+#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34460
	4820	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34461
	4821	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34462
	4822	+#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34463
	4823	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34464
	4824	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34465
	4825	+#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34466
	4826	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34467
	4827	+#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34468
	4828	+#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34469
	4829	+#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34470
	4830	+#define XCM_REG_CON_PHY_Q3_RT_OFFSET 34471
5036	4831
5037		-#define RUNTIME_ARRAY_SIZE 43022
5038		-
	4832	+#define RUNTIME_ARRAY_SIZE 34472
5039	4833
5040	4834	/* Init Callbacks */
5041	4835	#define DMAE_READY_CB 0
..	..	@@ -5557,9 +5351,9 @@
5557	5351	struct pstorm_eth_conn_st_ctx pstorm_st_context;
5558	5352	struct xstorm_eth_conn_st_ctx xstorm_st_context;
5559	5353	struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context;
	5354	+ struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
5560	5355	struct ystorm_eth_conn_st_ctx ystorm_st_context;
5561	5356	struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context;
5562		- struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
5563	5357	struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context;
5564	5358	struct ustorm_eth_conn_st_ctx ustorm_st_context;
5565	5359	struct mstorm_eth_conn_st_ctx mstorm_st_context;
..	..	@@ -5589,6 +5383,16 @@
5589	5383	ETH_FILTERS_VNI_ADD_FAIL_FULL,
5590	5384	ETH_FILTERS_VNI_ADD_FAIL_DUP,
5591	5385	ETH_FILTERS_GFT_UPDATE_FAIL,
	5386	+ ETH_RX_QUEUE_FAIL_LOAD_VF_DATA,
	5387	+ ETH_FILTERS_GFS_ADD_FILTER_FAIL_MAX_HOPS,
	5388	+ ETH_FILTERS_GFS_ADD_FILTER_FAIL_NO_FREE_ENRTY,
	5389	+ ETH_FILTERS_GFS_ADD_FILTER_FAIL_ALREADY_EXISTS,
	5390	+ ETH_FILTERS_GFS_ADD_FILTER_FAIL_PCI_ERROR,
	5391	+ ETH_FILTERS_GFS_ADD_FINLER_FAIL_MAGIC_NUM_ERROR,
	5392	+ ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAX_HOPS,
	5393	+ ETH_FILTERS_GFS_DEL_FILTER_FAIL_NO_MATCH_ENRTY,
	5394	+ ETH_FILTERS_GFS_DEL_FILTER_FAIL_PCI_ERROR,
	5395	+ ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAGIC_NUM_ERROR,
5592	5396	MAX_ETH_ERROR_CODE
5593	5397	};
5594	5398
..	..	@@ -5612,6 +5416,11 @@
5612	5416	ETH_EVENT_RX_CREATE_GFT_ACTION,
5613	5417	ETH_EVENT_RX_GFT_UPDATE_FILTER,
5614	5418	ETH_EVENT_TX_QUEUE_UPDATE,
	5419	+ ETH_EVENT_RGFS_ADD_FILTER,
	5420	+ ETH_EVENT_RGFS_DEL_FILTER,
	5421	+ ETH_EVENT_TGFS_ADD_FILTER,
	5422	+ ETH_EVENT_TGFS_DEL_FILTER,
	5423	+ ETH_EVENT_GFS_COUNTERS_REPORT_REQUEST,
5615	5424	MAX_ETH_EVENT_OPCODE
5616	5425	};
5617	5426
..	..	@@ -5661,6 +5470,14 @@
5661	5470	MAX_ETH_FILTER_TYPE
5662	5471	};
5663	5472
	5473	+/* inner to inner vlan priority translation configurations */
	5474	+struct eth_in_to_in_pri_map_cfg {
	5475	+ u8 inner_vlan_pri_remap_en;
	5476	+ u8 reserved[7];
	5477	+ u8 non_rdma_in_to_in_pri_map[8];
	5478	+ u8 rdma_in_to_in_pri_map[8];
	5479	+};
	5480	+
5664	5481	/* Eth IPv4 Fragment Type */
5665	5482	enum eth_ipv4_frag_type {
5666	5483	ETH_IPV4_NOT_FRAG,
..	..	@@ -5696,18 +5513,31 @@
5696	5513	ETH_RAMROD_RX_CREATE_GFT_ACTION,
5697	5514	ETH_RAMROD_GFT_UPDATE_FILTER,
5698	5515	ETH_RAMROD_TX_QUEUE_UPDATE,
	5516	+ ETH_RAMROD_RGFS_FILTER_ADD,
	5517	+ ETH_RAMROD_RGFS_FILTER_DEL,
	5518	+ ETH_RAMROD_TGFS_FILTER_ADD,
	5519	+ ETH_RAMROD_TGFS_FILTER_DEL,
	5520	+ ETH_RAMROD_GFS_COUNTERS_REPORT_REQUEST,
5699	5521	MAX_ETH_RAMROD_CMD_ID
5700	5522	};
5701	5523
5702	5524	/* Return code from eth sp ramrods */
5703	5525	struct eth_return_code {
5704	5526	u8 value;
5705		-#define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F
5706		-#define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
5707		-#define ETH_RETURN_CODE_RESERVED_MASK 0x3
5708		-#define ETH_RETURN_CODE_RESERVED_SHIFT 5
5709		-#define ETH_RETURN_CODE_RX_TX_MASK 0x1
5710		-#define ETH_RETURN_CODE_RX_TX_SHIFT 7
	5527	+#define ETH_RETURN_CODE_ERR_CODE_MASK 0x3F
	5528	+#define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
	5529	+#define ETH_RETURN_CODE_RESERVED_MASK 0x1
	5530	+#define ETH_RETURN_CODE_RESERVED_SHIFT 6
	5531	+#define ETH_RETURN_CODE_RX_TX_MASK 0x1
	5532	+#define ETH_RETURN_CODE_RX_TX_SHIFT 7
	5533	+};
	5534	+
	5535	+/* tx destination enum */
	5536	+enum eth_tx_dst_mode_config_enum {
	5537	+ ETH_TX_DST_MODE_CONFIG_DISABLE,
	5538	+ ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_BD,
	5539	+ ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_VPORT,
	5540	+ MAX_ETH_TX_DST_MODE_CONFIG_ENUM
5711	5541	};
5712	5542
5713	5543	/* What to do in case an error occurs */
..	..	@@ -5734,8 +5564,10 @@
5734	5564	#define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
5735	5565	#define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
5736	5566	#define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
5737		-#define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
5738		-#define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
	5567	+#define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_MASK 0x1
	5568	+#define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_SHIFT 7
	5569	+#define ETH_TX_ERR_VALS_RESERVED_MASK 0xFF
	5570	+#define ETH_TX_ERR_VALS_RESERVED_SHIFT 8
5739	5571	};
5740	5572
5741	5573	/* vport rss configuration data */
..	..	@@ -5765,7 +5597,6 @@
5765	5597	u8 tbl_size;
5766	5598	__le32 reserved2[2];
5767	5599	__le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
5768		-
5769	5600	__le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
5770	5601	__le32 reserved3[2];
5771	5602	};
..	..	@@ -5967,7 +5798,7 @@
5967	5798	u8 inner_vlan_removal_en;
5968	5799	};
5969	5800
5970		-/* Ramrod data for rx queue start ramrod */
	5801	+/* Ramrod data for tx queue start ramrod */
5971	5802	struct tx_queue_start_ramrod_data {
5972	5803	__le16 sb_id;
5973	5804	u8 sb_index;
..	..	@@ -5980,16 +5811,14 @@
5980	5811	#define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
5981	5812	#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
5982	5813	#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
5983		-#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
5984		-#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
5985	5814	#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
5986		-#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
	5815	+#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 2
5987	5816	#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
5988		-#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
	5817	+#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 3
5989	5818	#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
5990		-#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
5991		-#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
5992		-#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
	5819	+#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 4
	5820	+#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x7
	5821	+#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 5
5993	5822	u8 pxp_st_hint;
5994	5823	u8 pxp_tph_valid_bd;
5995	5824	u8 pxp_tph_valid_pkt;
..	..	@@ -6018,6 +5847,14 @@
6018	5847	struct regpair reserved1[5];
6019	5848	};
6020	5849
	5850	+/* Inner to Inner VLAN priority map update mode */
	5851	+enum update_in_to_in_pri_map_mode_enum {
	5852	+ ETH_IN_TO_IN_PRI_MAP_UPDATE_DISABLED,
	5853	+ ETH_IN_TO_IN_PRI_MAP_UPDATE_NON_RDMA_TBL,
	5854	+ ETH_IN_TO_IN_PRI_MAP_UPDATE_RDMA_TBL,
	5855	+ MAX_UPDATE_IN_TO_IN_PRI_MAP_MODE_ENUM
	5856	+};
	5857	+
6021	5858	/* Ramrod data for vport update ramrod */
6022	5859	struct vport_filter_update_ramrod_data {
6023	5860	struct eth_filter_cmd_header filter_cmd_hdr;
..	..	@@ -6037,18 +5874,23 @@
6037	5874	__le16 default_vlan;
6038	5875	u8 tx_switching_en;
6039	5876	u8 anti_spoofing_en;
6040		-
6041	5877	u8 default_vlan_en;
6042		-
6043	5878	u8 handle_ptp_pkts;
6044	5879	u8 silent_vlan_removal_en;
6045	5880	u8 untagged;
6046	5881	struct eth_tx_err_vals tx_err_behav;
6047		-
6048	5882	u8 zero_placement_offset;
6049	5883	u8 ctl_frame_mac_check_en;
6050	5884	u8 ctl_frame_ethtype_check_en;
6051		- u8 reserved[1];
	5885	+ u8 reserved0;
	5886	+ u8 reserved1;
	5887	+ u8 tx_dst_port_mode_config;
	5888	+ u8 dst_vport_id;
	5889	+ u8 tx_dst_port_mode;
	5890	+ u8 dst_vport_id_valid;
	5891	+ u8 wipe_inner_vlan_pri_en;
	5892	+ u8 reserved2[2];
	5893	+ struct eth_in_to_in_pri_map_cfg in_to_in_vlan_pri_map_cfg;
6052	5894	};
6053	5895
6054	5896	/* Ramrod data for vport stop ramrod */
..	..	@@ -6100,7 +5942,9 @@
6100	5942	u8 update_ctl_frame_checks_en_flg;
6101	5943	u8 ctl_frame_mac_check_en;
6102	5944	u8 ctl_frame_ethtype_check_en;
6103		- u8 reserved[15];
	5945	+ u8 update_in_to_in_pri_map_mode;
	5946	+ u8 in_to_in_pri_map[8];
	5947	+ u8 reserved[6];
6104	5948	};
6105	5949
6106	5950	struct vport_update_ramrod_mcast {
..	..	@@ -6605,19 +6449,6 @@
6605	6449	__le16 conn_dpi;
6606	6450	};
6607	6451
6608		-/* GFT CAM line struct */
6609		-struct gft_cam_line {
6610		- __le32 camline;
6611		-#define GFT_CAM_LINE_VALID_MASK 0x1
6612		-#define GFT_CAM_LINE_VALID_SHIFT 0
6613		-#define GFT_CAM_LINE_DATA_MASK 0x3FFF
6614		-#define GFT_CAM_LINE_DATA_SHIFT 1
6615		-#define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF
6616		-#define GFT_CAM_LINE_MASK_BITS_SHIFT 15
6617		-#define GFT_CAM_LINE_RESERVED1_MASK 0x7
6618		-#define GFT_CAM_LINE_RESERVED1_SHIFT 29
6619		-};
6620		-
6621	6452	/* GFT CAM line struct with fields breakout */
6622	6453	struct gft_cam_line_mapped {
6623	6454	__le32 camline;
..	..	@@ -6647,10 +6478,6 @@
6647	6478	#define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29
6648	6479	};
6649	6480
6650		-union gft_cam_line_union {
6651		- struct gft_cam_line cam_line;
6652		- struct gft_cam_line_mapped cam_line_mapped;
6653		-};
6654	6481
6655	6482	/* Used in gft_profile_key: Indication for ip version */
6656	6483	enum gft_profile_ip_version {
..	..	@@ -6931,7 +6758,7 @@
6931	6758
6932	6759	/* The roce task context of Ustorm */
6933	6760	struct ustorm_rdma_task_st_ctx {
6934		- struct regpair temp[2];
	6761	+ struct regpair temp[6];
6935	6762	};
6936	6763
6937	6764	struct e4_ustorm_rdma_task_ag_ctx {
..	..	@@ -6943,8 +6770,8 @@
6943	6770	#define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6944	6771	#define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6945	6772	#define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6946		-#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1
6947		-#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5
	6773	+#define E4_USTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
	6774	+#define E4_USTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6948	6775	#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
6949	6776	#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
6950	6777	u8 flags1;
..	..	@@ -6974,29 +6801,29 @@
6974	6801	#define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6975	6802	#define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
6976	6803	u8 flags3;
6977		-#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6978		-#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0
6979		-#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6980		-#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
6981		-#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6982		-#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2
6983		-#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6984		-#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
6985		-#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
6986		-#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
	6804	+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_MASK 0x1
	6805	+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_SHIFT 0
	6806	+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
	6807	+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
	6808	+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_MASK 0x1
	6809	+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_SHIFT 2
	6810	+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
	6811	+#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
	6812	+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
	6813	+#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
6987	6814	__le32 dif_err_intervals;
6988	6815	__le32 dif_error_1st_interval;
6989		- __le32 sq_cons;
6990		- __le32 dif_runt_value;
	6816	+ __le32 dif_rxmit_cons;
	6817	+ __le32 dif_rxmit_prod;
6991	6818	__le32 sge_index;
6992		- __le32 reg5;
	6819	+ __le32 sq_cons;
6993	6820	u8 byte2;
6994	6821	u8 byte3;
6995		- __le16 word1;
6996		- __le16 word2;
	6822	+ __le16 dif_write_cons;
	6823	+ __le16 dif_write_prod;
6997	6824	__le16 word3;
6998		- __le32 reg6;
6999		- __le32 reg7;
	6825	+ __le32 dif_error_buffer_address_lo;
	6826	+ __le32 dif_error_buffer_address_hi;
7000	6827	};
7001	6828
7002	6829	/* RDMA task context */
..	..	@@ -7044,7 +6871,12 @@
7044	6871	u8 pbl_log_page_size;
7045	6872	u8 toggle_bit;
7046	6873	__le16 int_timeout;
7047		- __le16 reserved1;
	6874	+ u8 vf_id;
	6875	+ u8 flags;
	6876	+#define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
	6877	+#define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 0
	6878	+#define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_MASK 0x7F
	6879	+#define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_SHIFT 1
7048	6880	};
7049	6881
7050	6882	/* rdma deregister tid ramrod data */
..	..	@@ -7088,6 +6920,7 @@
7088	6920	RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
7089	6921	RDMA_RETURN_RESIZE_CQ_ERR,
7090	6922	RDMA_RETURN_NIG_DRAIN_REQ,
	6923	+ RDMA_RETURN_GENERAL_ERR,
7091	6924	MAX_RDMA_FW_RETURN_CODE
7092	6925	};
7093	6926
..	..	@@ -7101,7 +6934,10 @@
7101	6934	u8 relaxed_ordering;
7102	6935	__le16 first_reg_srq_id;
7103	6936	__le32 reg_srq_base_addr;
7104		- __le32 reserved;
	6937	+ u8 searcher_mode;
	6938	+ u8 pvrdma_mode;
	6939	+ u8 max_num_ns_log;
	6940	+ u8 reserved;
7105	6941	};
7106	6942
7107	6943	/* rdma function init ramrod data */
..	..	@@ -7191,16 +7027,20 @@
7191	7027	#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
7192	7028	#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
7193	7029	#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
7194		-#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F
7195		-#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2
	7030	+#define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
	7031	+#define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 2
	7032	+#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x1F
	7033	+#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 3
7196	7034	u8 pbl_log_page_size;
7197	7035	__le16 pbl_num_pages;
7198	7036	__le32 max_cqes;
7199	7037	struct regpair pbl_addr;
7200	7038	struct regpair output_params_addr;
	7039	+ u8 vf_id;
	7040	+ u8 reserved1[7];
7201	7041	};
7202	7042
7203		-/* The rdma storm context of Mstorm */
	7043	+/* The rdma SRQ context */
7204	7044	struct rdma_srq_context {
7205	7045	struct regpair temp[8];
7206	7046	};
..	..	@@ -7247,6 +7087,7 @@
7247	7087	MAX_RDMA_TID_TYPE
7248	7088	};
7249	7089
	7090	+/* The rdma XRC SRQ context */
7250	7091	struct rdma_xrc_srq_context {
7251	7092	struct regpair temp[9];
7252	7093	};
..	..	@@ -7388,7 +7229,7 @@
7388	7229	#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
7389	7230	#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
7390	7231	u8 byte2;
7391		- u8 byte3;
	7232	+ u8 nvmf_only;
7392	7233	__le16 conn_dpi;
7393	7234	__le16 word1;
7394	7235	__le32 cq_cons;
..	..	@@ -7428,12 +7269,12 @@
7428	7269	#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_SHIFT 2
7429	7270	#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK 0x1
7430	7271	#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_SHIFT 3
7431		-#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT12_MASK 0x1
7432		-#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT12_SHIFT 4
	7272	+#define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
	7273	+#define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4
7433	7274	#define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
7434	7275	#define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5
7435		-#define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
7436		-#define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT 6
	7276	+#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT14_MASK 0x1
	7277	+#define E4_XSTORM_ROCE_CONN_AG_CTX_BIT14_SHIFT 6
7437	7278	#define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
7438	7279	#define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
7439	7280	u8 flags2;
..	..	@@ -7757,9 +7598,9 @@
7757	7598	struct regpair temp[6];
7758	7599	};
7759	7600
7760		-/* The roce storm context of Ystorm */
	7601	+/* The roce storm context of Ustorm */
7761	7602	struct ustorm_roce_conn_st_ctx {
7762		- struct regpair temp[12];
	7603	+ struct regpair temp[14];
7763	7604	};
7764	7605
7765	7606	/* roce connection context */
..	..	@@ -7777,6 +7618,7 @@
7777	7618	struct mstorm_roce_conn_st_ctx mstorm_st_context;
7778	7619	struct regpair mstorm_st_padding[2];
7779	7620	struct ustorm_roce_conn_st_ctx ustorm_st_context;
	7621	+ struct regpair ustorm_st_padding[2];
7780	7622	};
7781	7623
7782	7624	/* roce cqes statistics */
..	..	@@ -7831,7 +7673,17 @@
7831	7673	struct regpair qp_handle_for_cqe;
7832	7674	struct regpair qp_handle_for_async;
7833	7675	u8 stats_counter_id;
7834		- u8 reserved3[7];
	7676	+ u8 vf_id;
	7677	+ u8 vport_id;
	7678	+ u8 flags2;
	7679	+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK 0x1
	7680	+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT 0
	7681	+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
	7682	+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_SHIFT 1
	7683	+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x3F
	7684	+#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 2
	7685	+ u8 name_space;
	7686	+ u8 reserved3[3];
7835	7687	__le16 regular_latency_phy_queue;
7836	7688	__le16 dpi;
7837	7689	};
..	..	@@ -7859,8 +7711,10 @@
7859	7711	#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11
7860	7712	#define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1
7861	7713	#define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT 16
7862		-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x7FFF
7863		-#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 17
	7714	+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_MASK 0x1
	7715	+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_SHIFT 17
	7716	+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x3FFF
	7717	+#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 18
7864	7718	__le16 xrc_domain;
7865	7719	u8 max_ird;
7866	7720	u8 traffic_class;
..	..	@@ -7887,10 +7741,14 @@
7887	7741	struct regpair qp_handle_for_cqe;
7888	7742	struct regpair qp_handle_for_async;
7889	7743	__le16 low_latency_phy_queue;
7890		- u8 reserved2[2];
	7744	+ u8 vf_id;
	7745	+ u8 vport_id;
7891	7746	__le32 cq_cid;
7892	7747	__le16 regular_latency_phy_queue;
7893	7748	__le16 dpi;
	7749	+ __le32 src_qp_id;
	7750	+ u8 name_space;
	7751	+ u8 reserved3[3];
7894	7752	};
7895	7753
7896	7754	/* roce DCQCN received statistics */
..	..	@@ -7924,6 +7782,8 @@
7924	7782	/* RoCE destroy qp responder ramrod data */
7925	7783	struct roce_destroy_qp_resp_ramrod_data {
7926	7784	struct regpair output_params_addr;
	7785	+ __le32 src_qp_id;
	7786	+ __le32 reserved;
7927	7787	};
7928	7788
7929	7789	/* roce error statistics */
..	..	@@ -7954,6 +7814,7 @@
7954	7814	ROCE_EVENT_DESTROY_QP,
7955	7815	ROCE_EVENT_CREATE_UD_QP,
7956	7816	ROCE_EVENT_DESTROY_UD_QP,
	7817	+ ROCE_EVENT_FUNC_UPDATE,
7957	7818	MAX_ROCE_EVENT_OPCODE
7958	7819	};
7959	7820
..	..	@@ -7962,7 +7823,13 @@
7962	7823	u8 ll2_queue_id;
7963	7824	u8 cnp_vlan_priority;
7964	7825	u8 cnp_dscp;
7965		- u8 reserved;
	7826	+ u8 flags;
	7827	+#define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
	7828	+#define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0
	7829	+#define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
	7830	+#define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_SHIFT 1
	7831	+#define ROCE_INIT_FUNC_PARAMS_RESERVED0_MASK 0x3F
	7832	+#define ROCE_INIT_FUNC_PARAMS_RESERVED0_SHIFT 2
7966	7833	__le32 cnp_send_timeout;
7967	7834	__le16 rl_offset;
7968	7835	u8 rl_count_log;
..	..	@@ -8000,8 +7867,8 @@
8000	7867	#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9
8001	7868	#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
8002	7869	#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10
8003		-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1
8004		-#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 13
	7870	+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
	7871	+#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 13
8005	7872	#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3
8006	7873	#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 14
8007	7874	u8 fields;
..	..	@@ -8047,8 +7914,8 @@
8047	7914	#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
8048	7915	#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
8049	7916	#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9
8050		-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1
8051		-#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 10
	7917	+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
	7918	+#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 10
8052	7919	#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x1F
8053	7920	#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 11
8054	7921	u8 fields;
..	..	@@ -8089,7 +7956,7 @@
8089	7956	/* RoCE query qp responder output params */
8090	7957	struct roce_query_qp_resp_output_params {
8091	7958	__le32 psn;
8092		- __le32 err_flag;
	7959	+ __le32 flags;
8093	7960	#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
8094	7961	#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
8095	7962	#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
..	..	@@ -8109,7 +7976,22 @@
8109	7976	ROCE_RAMROD_DESTROY_QP,
8110	7977	ROCE_RAMROD_CREATE_UD_QP,
8111	7978	ROCE_RAMROD_DESTROY_UD_QP,
	7979	+ ROCE_RAMROD_FUNC_UPDATE,
8112	7980	MAX_ROCE_RAMROD_CMD_ID
	7981	+};
	7982	+
	7983	+/* RoCE func init ramrod data */
	7984	+struct roce_update_func_params {
	7985	+ u8 cnp_vlan_priority;
	7986	+ u8 cnp_dscp;
	7987	+ __le16 flags;
	7988	+#define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
	7989	+#define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0
	7990	+#define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
	7991	+#define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_SHIFT 1
	7992	+#define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_MASK 0x3FFF
	7993	+#define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_SHIFT 2
	7994	+ __le32 cnp_send_timeout;
8113	7995	};
8114	7996
8115	7997	struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
..	..	@@ -8141,12 +8023,12 @@
8141	8023	#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
8142	8024	#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
8143	8025	#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
8144		-#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1
8145		-#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4
8146		-#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1
8147		-#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT 5
8148		-#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1
8149		-#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT 6
	8026	+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1
	8027	+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT 4
	8028	+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1
	8029	+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT 5
	8030	+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
	8031	+#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
8150	8032	#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
8151	8033	#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
8152	8034	u8 flags2;
..	..	@@ -8519,8 +8401,8 @@
8519	8401	u8 flags5;
8520	8402	#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8521	8403	#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
8522		-#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8523		-#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
	8404	+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_MASK 0x1
	8405	+#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_SHIFT 1
8524	8406	#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8525	8407	#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
8526	8408	#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
..	..	@@ -8533,13 +8415,13 @@
8533	8415	#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
8534	8416	#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
8535	8417	#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
8536		- __le32 reg0;
	8418	+ __le32 dif_rxmit_cnt;
8537	8419	__le32 snd_nxt_psn;
8538	8420	__le32 snd_max_psn;
8539	8421	__le32 orq_prod;
8540	8422	__le32 reg4;
8541		- __le32 reg5;
8542		- __le32 reg6;
	8423	+ __le32 dif_acked_cnt;
	8424	+ __le32 dif_cnt;
8543	8425	__le32 reg7;
8544	8426	__le32 reg8;
8545	8427	u8 tx_cqe_error_type;
..	..	@@ -8550,7 +8432,7 @@
8550	8432	__le16 snd_sq_cons;
8551	8433	__le16 conn_dpi;
8552	8434	__le16 force_comp_cons;
8553		- __le32 reg9;
	8435	+ __le32 dif_rxmit_acked_cnt;
8554	8436	__le32 reg10;
8555	8437	};
8556	8438
..	..	@@ -8825,10 +8707,10 @@
8825	8707	#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
8826	8708	#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
8827	8709	#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
8828		-#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1
8829		-#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4
8830		-#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1
8831		-#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5
	8710	+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
	8711	+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4
	8712	+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
	8713	+#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5
8832	8714	#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8833	8715	#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
8834	8716	#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
..	..	@@ -9054,10 +8936,10 @@
9054	8936	#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
9055	8937	#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
9056	8938	#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
9057		-#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1
9058		-#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4
9059		-#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1
9060		-#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5
	8939	+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
	8940	+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4
	8941	+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
	8942	+#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5
9061	8943	#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
9062	8944	#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
9063	8945	#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
..	..	@@ -9784,7 +9666,7 @@
9784	9666
9785	9667	/* The iwarp storm context of Ustorm */
9786	9668	struct ustorm_iwarp_conn_st_ctx {
9787		- __le32 reserved[24];
	9669	+ struct regpair reserved[14];
9788	9670	};
9789	9671
9790	9672	/* iwarp connection context */
..	..	@@ -9802,6 +9684,7 @@
9802	9684	struct regpair tstorm_st_padding[2];
9803	9685	struct mstorm_iwarp_conn_st_ctx mstorm_st_context;
9804	9686	struct ustorm_iwarp_conn_st_ctx ustorm_st_context;
	9687	+ struct regpair ustorm_st_padding[2];
9805	9688	};
9806	9689
9807	9690	/* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */
..	..	@@ -9854,7 +9737,8 @@
9854	9737
9855	9738	struct iwarp_eqe_data_mpa_async_completion {
9856	9739	__le16 ulp_data_len;
9857		- u8 reserved[6];
	9740	+ u8 rtr_type_sent;
	9741	+ u8 reserved[5];
9858	9742	};
9859	9743
9860	9744	struct iwarp_eqe_data_tcp_async_completion {
..	..	@@ -9879,7 +9763,7 @@
9879	9763
9880	9764	/* iWARP EQE completion status */
9881	9765	enum iwarp_fw_return_code {
9882		- IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 5,
	9766	+ IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 6,
9883	9767	IWARP_CONN_ERROR_TCP_CONNECTION_RST,
9884	9768	IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT,
9885	9769	IWARP_CONN_ERROR_MPA_ERROR_REJECT,
..	..	@@ -10048,8 +9932,8 @@
10048	9932	* offload ramrod.
10049	9933	*/
10050	9934	struct iwarp_tcp_offload_ramrod_data {
10051		- struct iwarp_offload_params iwarp;
10052	9935	struct tcp_offload_params_opt2 tcp;
	9936	+ struct iwarp_offload_params iwarp;
10053	9937	};
10054	9938
10055	9939	/* iWARP MPA negotiation types */
..	..	@@ -11341,8 +11225,8 @@
11341	11225	u8 flags3;
11342	11226	#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
11343	11227	#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
11344		-#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
11345		-#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 2
	11228	+#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_MASK 0x3
	11229	+#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_SHIFT 2
11346	11230	#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11347	11231	#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4
11348	11232	#define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
..	..	@@ -11364,8 +11248,8 @@
11364	11248	#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4
11365	11249	#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
11366	11250	#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
11367		-#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
11368		-#define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 6
	11251	+#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_MASK 0x1
	11252	+#define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_SHIFT 6
11369	11253	#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11370	11254	#define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
11371	11255	u8 flags5;
..	..	@@ -11597,7 +11481,7 @@
11597	11481	/* The trace in the buffer */
11598	11482	#define MFW_TRACE_EVENTID_MASK 0x00ffff
11599	11483	#define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
11600		-#define MFW_TRACE_PRM_SIZE_SHIFT 16
	11484	+#define MFW_TRACE_PRM_SIZE_OFFSET 16
11601	11485	#define MFW_TRACE_ENTRY_SIZE 3
11602	11486
11603	11487	struct mcp_trace {
..	..	@@ -11652,37 +11536,98 @@
11652	11536
11653	11537	/* PHY configuration */
11654	11538	struct eth_phy_cfg {
11655		- u32 speed;
11656		-#define ETH_SPEED_AUTONEG 0
11657		-#define ETH_SPEED_SMARTLINQ 0x8
	11539	+ u32 speed;
	11540	+#define ETH_SPEED_AUTONEG 0x0
	11541	+#define ETH_SPEED_SMARTLINQ 0x8
11658	11542
11659		- u32 pause;
11660		-#define ETH_PAUSE_NONE 0x0
11661		-#define ETH_PAUSE_AUTONEG 0x1
11662		-#define ETH_PAUSE_RX 0x2
11663		-#define ETH_PAUSE_TX 0x4
	11543	+ u32 pause;
	11544	+#define ETH_PAUSE_NONE 0x0
	11545	+#define ETH_PAUSE_AUTONEG 0x1
	11546	+#define ETH_PAUSE_RX 0x2
	11547	+#define ETH_PAUSE_TX 0x4
11664	11548
11665		- u32 adv_speed;
11666		- u32 loopback_mode;
11667		-#define ETH_LOOPBACK_NONE (0)
11668		-#define ETH_LOOPBACK_INT_PHY (1)
11669		-#define ETH_LOOPBACK_EXT_PHY (2)
11670		-#define ETH_LOOPBACK_EXT (3)
11671		-#define ETH_LOOPBACK_MAC (4)
	11549	+ u32 adv_speed;
11672	11550
11673		- u32 eee_cfg;
	11551	+ u32 loopback_mode;
	11552	+#define ETH_LOOPBACK_NONE 0x0
	11553	+#define ETH_LOOPBACK_INT_PHY 0x1
	11554	+#define ETH_LOOPBACK_EXT_PHY 0x2
	11555	+#define ETH_LOOPBACK_EXT 0x3
	11556	+#define ETH_LOOPBACK_MAC 0x4
	11557	+#define ETH_LOOPBACK_CNIG_AH_ONLY_0123 0x5
	11558	+#define ETH_LOOPBACK_CNIG_AH_ONLY_2301 0x6
	11559	+#define ETH_LOOPBACK_PCS_AH_ONLY 0x7
	11560	+#define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY 0x8
	11561	+#define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY 0x9
	11562	+
	11563	+ u32 eee_cfg;
11674	11564	#define EEE_CFG_EEE_ENABLED BIT(0)
11675	11565	#define EEE_CFG_TX_LPI BIT(1)
11676	11566	#define EEE_CFG_ADV_SPEED_1G BIT(2)
11677	11567	#define EEE_CFG_ADV_SPEED_10G BIT(3)
11678		-#define EEE_TX_TIMER_USEC_MASK (0xfffffff0)
	11568	+#define EEE_TX_TIMER_USEC_MASK 0xfffffff0
11679	11569	#define EEE_TX_TIMER_USEC_OFFSET 4
11680		-#define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00)
11681		-#define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100)
11682		-#define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000)
	11570	+#define EEE_TX_TIMER_USEC_BALANCED_TIME 0xa00
	11571	+#define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME 0x100
	11572	+#define EEE_TX_TIMER_USEC_LATENCY_TIME 0x6000
11683	11573
11684		- u32 feature_config_flags;
11685		-#define ETH_EEE_MODE_ADV_LPI (1 << 0)
	11574	+ u32 deprecated;
	11575	+
	11576	+ u32 fec_mode;
	11577	+#define FEC_FORCE_MODE_MASK 0x000000ff
	11578	+#define FEC_FORCE_MODE_OFFSET 0
	11579	+#define FEC_FORCE_MODE_NONE 0x00
	11580	+#define FEC_FORCE_MODE_FIRECODE 0x01
	11581	+#define FEC_FORCE_MODE_RS 0x02
	11582	+#define FEC_FORCE_MODE_AUTO 0x07
	11583	+#define FEC_EXTENDED_MODE_MASK 0xffffff00
	11584	+#define FEC_EXTENDED_MODE_OFFSET 8
	11585	+#define ETH_EXT_FEC_NONE 0x00000100
	11586	+#define ETH_EXT_FEC_10G_NONE 0x00000200
	11587	+#define ETH_EXT_FEC_10G_BASE_R 0x00000400
	11588	+#define ETH_EXT_FEC_20G_NONE 0x00000800
	11589	+#define ETH_EXT_FEC_20G_BASE_R 0x00001000
	11590	+#define ETH_EXT_FEC_25G_NONE 0x00002000
	11591	+#define ETH_EXT_FEC_25G_BASE_R 0x00004000
	11592	+#define ETH_EXT_FEC_25G_RS528 0x00008000
	11593	+#define ETH_EXT_FEC_40G_NONE 0x00010000
	11594	+#define ETH_EXT_FEC_40G_BASE_R 0x00020000
	11595	+#define ETH_EXT_FEC_50G_NONE 0x00040000
	11596	+#define ETH_EXT_FEC_50G_BASE_R 0x00080000
	11597	+#define ETH_EXT_FEC_50G_RS528 0x00100000
	11598	+#define ETH_EXT_FEC_50G_RS544 0x00200000
	11599	+#define ETH_EXT_FEC_100G_NONE 0x00400000
	11600	+#define ETH_EXT_FEC_100G_BASE_R 0x00800000
	11601	+#define ETH_EXT_FEC_100G_RS528 0x01000000
	11602	+#define ETH_EXT_FEC_100G_RS544 0x02000000
	11603	+
	11604	+ u32 extended_speed;
	11605	+#define ETH_EXT_SPEED_MASK 0x0000ffff
	11606	+#define ETH_EXT_SPEED_OFFSET 0
	11607	+#define ETH_EXT_SPEED_AN 0x00000001
	11608	+#define ETH_EXT_SPEED_1G 0x00000002
	11609	+#define ETH_EXT_SPEED_10G 0x00000004
	11610	+#define ETH_EXT_SPEED_20G 0x00000008
	11611	+#define ETH_EXT_SPEED_25G 0x00000010
	11612	+#define ETH_EXT_SPEED_40G 0x00000020
	11613	+#define ETH_EXT_SPEED_50G_BASE_R 0x00000040
	11614	+#define ETH_EXT_SPEED_50G_BASE_R2 0x00000080
	11615	+#define ETH_EXT_SPEED_100G_BASE_R2 0x00000100
	11616	+#define ETH_EXT_SPEED_100G_BASE_R4 0x00000200
	11617	+#define ETH_EXT_SPEED_100G_BASE_P4 0x00000400
	11618	+#define ETH_EXT_ADV_SPEED_MASK 0xffff0000
	11619	+#define ETH_EXT_ADV_SPEED_OFFSET 16
	11620	+#define ETH_EXT_ADV_SPEED_RESERVED 0x00010000
	11621	+#define ETH_EXT_ADV_SPEED_1G 0x00020000
	11622	+#define ETH_EXT_ADV_SPEED_10G 0x00040000
	11623	+#define ETH_EXT_ADV_SPEED_20G 0x00080000
	11624	+#define ETH_EXT_ADV_SPEED_25G 0x00100000
	11625	+#define ETH_EXT_ADV_SPEED_40G 0x00200000
	11626	+#define ETH_EXT_ADV_SPEED_50G_BASE_R 0x00400000
	11627	+#define ETH_EXT_ADV_SPEED_50G_BASE_R2 0x00800000
	11628	+#define ETH_EXT_ADV_SPEED_100G_BASE_R2 0x01000000
	11629	+#define ETH_EXT_ADV_SPEED_100G_BASE_R4 0x02000000
	11630	+#define ETH_EXT_ADV_SPEED_100G_BASE_P4 0x04000000
11686	11631	};
11687	11632
11688	11633	struct port_mf_cfg {
..	..	@@ -12011,41 +11956,36 @@
12011	11956	};
12012	11957
12013	11958	struct public_port {
12014		- u32 validity_map;
	11959	+ u32 validity_map;
12015	11960
12016		- u32 link_status;
12017		-#define LINK_STATUS_LINK_UP 0x00000001
12018		-#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
12019		-#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1)
12020		-#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
12021		-#define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
12022		-#define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
12023		-#define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
12024		-#define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
12025		-#define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
12026		-#define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
12027		-
12028		-#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
12029		-
12030		-#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
12031		-#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
12032		-
	11961	+ u32 link_status;
	11962	+#define LINK_STATUS_LINK_UP 0x00000001
	11963	+#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
	11964	+#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1)
	11965	+#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
	11966	+#define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
	11967	+#define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
	11968	+#define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
	11969	+#define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
	11970	+#define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
	11971	+#define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
	11972	+#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
	11973	+#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
	11974	+#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
12033	11975	#define LINK_STATUS_PFC_ENABLED 0x00000100
12034		-#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
12035		-#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
	11976	+#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
	11977	+#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
12036	11978	#define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
12037	11979	#define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
12038	11980	#define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
12039	11981	#define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
12040	11982	#define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
12041	11983	#define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
12042		-
12043		-#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
	11984	+#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000c0000
12044	11985	#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
12045	11986	#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18)
12046	11987	#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
12047	11988	#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
12048		-
12049	11989	#define LINK_STATUS_SFP_TX_FAULT 0x00100000
12050	11990	#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
12051	11991	#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
..	..	@@ -12053,6 +11993,11 @@
12053	11993	#define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
12054	11994	#define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
12055	11995	#define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
	11996	+
	11997	+#define LINK_STATUS_FEC_MODE_MASK 0x38000000
	11998	+#define LINK_STATUS_FEC_MODE_NONE (0 << 27)
	11999	+#define LINK_STATUS_FEC_MODE_FIRECODE_CL74 (1 << 27)
	12000	+#define LINK_STATUS_FEC_MODE_RS_CL91 (2 << 27)
12056	12001
12057	12002	u32 link_status1;
12058	12003	u32 ext_phy_fw_version;
..	..	@@ -12089,13 +12034,64 @@
12089	12034	struct dcbx_mib operational_dcbx_mib;
12090	12035
12091	12036	u32 reserved[2];
12092		- u32 transceiver_data;
12093		-#define ETH_TRANSCEIVER_STATE_MASK 0x000000FF
12094		-#define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
12095		-#define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
12096		-#define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
12097		-#define ETH_TRANSCEIVER_STATE_VALID 0x00000003
12098		-#define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
	12037	+
	12038	+ u32 transceiver_data;
	12039	+#define ETH_TRANSCEIVER_STATE_MASK 0x000000ff
	12040	+#define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
	12041	+#define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000
	12042	+#define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
	12043	+#define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
	12044	+#define ETH_TRANSCEIVER_STATE_VALID 0x00000003
	12045	+#define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
	12046	+#define ETH_TRANSCEIVER_TYPE_MASK 0x0000ff00
	12047	+#define ETH_TRANSCEIVER_TYPE_OFFSET 0x8
	12048	+#define ETH_TRANSCEIVER_TYPE_NONE 0x00
	12049	+#define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xff
	12050	+#define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01
	12051	+#define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02
	12052	+#define ETH_TRANSCEIVER_TYPE_1G_LX 0x03
	12053	+#define ETH_TRANSCEIVER_TYPE_1G_SX 0x04
	12054	+#define ETH_TRANSCEIVER_TYPE_10G_SR 0x05
	12055	+#define ETH_TRANSCEIVER_TYPE_10G_LR 0x06
	12056	+#define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07
	12057	+#define ETH_TRANSCEIVER_TYPE_10G_ER 0x08
	12058	+#define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09
	12059	+#define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a
	12060	+#define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b
	12061	+#define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c
	12062	+#define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d
	12063	+#define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e
	12064	+#define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f
	12065	+#define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10
	12066	+#define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11
	12067	+#define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12
	12068	+#define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13
	12069	+#define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14
	12070	+#define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15
	12071	+#define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16
	12072	+#define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17
	12073	+#define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18
	12074	+#define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19
	12075	+#define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a
	12076	+#define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b
	12077	+#define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c
	12078	+#define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d
	12079	+#define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e
	12080	+#define ETH_TRANSCEIVER_TYPE_4x10G 0x1f
	12081	+#define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20
	12082	+#define ETH_TRANSCEIVER_TYPE_1000BASET 0x21
	12083	+#define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22
	12084	+#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30
	12085	+#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
	12086	+#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
	12087	+#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33
	12088	+#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
	12089	+#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
	12090	+#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
	12091	+#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR 0x37
	12092	+#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR 0x38
	12093	+#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR 0x39
	12094	+#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR 0x3a
12099	12095
12100	12096	u32 wol_info;
12101	12097	u32 wol_pkt_len;
..	..	@@ -12161,7 +12157,7 @@
12161	12157	#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
12162	12158
12163	12159	u32 status;
12164		-#define FUNC_STATUS_VLINK_DOWN 0x00000001
	12160	+#define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001
12165	12161
12166	12162	u32 mac_upper;
12167	12163	#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
..	..	@@ -12310,6 +12306,11 @@
12310	12306	RESOURCE_LL2_QUEUE_E = 15,
12311	12307	RESOURCE_RDMA_STATS_QUEUE_E = 16,
12312	12308	RESOURCE_BDQ_E = 17,
	12309	+ RESOURCE_QCN_E = 18,
	12310	+ RESOURCE_LLH_FILTER_E = 19,
	12311	+ RESOURCE_VF_MAC_ADDR = 20,
	12312	+ RESOURCE_LL2_CQS_E = 21,
	12313	+ RESOURCE_VF_CNQS = 22,
12313	12314	RESOURCE_MAX_NUM,
12314	12315	RESOURCE_NUM_INVALID = 0xFFFFFFFF
12315	12316	};
..	..	@@ -12367,6 +12368,13 @@
12367	12368	#define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0)
12368	12369	};
12369	12370
	12371	+struct mdump_retain_data_stc {
	12372	+ u32 valid;
	12373	+ u32 epoch;
	12374	+ u32 pf;
	12375	+ u32 status;
	12376	+};
	12377	+
12370	12378	union drv_union_data {
12371	12379	u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
12372	12380	struct mcp_mac wol_mac;
..	..	@@ -12420,6 +12428,8 @@
12420	12428	#define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
12421	12429	#define DRV_MSG_CODE_NIG_DRAIN 0x30000000
12422	12430	#define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000
	12431	+#define DRV_MSG_CODE_GET_NVM_CFG_OPTION 0x003e0000
	12432	+#define DRV_MSG_CODE_SET_NVM_CFG_OPTION 0x003f0000
12423	12433	#define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000
12424	12434	#define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
12425	12435	#define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
..	..	@@ -12452,8 +12462,14 @@
12452	12462
12453	12463	#define DRV_MSG_CODE_BIST_TEST 0x001e0000
12454	12464	#define DRV_MSG_CODE_SET_LED_MODE 0x00200000
12455		-#define DRV_MSG_CODE_RESOURCE_CMD 0x00230000
	12465	+#define DRV_MSG_CODE_RESOURCE_CMD 0x00230000
	12466	+/* Send crash dump commands with param[3:0] - opcode */
	12467	+#define DRV_MSG_CODE_MDUMP_CMD 0x00250000
12456	12468	#define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000
	12469	+#define DRV_MSG_CODE_GET_ENGINE_CONFIG 0x00370000
	12470	+#define DRV_MSG_CODE_GET_PPFID_BITMAP 0x43000000
	12471	+
	12472	+#define DRV_MSG_CODE_DEBUG_DATA_SEND 0xc0040000
12457	12473
12458	12474	#define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F
12459	12475	#define RESOURCE_CMD_REQ_RESC_SHIFT 0
..	..	@@ -12480,6 +12496,21 @@
12480	12496
12481	12497	#define RESOURCE_DUMP 0
12482	12498
	12499	+/* DRV_MSG_CODE_MDUMP_CMD parameters */
	12500	+#define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f
	12501	+#define DRV_MSG_CODE_MDUMP_ACK 0x01
	12502	+#define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02
	12503	+#define DRV_MSG_CODE_MDUMP_TRIGGER 0x03
	12504	+#define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04
	12505	+#define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05
	12506	+#define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06
	12507	+#define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07
	12508	+#define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08
	12509	+
	12510	+#define DRV_MSG_CODE_HW_DUMP_TRIGGER 0x0a
	12511	+#define DRV_MSG_CODE_MDUMP_GEN_MDUMP2 0x0b
	12512	+#define DRV_MSG_CODE_MDUMP_FREE_MDUMP2 0x0c
	12513	+
12483	12514	#define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000
12484	12515	#define DRV_MSG_CODE_OS_WOL 0x002e0000
12485	12516
..	..	@@ -12495,7 +12526,11 @@
12495	12526	#define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x000000FF
12496	12527	#define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
12497	12528
	12529	+#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI 0x3
	12530	+#define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0
	12531	+#define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
12498	12532	#define DRV_MB_PARAM_NVM_LEN_OFFSET 24
	12533	+#define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
12499	12534
12500	12535	#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
12501	12536	#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
..	..	@@ -12550,39 +12585,68 @@
12550	12585	#define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
12551	12586	#define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
12552	12587
12553		-#define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0
12554		-#define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003
12555		-#define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2
12556		-#define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC
12557		-#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8
12558		-#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00
12559		-#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16
12560		-#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000
	12588	+#define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0
	12589	+#define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003
	12590	+#define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2
	12591	+#define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000fc
	12592	+#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8
	12593	+#define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000ff00
	12594	+#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16
	12595	+#define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xffff0000
12561	12596
12562	12597	/* Resource Allocation params - Driver version support */
12563		-#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
12564		-#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
12565		-#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
12566		-#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
	12598	+#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xffff0000
	12599	+#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
	12600	+#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000ffff
	12601	+#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
12567	12602
12568		-#define DRV_MB_PARAM_BIST_REGISTER_TEST 1
12569		-#define DRV_MB_PARAM_BIST_CLOCK_TEST 2
12570		-#define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
12571		-#define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4
	12603	+#define DRV_MB_PARAM_BIST_REGISTER_TEST 1
	12604	+#define DRV_MB_PARAM_BIST_CLOCK_TEST 2
	12605	+#define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
	12606	+#define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4
12572	12607
12573		-#define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
12574		-#define DRV_MB_PARAM_BIST_RC_PASSED 1
12575		-#define DRV_MB_PARAM_BIST_RC_FAILED 2
12576		-#define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
	12608	+#define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
	12609	+#define DRV_MB_PARAM_BIST_RC_PASSED 1
	12610	+#define DRV_MB_PARAM_BIST_RC_FAILED 2
	12611	+#define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
12577	12612
12578		-#define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
12579		-#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
12580		-#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8
12581		-#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00
	12613	+#define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
	12614	+#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000ff
	12615	+#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8
	12616	+#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000ff00
12582	12617
12583		-#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF
12584		-#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0
12585		-#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002
	12618	+#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000ffff
	12619	+#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0
	12620	+#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002
	12621	+#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL 0x00000004
	12622	+#define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EXT_SPEED_FEC_CONTROL 0x00000008
	12623	+#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000
	12624	+
	12625	+/* DRV_MSG_CODE_DEBUG_DATA_SEND parameters */
	12626	+#define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_OFFSET 0
	12627	+#define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_MASK 0xff
	12628	+
	12629	+/* Driver attributes params */
	12630	+#define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0
	12631	+#define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00ffffff
	12632	+#define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 24
	12633	+#define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xff000000
	12634	+
	12635	+#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET 0
	12636	+#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT 0
	12637	+#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK 0x0000ffff
	12638	+#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT 16
	12639	+#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK 0x00010000
	12640	+#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_SHIFT 17
	12641	+#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK 0x00020000
	12642	+#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_SHIFT 18
	12643	+#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK 0x00040000
	12644	+#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_SHIFT 19
	12645	+#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK 0x00080000
	12646	+#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_SHIFT 20
	12647	+#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK 0x00100000
	12648	+#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_SHIFT 24
	12649	+#define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK 0x0f000000
12586	12650
12587	12651	u32 fw_mb_header;
12588	12652	#define FW_MSG_CODE_MASK 0xffff0000
..	..	@@ -12621,36 +12685,65 @@
12621	12685	#define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000
12622	12686	#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
12623	12687
12624		- u32 fw_mb_param;
12625		-#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
12626		-#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
12627		-#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
12628		-#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
	12688	+#define FW_MSG_CODE_DEBUG_DATA_SEND_INV_ARG 0xb0070000
	12689	+#define FW_MSG_CODE_DEBUG_DATA_SEND_BUF_FULL 0xb0080000
	12690	+#define FW_MSG_CODE_DEBUG_DATA_SEND_NO_BUF 0xb0090000
	12691	+#define FW_MSG_CODE_DEBUG_NOT_ENABLED 0xb00a0000
	12692	+#define FW_MSG_CODE_DEBUG_DATA_SEND_OK 0xb00b0000
12629	12693
12630		- /* get pf rdma protocol command responce */
12631		-#define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0
12632		-#define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1
12633		-#define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
12634		-#define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3
	12694	+#define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000
12635	12695
12636		-/* get MFW feature support response */
12637		-#define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002
	12696	+ u32 fw_mb_param;
	12697	+#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xffff0000
	12698	+#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
	12699	+#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000ffff
	12700	+#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
12638	12701
12639		-#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0)
	12702	+ /* Get PF RDMA protocol command response */
	12703	+#define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0
	12704	+#define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1
	12705	+#define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
	12706	+#define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3
12640	12707
12641		- u32 drv_pulse_mb;
12642		-#define DRV_PULSE_SEQ_MASK 0x00007fff
12643		-#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
12644		-#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
	12708	+ /* Get MFW feature support response */
	12709	+#define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ BIT(0)
	12710	+#define FW_MB_PARAM_FEATURE_SUPPORT_EEE BIT(1)
	12711	+#define FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL BIT(5)
	12712	+#define FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL BIT(6)
	12713	+#define FW_MB_PARAM_FEATURE_SUPPORT_VLINK BIT(16)
12645	12714
12646		- u32 mcp_pulse_mb;
12647		-#define MCP_PULSE_SEQ_MASK 0x00007fff
12648		-#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
12649		-#define MCP_EVENT_MASK 0xffff0000
12650		-#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
	12715	+#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR BIT(0)
12651	12716
12652		- union drv_union_data union_data;
	12717	+#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001
	12718	+#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_SHIFT 0
	12719	+#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002
	12720	+#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_SHIFT 1
	12721	+#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004
	12722	+#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_SHIFT 2
	12723	+#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008
	12724	+#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_SHIFT 3
	12725	+
	12726	+#define FW_MB_PARAM_PPFID_BITMAP_MASK 0xff
	12727	+#define FW_MB_PARAM_PPFID_BITMAP_SHIFT 0
	12728	+
	12729	+ u32 drv_pulse_mb;
	12730	+#define DRV_PULSE_SEQ_MASK 0x00007fff
	12731	+#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
	12732	+#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
	12733	+
	12734	+ u32 mcp_pulse_mb;
	12735	+#define MCP_PULSE_SEQ_MASK 0x00007fff
	12736	+#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
	12737	+#define MCP_EVENT_MASK 0xffff0000
	12738	+#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
	12739	+
	12740	+ union drv_union_data union_data;
12653	12741	};
	12742	+
	12743	+#define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_MASK 0x00ffffff
	12744	+#define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_SHIFT 0
	12745	+#define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_MASK 0xff000000
	12746	+#define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_SHIFT 24
12654	12747
12655	12748	enum MFW_DRV_MSG_TYPE {
12656	12749	MFW_DRV_MSG_LINK_CHANGE,
..	..	@@ -12659,16 +12752,16 @@
12659	12752	MFW_DRV_MSG_LLDP_DATA_UPDATED,
12660	12753	MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
12661	12754	MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
12662		- MFW_DRV_MSG_RESERVED4,
	12755	+ MFW_DRV_MSG_ERROR_RECOVERY,
12663	12756	MFW_DRV_MSG_BW_UPDATE,
12664	12757	MFW_DRV_MSG_S_TAG_UPDATE,
12665	12758	MFW_DRV_MSG_GET_LAN_STATS,
12666	12759	MFW_DRV_MSG_GET_FCOE_STATS,
12667	12760	MFW_DRV_MSG_GET_ISCSI_STATS,
12668	12761	MFW_DRV_MSG_GET_RDMA_STATS,
12669		- MFW_DRV_MSG_BW_UPDATE10,
	12762	+ MFW_DRV_MSG_FAILURE_DETECTED,
12670	12763	MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
12671		- MFW_DRV_MSG_BW_UPDATE11,
	12764	+ MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED,
12672	12765	MFW_DRV_MSG_RESERVED,
12673	12766	MFW_DRV_MSG_GET_TLV_REQ,
12674	12767	MFW_DRV_MSG_OEM_CFG_UPDATE,
..	..	@@ -12937,120 +13030,138 @@
12937	13030	};
12938	13031
12939	13032	struct nvm_cfg_mac_address {
12940		- u32 mac_addr_hi;
12941		-#define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
12942		-#define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
12943		- u32 mac_addr_lo;
	13033	+ u32 mac_addr_hi;
	13034	+#define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000ffff
	13035	+#define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
	13036	+
	13037	+ u32 mac_addr_lo;
12944	13038	};
12945	13039
12946	13040	struct nvm_cfg1_glob {
12947		- u32 generic_cont0;
12948		-#define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
12949		-#define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
12950		-#define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
12951		-#define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
12952		-#define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
12953		-#define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
12954		-#define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
12955		-#define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
12956		-#define NVM_CFG1_GLOB_MF_MODE_BD 0x6
12957		-#define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
12958		- u32 engineering_change[3];
12959		- u32 manufacturing_id;
12960		- u32 serial_number[4];
12961		- u32 pcie_cfg;
12962		- u32 mgmt_traffic;
12963		- u32 core_cfg;
12964		-#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
12965		-#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
12966		-#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
12967		-#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
12968		-#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
12969		-#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
12970		-#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
12971		-#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
12972		-#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB
12973		-#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
12974		-#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
12975		-#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
12976		-#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF
	13041	+ u32 generic_cont0;
	13042	+#define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000ff0
	13043	+#define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
	13044	+#define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
	13045	+#define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
	13046	+#define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
	13047	+#define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
	13048	+#define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
	13049	+#define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
	13050	+#define NVM_CFG1_GLOB_MF_MODE_BD 0x6
	13051	+#define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
12977	13052
12978		- u32 e_lane_cfg1;
12979		- u32 e_lane_cfg2;
12980		- u32 f_lane_cfg1;
12981		- u32 f_lane_cfg2;
12982		- u32 mps10_preemphasis;
12983		- u32 mps10_driver_current;
12984		- u32 mps25_preemphasis;
12985		- u32 mps25_driver_current;
12986		- u32 pci_id;
12987		- u32 pci_subsys_id;
12988		- u32 bar;
12989		- u32 mps10_txfir_main;
12990		- u32 mps10_txfir_post;
12991		- u32 mps25_txfir_main;
12992		- u32 mps25_txfir_post;
12993		- u32 manufacture_ver;
12994		- u32 manufacture_time;
12995		- u32 led_global_settings;
12996		- u32 generic_cont1;
12997		- u32 mbi_version;
12998		-#define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
12999		-#define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
13000		-#define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
13001		-#define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
13002		-#define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
13003		-#define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
13004		- u32 mbi_date;
13005		- u32 misc_sig;
13006		- u32 device_capabilities;
13007		-#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
13008		-#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
13009		-#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
13010		-#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
13011		- u32 power_dissipated;
13012		- u32 power_consumed;
13013		- u32 efi_version;
13014		- u32 multi_network_modes_capability;
13015		- u32 reserved[41];
	13053	+ u32 engineering_change[3];
	13054	+ u32 manufacturing_id;
	13055	+ u32 serial_number[4];
	13056	+ u32 pcie_cfg;
	13057	+ u32 mgmt_traffic;
	13058	+
	13059	+ u32 core_cfg;
	13060	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000ff
	13061	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
	13062	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
	13063	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
	13064	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
	13065	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
	13066	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
	13067	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
	13068	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xb
	13069	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xc
	13070	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xd
	13071	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xe
	13072	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xf
	13073	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X50G_R1 0x11
	13074	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_4X50G_R1 0x12
	13075	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R2 0x13
	13076	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X100G_R2 0x14
	13077	+#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R4 0x15
	13078	+
	13079	+ u32 e_lane_cfg1;
	13080	+ u32 e_lane_cfg2;
	13081	+ u32 f_lane_cfg1;
	13082	+ u32 f_lane_cfg2;
	13083	+ u32 mps10_preemphasis;
	13084	+ u32 mps10_driver_current;
	13085	+ u32 mps25_preemphasis;
	13086	+ u32 mps25_driver_current;
	13087	+ u32 pci_id;
	13088	+ u32 pci_subsys_id;
	13089	+ u32 bar;
	13090	+ u32 mps10_txfir_main;
	13091	+ u32 mps10_txfir_post;
	13092	+ u32 mps25_txfir_main;
	13093	+ u32 mps25_txfir_post;
	13094	+ u32 manufacture_ver;
	13095	+ u32 manufacture_time;
	13096	+ u32 led_global_settings;
	13097	+ u32 generic_cont1;
	13098	+
	13099	+ u32 mbi_version;
	13100	+#define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000ff
	13101	+#define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
	13102	+#define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000ff00
	13103	+#define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
	13104	+#define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00ff0000
	13105	+#define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
	13106	+
	13107	+ u32 mbi_date;
	13108	+ u32 misc_sig;
	13109	+
	13110	+ u32 device_capabilities;
	13111	+#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
	13112	+#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
	13113	+#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
	13114	+#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
	13115	+
	13116	+ u32 power_dissipated;
	13117	+ u32 power_consumed;
	13118	+ u32 efi_version;
	13119	+ u32 multi_net_modes_cap;
	13120	+ u32 reserved[41];
13016	13121	};
13017	13122
13018	13123	struct nvm_cfg1_path {
13019		- u32 reserved[30];
	13124	+ u32 reserved[30];
13020	13125	};
13021	13126
13022	13127	struct nvm_cfg1_port {
13023		- u32 reserved__m_relocated_to_option_123;
13024		- u32 reserved__m_relocated_to_option_124;
13025		- u32 generic_cont0;
13026		-#define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
	13128	+ u32 rel_to_opt123;
	13129	+ u32 rel_to_opt124;
	13130	+
	13131	+ u32 generic_cont0;
	13132	+#define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000f0000
13027	13133	#define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
13028	13134	#define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
13029	13135	#define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
13030	13136	#define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
13031	13137	#define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
13032		-#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
	13138	+#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00f00000
13033	13139	#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
13034	13140	#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
13035	13141	#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
13036	13142	#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
13037		- u32 pcie_cfg;
13038		- u32 features;
13039		- u32 speed_cap_mask;
13040		-#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
	13143	+
	13144	+ u32 pcie_cfg;
	13145	+ u32 features;
	13146	+
	13147	+ u32 speed_cap_mask;
	13148	+#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000ffff
13041	13149	#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
13042	13150	#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
13043	13151	#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
	13152	+#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4
13044	13153	#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
13045	13154	#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
13046	13155	#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
13047	13156	#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
13048		- u32 link_settings;
13049		-#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
	13157	+
	13158	+ u32 link_settings;
	13159	+#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000f
13050	13160	#define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
13051	13161	#define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
13052	13162	#define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
13053	13163	#define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
	13164	+#define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3
13054	13165	#define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
13055	13166	#define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
13056	13167	#define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
..	..	@@ -13061,42 +13172,92 @@
13061	13172	#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
13062	13173	#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
13063	13174	#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
13064		- u32 phy_cfg;
13065		- u32 mgmt_traffic;
	13175	+#define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000e0000
	13176	+#define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17
	13177	+#define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0
	13178	+#define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1
	13179	+#define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2
	13180	+#define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7
13066	13181
13067		- u32 ext_phy;
	13182	+ u32 phy_cfg;
	13183	+ u32 mgmt_traffic;
	13184	+
	13185	+ u32 ext_phy;
13068	13186	/* EEE power saving mode */
13069		-#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000
	13187	+#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00ff0000
13070	13188	#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16
13071	13189	#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0
13072	13190	#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1
13073	13191	#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2
13074	13192	#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3
13075	13193
13076		- u32 mba_cfg1;
13077		- u32 mba_cfg2;
13078		- u32 vf_cfg;
13079		- struct nvm_cfg_mac_address lldp_mac_address;
13080		- u32 led_port_settings;
13081		- u32 transceiver_00;
13082		- u32 device_ids;
13083		- u32 board_cfg;
13084		- u32 mnm_10g_cap;
13085		- u32 mnm_10g_ctrl;
13086		- u32 mnm_10g_misc;
13087		- u32 mnm_25g_cap;
13088		- u32 mnm_25g_ctrl;
13089		- u32 mnm_25g_misc;
13090		- u32 mnm_40g_cap;
13091		- u32 mnm_40g_ctrl;
13092		- u32 mnm_40g_misc;
13093		- u32 mnm_50g_cap;
13094		- u32 mnm_50g_ctrl;
13095		- u32 mnm_50g_misc;
13096		- u32 mnm_100g_cap;
13097		- u32 mnm_100g_ctrl;
13098		- u32 mnm_100g_misc;
13099		- u32 reserved[116];
	13194	+ u32 mba_cfg1;
	13195	+ u32 mba_cfg2;
	13196	+ u32 vf_cfg;
	13197	+ struct nvm_cfg_mac_address lldp_mac_address;
	13198	+ u32 led_port_settings;
	13199	+ u32 transceiver_00;
	13200	+ u32 device_ids;
	13201	+
	13202	+ u32 board_cfg;
	13203	+#define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000ff
	13204	+#define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0
	13205	+#define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0
	13206	+#define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1
	13207	+#define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2
	13208	+#define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3
	13209	+#define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4
	13210	+
	13211	+ u32 mnm_10g_cap;
	13212	+ u32 mnm_10g_ctrl;
	13213	+ u32 mnm_10g_misc;
	13214	+ u32 mnm_25g_cap;
	13215	+ u32 mnm_25g_ctrl;
	13216	+ u32 mnm_25g_misc;
	13217	+ u32 mnm_40g_cap;
	13218	+ u32 mnm_40g_ctrl;
	13219	+ u32 mnm_40g_misc;
	13220	+ u32 mnm_50g_cap;
	13221	+ u32 mnm_50g_ctrl;
	13222	+ u32 mnm_50g_misc;
	13223	+ u32 mnm_100g_cap;
	13224	+ u32 mnm_100g_ctrl;
	13225	+ u32 mnm_100g_misc;
	13226	+
	13227	+ u32 temperature;
	13228	+ u32 ext_phy_cfg1;
	13229	+
	13230	+ u32 extended_speed;
	13231	+#define NVM_CFG1_PORT_EXTENDED_SPEED_MASK 0x0000ffff
	13232	+#define NVM_CFG1_PORT_EXTENDED_SPEED_OFFSET 0
	13233	+#define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_AN 0x1
	13234	+#define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G 0x2
	13235	+#define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G 0x4
	13236	+#define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_20G 0x8
	13237	+#define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_25G 0x10
	13238	+#define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_40G 0x20
	13239	+#define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R 0x40
	13240	+#define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R2 0x80
	13241	+#define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R2 0x100
	13242	+#define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R4 0x200
	13243	+#define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_P4 0x400
	13244	+#define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_MASK 0xffff0000
	13245	+#define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_OFFSET 16
	13246	+#define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_RESERVED 0x1
	13247	+#define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_1G 0x2
	13248	+#define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_10G 0x4
	13249	+#define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_20G 0x8
	13250	+#define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_25G 0x10
	13251	+#define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_40G 0x20
	13252	+#define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R 0x40
	13253	+#define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R2 0x80
	13254	+#define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R2 0x100
	13255	+#define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R4 0x200
	13256	+#define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_P4 0x400
	13257	+
	13258	+ u32 extended_fec_mode;
	13259	+
	13260	+ u32 reserved[112];
13100	13261	};
13101	13262
13102	13263	struct nvm_cfg1_func {
..	..	@@ -13212,6 +13373,21 @@
13212	13373	NVM_TYPE_FCOE_CFG = 0x1f,
13213	13374	NVM_TYPE_ETH_PHY_FW1 = 0x20,
13214	13375	NVM_TYPE_ETH_PHY_FW2 = 0x21,
	13376	+ NVM_TYPE_BDN = 0x22,
	13377	+ NVM_TYPE_8485X_PHY_FW = 0x23,
	13378	+ NVM_TYPE_PUB_KEY = 0x24,
	13379	+ NVM_TYPE_RECOVERY = 0x25,
	13380	+ NVM_TYPE_PLDM = 0x26,
	13381	+ NVM_TYPE_UPK1 = 0x27,
	13382	+ NVM_TYPE_UPK2 = 0x28,
	13383	+ NVM_TYPE_MASTER_KC = 0x29,
	13384	+ NVM_TYPE_BACKUP_KC = 0x2a,
	13385	+ NVM_TYPE_HW_DUMP = 0x2b,
	13386	+ NVM_TYPE_HW_DUMP_OUT = 0x2c,
	13387	+ NVM_TYPE_BIN_NVM_META = 0x30,
	13388	+ NVM_TYPE_ROM_TEST = 0xf0,
	13389	+ NVM_TYPE_88X33X0_PHY_FW = 0x31,
	13390	+ NVM_TYPE_88X33X0_PHY_SLAVE_FW = 0x32,
13215	13391	NVM_TYPE_MAX,
13216	13392	};
13217	13393