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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/net/ethernet/mellanox/mlxsw/i2c.c
..
..
@@ -14,14 +14,17 @@
14
14
 #include "cmd.h"
15
15
 #include "core.h"
16
16
 #include "i2c.h"
17
+#include "resources.h"
17
18
 
18
19
 #define MLXSW_I2C_CIR2_BASE		0x72000
19
20
 #define MLXSW_I2C_CIR_STATUS_OFF	0x18
20
21
 #define MLXSW_I2C_CIR2_OFF_STATUS	(MLXSW_I2C_CIR2_BASE + \
21
22
 					 MLXSW_I2C_CIR_STATUS_OFF)
22
23
 #define MLXSW_I2C_OPMOD_SHIFT		12
24
+#define MLXSW_I2C_EVENT_BIT_SHIFT	22
23
25
 #define MLXSW_I2C_GO_BIT_SHIFT		23
24
26
 #define MLXSW_I2C_CIR_CTRL_STATUS_SHIFT	24
27
+#define MLXSW_I2C_EVENT_BIT		BIT(MLXSW_I2C_EVENT_BIT_SHIFT)
25
28
 #define MLXSW_I2C_GO_BIT		BIT(MLXSW_I2C_GO_BIT_SHIFT)
26
29
 #define MLXSW_I2C_GO_OPMODE		BIT(MLXSW_I2C_OPMOD_SHIFT)
27
30
 #define MLXSW_I2C_SET_IMM_CMD		(MLXSW_I2C_GO_OPMODE | \
..
..
@@ -33,20 +36,24 @@
33
36
 #define MLXSW_I2C_TLV_HDR_SIZE		0x10
34
37
 #define MLXSW_I2C_ADDR_WIDTH		4
35
38
 #define MLXSW_I2C_PUSH_CMD_SIZE		(MLXSW_I2C_ADDR_WIDTH + 4)
39
+#define MLXSW_I2C_SET_EVENT_CMD		(MLXSW_I2C_EVENT_BIT)
40
+#define MLXSW_I2C_PUSH_EVENT_CMD	(MLXSW_I2C_GO_BIT | \
41
+					 MLXSW_I2C_SET_EVENT_CMD)
36
42
 #define MLXSW_I2C_READ_SEMA_SIZE	4
37
43
 #define MLXSW_I2C_PREP_SIZE		(MLXSW_I2C_ADDR_WIDTH + 28)
38
44
 #define MLXSW_I2C_MBOX_SIZE		20
39
45
 #define MLXSW_I2C_MBOX_OUT_PARAM_OFF	12
40
-#define MLXSW_I2C_MAX_BUFF_SIZE		32
41
46
 #define MLXSW_I2C_MBOX_OFFSET_BITS	20
42
47
 #define MLXSW_I2C_MBOX_SIZE_BITS	12
43
48
 #define MLXSW_I2C_ADDR_BUF_SIZE		4
44
-#define MLXSW_I2C_BLK_MAX		32
49
+#define MLXSW_I2C_BLK_DEF		32
45
50
 #define MLXSW_I2C_RETRY			5
46
51
 #define MLXSW_I2C_TIMEOUT_MSECS		5000
52
+#define MLXSW_I2C_MAX_DATA_SIZE		256
47
53
 
48
54
 /**
49
55
  * struct mlxsw_i2c - device private data:
56
+ * @cmd: command attributes;
50
57
  * @cmd.mb_size_in: input mailbox size;
51
58
  * @cmd.mb_off_in: input mailbox offset in register space;
52
59
  * @cmd.mb_size_out: output mailbox size;
..
..
@@ -55,6 +62,7 @@
55
62
  * @dev: I2C device;
56
63
  * @core: switch core pointer;
57
64
  * @bus_info: bus info block;
65
+ * @block_size: maximum block size allowed to pass to under layer;
58
66
  */
59
67
 struct mlxsw_i2c {
60
68
 	struct {
..
..
@@ -67,6 +75,7 @@
67
75
 	struct device *dev;
68
76
 	struct mlxsw_core *core;
69
77
 	struct mlxsw_bus_info bus_info;
78
+	u16 block_size;
70
79
 };
71
80
 
72
81
 #define MLXSW_I2C_READ_MSG(_client, _addr_buf, _buf, _len) {	\
..
..
@@ -167,7 +176,7 @@
167
176
 	return err > 0 ? 0 : err;
168
177
 }
169
178
 
170
-/* Routine posts a command to ASIC though mail box. */
179
+/* Routine posts a command to ASIC through mail box. */
171
180
 static int mlxsw_i2c_write_cmd(struct i2c_client *client,
172
181
 			       struct mlxsw_i2c *mlxsw_i2c,
173
182
 			       int immediate)
..
..
@@ -213,6 +222,66 @@
213
222
 	return 0;
214
223
 }
215
224
 
225
+/* Routine posts initialization command to ASIC through mail box. */
226
+static int
227
+mlxsw_i2c_write_init_cmd(struct i2c_client *client,
228
+			 struct mlxsw_i2c *mlxsw_i2c, u16 opcode, u32 in_mod)
229
+{
230
+	__be32 push_cmd_buf[MLXSW_I2C_PUSH_CMD_SIZE / 4] = {
231
+		0, cpu_to_be32(MLXSW_I2C_PUSH_EVENT_CMD)
232
+	};
233
+	__be32 prep_cmd_buf[MLXSW_I2C_PREP_SIZE / 4] = {
234
+		0, 0, 0, 0, 0, 0,
235
+		cpu_to_be32(client->adapter->nr & 0xffff),
236
+		cpu_to_be32(MLXSW_I2C_SET_EVENT_CMD)
237
+	};
238
+	struct i2c_msg push_cmd =
239
+		MLXSW_I2C_WRITE_MSG(client, push_cmd_buf,
240
+				    MLXSW_I2C_PUSH_CMD_SIZE);
241
+	struct i2c_msg prep_cmd =
242
+		MLXSW_I2C_WRITE_MSG(client, prep_cmd_buf, MLXSW_I2C_PREP_SIZE);
243
+	u8 status;
244
+	int err;
245
+
246
+	push_cmd_buf[1] = cpu_to_be32(MLXSW_I2C_PUSH_EVENT_CMD | opcode);
247
+	prep_cmd_buf[3] = cpu_to_be32(in_mod);
248
+	prep_cmd_buf[7] = cpu_to_be32(MLXSW_I2C_GO_BIT | opcode);
249
+	mlxsw_i2c_set_slave_addr((u8 *)prep_cmd_buf,
250
+				 MLXSW_I2C_CIR2_BASE);
251
+	mlxsw_i2c_set_slave_addr((u8 *)push_cmd_buf,
252
+				 MLXSW_I2C_CIR2_OFF_STATUS);
253
+
254
+	/* Prepare Command Interface Register for transaction */
255
+	err = i2c_transfer(client->adapter, &prep_cmd, 1);
256
+	if (err < 0)
257
+		return err;
258
+	else if (err != 1)
259
+		return -EIO;
260
+
261
+	/* Write out Command Interface Register GO bit to push transaction */
262
+	err = i2c_transfer(client->adapter, &push_cmd, 1);
263
+	if (err < 0)
264
+		return err;
265
+	else if (err != 1)
266
+		return -EIO;
267
+
268
+	/* Wait until go bit is cleared. */
269
+	err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, &status);
270
+	if (err) {
271
+		dev_err(&client->dev, "HW semaphore is not released");
272
+		return err;
273
+	}
274
+
275
+	/* Validate transaction completion status. */
276
+	if (status) {
277
+		dev_err(&client->dev, "Bad transaction completion status %x\n",
278
+			status);
279
+		return -EIO;
280
+	}
281
+
282
+	return 0;
283
+}
284
+
216
285
 /* Routine obtains mail box offsets from ASIC register space. */
217
286
 static int mlxsw_i2c_get_mbox(struct i2c_client *client,
218
287
 			      struct mlxsw_i2c *mlxsw_i2c)
..
..
@@ -248,20 +317,26 @@
248
317
 	struct i2c_client *client = to_i2c_client(dev);
249
318
 	struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client);
250
319
 	unsigned long timeout = msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS);
251
-	u8 tran_buf[MLXSW_I2C_MAX_BUFF_SIZE + MLXSW_I2C_ADDR_BUF_SIZE];
252
320
 	int off = mlxsw_i2c->cmd.mb_off_in, chunk_size, i, j;
253
321
 	unsigned long end;
322
+	u8 *tran_buf;
254
323
 	struct i2c_msg write_tran =
255
-		MLXSW_I2C_WRITE_MSG(client, tran_buf, MLXSW_I2C_PUSH_CMD_SIZE);
324
+		MLXSW_I2C_WRITE_MSG(client, NULL, MLXSW_I2C_PUSH_CMD_SIZE);
256
325
 	int err;
257
326
 
327
+	tran_buf = kmalloc(mlxsw_i2c->block_size + MLXSW_I2C_ADDR_BUF_SIZE,
328
+			   GFP_KERNEL);
329
+	if (!tran_buf)
330
+		return -ENOMEM;
331
+
332
+	write_tran.buf = tran_buf;
258
333
 	for (i = 0; i < num; i++) {
259
-		chunk_size = (in_mbox_size > MLXSW_I2C_BLK_MAX) ?
260
-			     MLXSW_I2C_BLK_MAX : in_mbox_size;
334
+		chunk_size = (in_mbox_size > mlxsw_i2c->block_size) ?
335
+			     mlxsw_i2c->block_size : in_mbox_size;
261
336
 		write_tran.len = MLXSW_I2C_ADDR_WIDTH + chunk_size;
262
337
 		mlxsw_i2c_set_slave_addr(tran_buf, off);
263
338
 		memcpy(&tran_buf[MLXSW_I2C_ADDR_BUF_SIZE], in_mbox +
264
-		       MLXSW_I2C_BLK_MAX * i, chunk_size);
339
+		       mlxsw_i2c->block_size * i, chunk_size);
265
340
 
266
341
 		j = 0;
267
342
 		end = jiffies + timeout;
..
..
@@ -275,9 +350,10 @@
275
350
 			 (j++ < MLXSW_I2C_RETRY));
276
351
 
277
352
 		if (err != 1) {
278
-			if (!err)
353
+			if (!err) {
279
354
 				err = -EIO;
280
-			return err;
355
+				goto mlxsw_i2c_write_exit;
356
+			}
281
357
 		}
282
358
 
283
359
 		off += chunk_size;
..
..
@@ -288,30 +364,33 @@
288
364
 	err = mlxsw_i2c_write_cmd(client, mlxsw_i2c, 0);
289
365
 	if (err) {
290
366
 		dev_err(&client->dev, "Could not start transaction");
291
-		return -EIO;
367
+		err = -EIO;
368
+		goto mlxsw_i2c_write_exit;
292
369
 	}
293
370
 
294
371
 	/* Wait until go bit is cleared. */
295
372
 	err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, p_status);
296
373
 	if (err) {
297
374
 		dev_err(&client->dev, "HW semaphore is not released");
298
-		return err;
375
+		goto mlxsw_i2c_write_exit;
299
376
 	}
300
377
 
301
378
 	/* Validate transaction completion status. */
302
379
 	if (*p_status) {
303
380
 		dev_err(&client->dev, "Bad transaction completion status %x\n",
304
381
 			*p_status);
305
-		return -EIO;
382
+		err = -EIO;
306
383
 	}
307
384
 
308
-	return 0;
385
+mlxsw_i2c_write_exit:
386
+	kfree(tran_buf);
387
+	return err;
309
388
 }
310
389
 
311
390
 /* Routine executes I2C command. */
312
391
 static int
313
-mlxsw_i2c_cmd(struct device *dev, size_t in_mbox_size, u8 *in_mbox,
314
-	      size_t out_mbox_size, u8 *out_mbox, u8 *status)
392
+mlxsw_i2c_cmd(struct device *dev, u16 opcode, u32 in_mod, size_t in_mbox_size,
393
+	      u8 *in_mbox, size_t out_mbox_size, u8 *out_mbox, u8 *status)
315
394
 {
316
395
 	struct i2c_client *client = to_i2c_client(dev);
317
396
 	struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client);
..
..
@@ -326,31 +405,47 @@
326
405
 
327
406
 	WARN_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32));
328
407
 
329
-	reg_size = mlxsw_i2c_get_reg_size(in_mbox);
330
-	num = reg_size / MLXSW_I2C_BLK_MAX;
331
-	if (reg_size % MLXSW_I2C_BLK_MAX)
332
-		num++;
408
+	if (in_mbox) {
409
+		reg_size = mlxsw_i2c_get_reg_size(in_mbox);
410
+		num = reg_size / mlxsw_i2c->block_size;
411
+		if (reg_size % mlxsw_i2c->block_size)
412
+			num++;
333
413
 
334
-	if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) {
335
-		dev_err(&client->dev, "Could not acquire lock");
336
-		return -EINVAL;
337
-	}
414
+		if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) {
415
+			dev_err(&client->dev, "Could not acquire lock");
416
+			return -EINVAL;
417
+		}
338
418
 
339
-	err = mlxsw_i2c_write(dev, reg_size, in_mbox, num, status);
340
-	if (err)
341
-		goto cmd_fail;
419
+		err = mlxsw_i2c_write(dev, reg_size, in_mbox, num, status);
420
+		if (err)
421
+			goto cmd_fail;
342
422
 
343
-	/* No out mailbox is case of write transaction. */
344
-	if (!out_mbox) {
345
-		mutex_unlock(&mlxsw_i2c->cmd.lock);
346
-		return 0;
423
+		/* No out mailbox is case of write transaction. */
424
+		if (!out_mbox) {
425
+			mutex_unlock(&mlxsw_i2c->cmd.lock);
426
+			return 0;
427
+		}
428
+	} else {
429
+		/* No input mailbox is case of initialization query command. */
430
+		reg_size = MLXSW_I2C_MAX_DATA_SIZE;
431
+		num = reg_size / mlxsw_i2c->block_size;
432
+
433
+		if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) {
434
+			dev_err(&client->dev, "Could not acquire lock");
435
+			return -EINVAL;
436
+		}
437
+
438
+		err = mlxsw_i2c_write_init_cmd(client, mlxsw_i2c, opcode,
439
+					       in_mod);
440
+		if (err)
441
+			goto cmd_fail;
347
442
 	}
348
443
 
349
444
 	/* Send read transaction to get output mailbox content. */
350
445
 	read_tran[1].buf = out_mbox;
351
446
 	for (i = 0; i < num; i++) {
352
-		chunk_size = (reg_size > MLXSW_I2C_BLK_MAX) ?
353
-			     MLXSW_I2C_BLK_MAX : reg_size;
447
+		chunk_size = (reg_size > mlxsw_i2c->block_size) ?
448
+			     mlxsw_i2c->block_size : reg_size;
354
449
 		read_tran[1].len = chunk_size;
355
450
 		mlxsw_i2c_set_slave_addr(tran_buf, off);
356
451
 
..
..
@@ -395,8 +490,8 @@
395
490
 {
396
491
 	struct mlxsw_i2c *mlxsw_i2c = bus_priv;
397
492
 
398
-	return mlxsw_i2c_cmd(mlxsw_i2c->dev, in_mbox_size, in_mbox,
399
-			     out_mbox_size, out_mbox, status);
493
+	return mlxsw_i2c_cmd(mlxsw_i2c->dev, opcode, in_mod, in_mbox_size,
494
+			     in_mbox, out_mbox_size, out_mbox, status);
400
495
 }
401
496
 
402
497
 static bool mlxsw_i2c_skb_transmit_busy(void *bus_priv,
..
..
@@ -414,13 +509,34 @@
414
509
 static int
415
510
 mlxsw_i2c_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
416
511
 	       const struct mlxsw_config_profile *profile,
417
-	       struct mlxsw_res *resources)
512
+	       struct mlxsw_res *res)
418
513
 {
419
514
 	struct mlxsw_i2c *mlxsw_i2c = bus_priv;
515
+	char *mbox;
516
+	int err;
420
517
 
421
518
 	mlxsw_i2c->core = mlxsw_core;
422
519
 
423
-	return 0;
520
+	mbox = mlxsw_cmd_mbox_alloc();
521
+	if (!mbox)
522
+		return -ENOMEM;
523
+
524
+	err = mlxsw_cmd_query_fw(mlxsw_core, mbox);
525
+	if (err)
526
+		goto mbox_put;
527
+
528
+	mlxsw_i2c->bus_info.fw_rev.major =
529
+		mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);
530
+	mlxsw_i2c->bus_info.fw_rev.minor =
531
+		mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);
532
+	mlxsw_i2c->bus_info.fw_rev.subminor =
533
+		mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);
534
+
535
+	err = mlxsw_core_resources_query(mlxsw_core, mbox, res);
536
+
537
+mbox_put:
538
+	mlxsw_cmd_mbox_free(mbox);
539
+	return err;
424
540
 }
425
541
 
426
542
 static void mlxsw_i2c_fini(void *bus_priv)
..
..
@@ -442,6 +558,7 @@
442
558
 static int mlxsw_i2c_probe(struct i2c_client *client,
443
559
 			   const struct i2c_device_id *id)
444
560
 {
561
+	const struct i2c_adapter_quirks *quirks = client->adapter->quirks;
445
562
 	struct mlxsw_i2c *mlxsw_i2c;
446
563
 	u8 status;
447
564
 	int err;
..
..
@@ -449,6 +566,22 @@
449
566
 	mlxsw_i2c = devm_kzalloc(&client->dev, sizeof(*mlxsw_i2c), GFP_KERNEL);
450
567
 	if (!mlxsw_i2c)
451
568
 		return -ENOMEM;
569
+
570
+	if (quirks) {
571
+		if ((quirks->max_read_len &&
572
+		     quirks->max_read_len < MLXSW_I2C_BLK_DEF) ||
573
+		    (quirks->max_write_len &&
574
+		     quirks->max_write_len < MLXSW_I2C_BLK_DEF)) {
575
+			dev_err(&client->dev, "Insufficient transaction buffer length\n");
576
+			return -EOPNOTSUPP;
577
+		}
578
+
579
+		mlxsw_i2c->block_size = max_t(u16, MLXSW_I2C_BLK_DEF,
580
+					      min_t(u16, quirks->max_read_len,
581
+						    quirks->max_write_len));
582
+	} else {
583
+		mlxsw_i2c->block_size = MLXSW_I2C_BLK_DEF;
584
+	}
452
585
 
453
586
 	i2c_set_clientdata(client, mlxsw_i2c);
454
587
 	mutex_init(&mlxsw_i2c->cmd.lock);
..
..
@@ -503,11 +636,12 @@
503
636
 	mlxsw_i2c->bus_info.device_kind = id->name;
504
637
 	mlxsw_i2c->bus_info.device_name = client->name;
505
638
 	mlxsw_i2c->bus_info.dev = &client->dev;
639
+	mlxsw_i2c->bus_info.low_frequency = true;
506
640
 	mlxsw_i2c->dev = &client->dev;
507
641
 
508
642
 	err = mlxsw_core_bus_device_register(&mlxsw_i2c->bus_info,
509
643
 					     &mlxsw_i2c_bus, mlxsw_i2c, false,
510
-					     NULL);
644
+					     NULL, NULL);
511
645
 	if (err) {
512
646
 		dev_err(&client->dev, "Fail to register core bus\n");
513
647
 		return err;
..
..
@@ -516,6 +650,7 @@
516
650
 	return 0;
517
651
 
518
652
 errout:
653
+	mutex_destroy(&mlxsw_i2c->cmd.lock);
519
654
 	i2c_set_clientdata(client, NULL);
520
655
 
521
656
 	return err;