forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c
....@@ -1,10 +1,8 @@
1
-/*
2
- * aQuantia Corporation Network Driver
3
- * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
1
+// SPDX-License-Identifier: GPL-2.0-only
2
+/* Atlantic Network Driver
43  *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms and conditions of the GNU General Public License,
7
- * version 2, as published by the Free Software Foundation.
4
+ * Copyright (C) 2014-2019 aQuantia Corporation
5
+ * Copyright (C) 2019-2020 Marvell International Ltd.
86  */
97 
108 /* File hw_atl_a0.c: Definition of Atlantic hardware specific functions. */
....@@ -18,73 +16,77 @@
1816 #include "hw_atl_llh.h"
1917 #include "hw_atl_a0_internal.h"
2018 
21
-#define DEFAULT_A0_BOARD_BASIC_CAPABILITIES \
22
-	.is_64_dma = true,		  \
23
-	.msix_irqs = 4U,		  \
24
-	.irq_mask = ~0U,		  \
25
-	.vecs = HW_ATL_A0_RSS_MAX,	  \
26
-	.tcs = HW_ATL_A0_TC_MAX,	  \
27
-	.rxd_alignment = 1U,		  \
28
-	.rxd_size = HW_ATL_A0_RXD_SIZE,   \
29
-	.rxds_max = HW_ATL_A0_MAX_RXD,    \
30
-	.rxds_min = HW_ATL_A0_MIN_RXD,    \
31
-	.txd_alignment = 1U,		  \
32
-	.txd_size = HW_ATL_A0_TXD_SIZE,   \
33
-	.txds_max = HW_ATL_A0_MAX_TXD,    \
34
-	.txds_min = HW_ATL_A0_MIN_RXD,    \
35
-	.txhwb_alignment = 4096U,	  \
36
-	.tx_rings = HW_ATL_A0_TX_RINGS,   \
37
-	.rx_rings = HW_ATL_A0_RX_RINGS,   \
38
-	.hw_features = NETIF_F_HW_CSUM |  \
39
-			NETIF_F_RXHASH |  \
40
-			NETIF_F_RXCSUM |  \
41
-			NETIF_F_SG |	  \
42
-			NETIF_F_TSO,	  \
43
-	.hw_priv_flags = IFF_UNICAST_FLT, \
44
-	.flow_control = true,		  \
45
-	.mtu = HW_ATL_A0_MTU_JUMBO,       \
46
-	.mac_regs_count = 88,		  \
19
+#define DEFAULT_A0_BOARD_BASIC_CAPABILITIES	     \
20
+	.is_64_dma = true,			     \
21
+	.op64bit = false,			     \
22
+	.msix_irqs = 4U,			     \
23
+	.irq_mask = ~0U,			     \
24
+	.vecs = HW_ATL_A0_RSS_MAX,		     \
25
+	.tcs_max = HW_ATL_A0_TC_MAX,		     \
26
+	.rxd_alignment = 1U,			     \
27
+	.rxd_size = HW_ATL_A0_RXD_SIZE,		     \
28
+	.rxds_max = HW_ATL_A0_MAX_RXD,		     \
29
+	.rxds_min = HW_ATL_A0_MIN_RXD,		     \
30
+	.txd_alignment = 1U,			     \
31
+	.txd_size = HW_ATL_A0_TXD_SIZE,		     \
32
+	.txds_max = HW_ATL_A0_MAX_TXD,		     \
33
+	.txds_min = HW_ATL_A0_MIN_RXD,		     \
34
+	.txhwb_alignment = 4096U,		     \
35
+	.tx_rings = HW_ATL_A0_TX_RINGS,		     \
36
+	.rx_rings = HW_ATL_A0_RX_RINGS,		     \
37
+	.hw_features = NETIF_F_HW_CSUM |	     \
38
+			NETIF_F_RXHASH |	     \
39
+			NETIF_F_RXCSUM |	     \
40
+			NETIF_F_SG |		     \
41
+			NETIF_F_TSO |		     \
42
+			NETIF_F_NTUPLE |	     \
43
+			NETIF_F_HW_VLAN_CTAG_FILTER, \
44
+	.hw_priv_flags = IFF_UNICAST_FLT,	     \
45
+	.flow_control = true,			     \
46
+	.mtu = HW_ATL_A0_MTU_JUMBO,		     \
47
+	.mac_regs_count = 88,			     \
4748 	.hw_alive_check_addr = 0x10U
4849 
4950 const struct aq_hw_caps_s hw_atl_a0_caps_aqc100 = {
5051 	DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
5152 	.media_type = AQ_HW_MEDIA_TYPE_FIBRE,
52
-	.link_speed_msk = HW_ATL_A0_RATE_5G  |
53
-			  HW_ATL_A0_RATE_2G5 |
54
-			  HW_ATL_A0_RATE_1G  |
55
-			  HW_ATL_A0_RATE_100M,
53
+	.link_speed_msk = AQ_NIC_RATE_5G |
54
+			  AQ_NIC_RATE_2G5 |
55
+			  AQ_NIC_RATE_1G |
56
+			  AQ_NIC_RATE_100M,
5657 };
5758 
5859 const struct aq_hw_caps_s hw_atl_a0_caps_aqc107 = {
5960 	DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
6061 	.media_type = AQ_HW_MEDIA_TYPE_TP,
61
-	.link_speed_msk = HW_ATL_A0_RATE_10G |
62
-			  HW_ATL_A0_RATE_5G  |
63
-			  HW_ATL_A0_RATE_2G5 |
64
-			  HW_ATL_A0_RATE_1G  |
65
-			  HW_ATL_A0_RATE_100M,
62
+	.link_speed_msk = AQ_NIC_RATE_10G |
63
+			  AQ_NIC_RATE_5G |
64
+			  AQ_NIC_RATE_2G5 |
65
+			  AQ_NIC_RATE_1G |
66
+			  AQ_NIC_RATE_100M,
6667 };
6768 
6869 const struct aq_hw_caps_s hw_atl_a0_caps_aqc108 = {
6970 	DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
7071 	.media_type = AQ_HW_MEDIA_TYPE_TP,
71
-	.link_speed_msk = HW_ATL_A0_RATE_5G  |
72
-			  HW_ATL_A0_RATE_2G5 |
73
-			  HW_ATL_A0_RATE_1G  |
74
-			  HW_ATL_A0_RATE_100M,
72
+	.link_speed_msk = AQ_NIC_RATE_5G |
73
+			  AQ_NIC_RATE_2G5 |
74
+			  AQ_NIC_RATE_1G |
75
+			  AQ_NIC_RATE_100M,
7576 };
7677 
7778 const struct aq_hw_caps_s hw_atl_a0_caps_aqc109 = {
7879 	DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
7980 	.media_type = AQ_HW_MEDIA_TYPE_TP,
80
-	.link_speed_msk = HW_ATL_A0_RATE_2G5 |
81
-			  HW_ATL_A0_RATE_1G  |
82
-			  HW_ATL_A0_RATE_100M,
81
+	.link_speed_msk = AQ_NIC_RATE_2G5 |
82
+			  AQ_NIC_RATE_1G |
83
+			  AQ_NIC_RATE_100M,
8384 };
8485 
8586 static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
8687 {
8788 	int err = 0;
89
+	u32 val;
8890 
8991 	hw_atl_glb_glb_reg_res_dis_set(self, 1U);
9092 	hw_atl_pci_pci_reg_res_dis_set(self, 0U);
....@@ -95,7 +97,9 @@
9597 	hw_atl_glb_soft_res_set(self, 1);
9698 
9799 	/* check 10 times by 1ms */
98
-	AQ_HW_WAIT_FOR(hw_atl_glb_soft_res_get(self) == 0, 1000U, 10U);
100
+	err = readx_poll_timeout_atomic(hw_atl_glb_soft_res_get,
101
+					self, val, val == 0,
102
+					1000U, 10000U);
99103 	if (err < 0)
100104 		goto err_exit;
101105 
....@@ -103,7 +107,9 @@
103107 	hw_atl_itr_res_irq_set(self, 1U);
104108 
105109 	/* check 10 times by 1ms */
106
-	AQ_HW_WAIT_FOR(hw_atl_itr_res_irq_get(self) == 0, 1000U, 10U);
110
+	err = readx_poll_timeout_atomic(hw_atl_itr_res_irq_get,
111
+					self, val, val == 0,
112
+					1000U, 10000U);
107113 	if (err < 0)
108114 		goto err_exit;
109115 
....@@ -117,10 +123,10 @@
117123 
118124 static int hw_atl_a0_hw_qos_set(struct aq_hw_s *self)
119125 {
120
-	u32 tc = 0U;
121
-	u32 buff_size = 0U;
122
-	unsigned int i_priority = 0U;
123126 	bool is_rx_flow_control = false;
127
+	unsigned int i_priority = 0U;
128
+	u32 buff_size = 0U;
129
+	u32 tc = 0U;
124130 
125131 	/* TPS Descriptor rate init */
126132 	hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
....@@ -133,10 +139,10 @@
133139 	hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
134140 	hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
135141 
136
-	hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
137
-	hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
138
-	hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
139
-	hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
142
+	hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0U, 0xFFF);
143
+	hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0U, 0x64);
144
+	hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0U, 0x50);
145
+	hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0U, 0x1E);
140146 
141147 	/* Tx buf size */
142148 	buff_size = HW_ATL_A0_TXBUF_MAX;
....@@ -153,7 +159,7 @@
153159 
154160 	/* QoS Rx buf size per TC */
155161 	tc = 0;
156
-	is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
162
+	is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->fc.req);
157163 	buff_size = HW_ATL_A0_RXBUF_MAX;
158164 
159165 	hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
....@@ -178,9 +184,10 @@
178184 				     struct aq_rss_parameters *rss_params)
179185 {
180186 	struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
181
-	int err = 0;
182
-	unsigned int i = 0U;
183187 	unsigned int addr = 0U;
188
+	unsigned int i = 0U;
189
+	int err = 0;
190
+	u32 val;
184191 
185192 	for (i = 10, addr = 0U; i--; ++addr) {
186193 		u32 key_data = cfg->is_rss ?
....@@ -188,8 +195,9 @@
188195 		hw_atl_rpf_rss_key_wr_data_set(self, key_data);
189196 		hw_atl_rpf_rss_key_addr_set(self, addr);
190197 		hw_atl_rpf_rss_key_wr_en_set(self, 1U);
191
-		AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,
192
-			       1000U, 10U);
198
+		err = readx_poll_timeout_atomic(hw_atl_rpf_rss_key_wr_en_get,
199
+						self, val, val == 0,
200
+						1000U, 10000U);
193201 		if (err < 0)
194202 			goto err_exit;
195203 	}
....@@ -203,12 +211,13 @@
203211 static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self,
204212 				struct aq_rss_parameters *rss_params)
205213 {
206
-	u8 *indirection_table =	rss_params->indirection_table;
207
-	u32 i = 0U;
208214 	u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
209
-	int err = 0;
215
+	u8 *indirection_table =	rss_params->indirection_table;
210216 	u16 bitary[1 + (HW_ATL_A0_RSS_REDIRECTION_MAX *
211217 		   HW_ATL_A0_RSS_REDIRECTION_BITS / 16U)];
218
+	int err = 0;
219
+	u32 i = 0U;
220
+	u32 val;
212221 
213222 	memset(bitary, 0, sizeof(bitary));
214223 
....@@ -222,8 +231,9 @@
222231 		hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
223232 		hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
224233 		hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
225
-		AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,
226
-			       1000U, 10U);
234
+		err = readx_poll_timeout_atomic(hw_atl_rpf_rss_redir_wr_en_get,
235
+						self, val, val == 0,
236
+						1000U, 10000U);
227237 		if (err < 0)
228238 			goto err_exit;
229239 	}
....@@ -261,8 +271,7 @@
261271 	hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
262272 
263273 	/* misc */
264
-	aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
265
-			0x00010000U : 0x00000000U);
274
+	aq_hw_write_reg(self, 0x00007040U, 0x00000000U);
266275 	hw_atl_tdm_tx_dca_en_set(self, 0U);
267276 	hw_atl_tdm_tx_dca_mode_set(self, 0U);
268277 
....@@ -284,7 +293,7 @@
284293 
285294 	/* RSS Ring selection */
286295 	hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?
287
-					0xB3333333U : 0x00000000U);
296
+					  0xB3333333U : 0x00000000U);
288297 
289298 	/* Multicast filters */
290299 	for (i = HW_ATL_A0_MAC_MAX; i--;) {
....@@ -315,17 +324,18 @@
315324 
316325 static int hw_atl_a0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
317326 {
318
-	int err = 0;
319327 	unsigned int h = 0U;
320328 	unsigned int l = 0U;
329
+	int err = 0;
321330 
322331 	if (!mac_addr) {
323332 		err = -EINVAL;
324333 		goto err_exit;
325334 	}
335
+
326336 	h = (mac_addr[0] << 8) | (mac_addr[1]);
327337 	l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
328
-		(mac_addr[4] << 8) | mac_addr[5];
338
+	    (mac_addr[4] << 8) | mac_addr[5];
329339 
330340 	hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC);
331341 	hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_A0_MAC);
....@@ -341,15 +351,13 @@
341351 static int hw_atl_a0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
342352 {
343353 	static u32 aq_hw_atl_igcr_table_[4][2] = {
344
-		{ 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
345
-		{ 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */
346
-		{ 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */
347
-		{ 0x20000022U, 0x20000026U }  /* AQ_IRQ_MSIX */
354
+		[AQ_HW_IRQ_INVALID] = { 0x20000000U, 0x20000000U },
355
+		[AQ_HW_IRQ_LEGACY]  = { 0x20000080U, 0x20000080U },
356
+		[AQ_HW_IRQ_MSI]     = { 0x20000021U, 0x20000025U },
357
+		[AQ_HW_IRQ_MSIX]    = { 0x20000022U, 0x20000026U },
348358 	};
349
-
350
-	int err = 0;
351
-
352359 	struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg;
360
+	int err = 0;
353361 
354362 	hw_atl_a0_hw_init_tx_path(self);
355363 	hw_atl_a0_hw_init_rx_path(self);
....@@ -398,6 +406,7 @@
398406 				      struct aq_ring_s *ring)
399407 {
400408 	hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx);
409
+
401410 	return aq_hw_err_from_flags(self);
402411 }
403412 
....@@ -405,6 +414,7 @@
405414 				      struct aq_ring_s *ring)
406415 {
407416 	hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx);
417
+
408418 	return aq_hw_err_from_flags(self);
409419 }
410420 
....@@ -412,6 +422,7 @@
412422 {
413423 	hw_atl_tpb_tx_buff_en_set(self, 1);
414424 	hw_atl_rpb_rx_buff_en_set(self, 1);
425
+
415426 	return aq_hw_err_from_flags(self);
416427 }
417428 
....@@ -419,6 +430,7 @@
419430 					    struct aq_ring_s *ring)
420431 {
421432 	hw_atl_reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
433
+
422434 	return 0;
423435 }
424436 
....@@ -429,8 +441,8 @@
429441 	struct aq_ring_buff_s *buff = NULL;
430442 	struct hw_atl_txd_s *txd = NULL;
431443 	unsigned int buff_pa_len = 0U;
432
-	unsigned int pkt_len = 0U;
433444 	unsigned int frag_count = 0U;
445
+	unsigned int pkt_len = 0U;
434446 	bool is_gso = false;
435447 
436448 	buff = &ring->buff_ring[ring->sw_tail];
....@@ -445,7 +457,7 @@
445457 
446458 		buff = &ring->buff_ring[ring->sw_tail];
447459 
448
-		if (buff->is_txc) {
460
+		if (buff->is_gso_tcp) {
449461 			txd->ctl |= (buff->len_l3 << 31) |
450462 				(buff->len_l2 << 24) |
451463 				HW_ATL_A0_TXD_CTL_CMD_TCP |
....@@ -494,6 +506,7 @@
494506 	}
495507 
496508 	hw_atl_a0_hw_tx_ring_tail_update(self, ring);
509
+
497510 	return aq_hw_err_from_flags(self);
498511 }
499512 
....@@ -501,8 +514,8 @@
501514 				     struct aq_ring_s *aq_ring,
502515 				     struct aq_ring_param_s *aq_ring_param)
503516 {
504
-	u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
505517 	u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
518
+	u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
506519 
507520 	hw_atl_rdm_rx_desc_en_set(self, false, aq_ring->idx);
508521 
....@@ -519,7 +532,7 @@
519532 
520533 	hw_atl_rdm_rx_desc_data_buff_size_set(self,
521534 					      AQ_CFG_RX_FRAME_MAX / 1024U,
522
-				       aq_ring->idx);
535
+					      aq_ring->idx);
523536 
524537 	hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
525538 	hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
....@@ -543,8 +556,8 @@
543556 				     struct aq_ring_s *aq_ring,
544557 				     struct aq_ring_param_s *aq_ring_param)
545558 {
546
-	u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
547559 	u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
560
+	u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
548561 
549562 	hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
550563 						  aq_ring->idx);
....@@ -593,8 +606,8 @@
593606 static int hw_atl_a0_hw_ring_tx_head_update(struct aq_hw_s *self,
594607 					    struct aq_ring_s *ring)
595608 {
596
-	int err = 0;
597609 	unsigned int hw_head = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx);
610
+	int err = 0;
598611 
599612 	if (aq_utils_obj_test(&self->flags, AQ_HW_FLAG_ERR_UNPLUG)) {
600613 		err = -ENXIO;
....@@ -610,8 +623,6 @@
610623 static int hw_atl_a0_hw_ring_rx_receive(struct aq_hw_s *self,
611624 					struct aq_ring_s *ring)
612625 {
613
-	struct device *ndev = aq_nic_get_dev(ring->aq_nic);
614
-
615626 	for (; ring->hw_head != ring->sw_tail;
616627 		ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
617628 		struct aq_ring_buff_s *buff = NULL;
....@@ -678,8 +689,6 @@
678689 		is_err &= ~0x18U;
679690 		is_err &= ~0x04U;
680691 
681
-		dma_unmap_page(ndev, buff->pa, buff->len, DMA_FROM_DEVICE);
682
-
683692 		if (is_err || rxd_wb->type & 0x1000U) {
684693 			/* status error or DMA error */
685694 			buff->is_error = 1U;
....@@ -718,6 +727,7 @@
718727 {
719728 	hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask) |
720729 			       (1U << HW_ATL_A0_ERR_INT));
730
+
721731 	return aq_hw_err_from_flags(self);
722732 }
723733 
....@@ -735,6 +745,7 @@
735745 static int hw_atl_a0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
736746 {
737747 	*mask = hw_atl_itr_irq_statuslsw_get(self);
748
+
738749 	return aq_hw_err_from_flags(self);
739750 }
740751 
....@@ -743,6 +754,7 @@
743754 static int hw_atl_a0_hw_packet_filter_set(struct aq_hw_s *self,
744755 					  unsigned int packet_filter)
745756 {
757
+	struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
746758 	unsigned int i = 0U;
747759 
748760 	hw_atl_rpfl2promiscuous_mode_en_set(self,
....@@ -751,14 +763,13 @@
751763 					 IS_FILTER_ENABLED(IFF_MULTICAST), 0);
752764 	hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
753765 
754
-	self->aq_nic_cfg->is_mc_list_enabled =
755
-			IS_FILTER_ENABLED(IFF_MULTICAST);
766
+	cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST);
756767 
757768 	for (i = HW_ATL_A0_MAC_MIN; i < HW_ATL_A0_MAC_MAX; ++i)
758769 		hw_atl_rpfl2_uc_flr_en_set(self,
759
-					   (self->aq_nic_cfg->is_mc_list_enabled &&
760
-					   (i <= self->aq_nic_cfg->mc_list_count)) ?
761
-					    1U : 0U, i);
770
+					   (cfg->is_mc_list_enabled &&
771
+					    (i <= cfg->mc_list_count)) ? 1U : 0U,
772
+					   i);
762773 
763774 	return aq_hw_err_from_flags(self);
764775 }
....@@ -771,19 +782,18 @@
771782 					   [ETH_ALEN],
772783 					   u32 count)
773784 {
785
+	struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
774786 	int err = 0;
775787 
776788 	if (count > (HW_ATL_A0_MAC_MAX - HW_ATL_A0_MAC_MIN)) {
777789 		err = -EBADRQC;
778790 		goto err_exit;
779791 	}
780
-	for (self->aq_nic_cfg->mc_list_count = 0U;
781
-			self->aq_nic_cfg->mc_list_count < count;
782
-			++self->aq_nic_cfg->mc_list_count) {
783
-		u32 i = self->aq_nic_cfg->mc_list_count;
792
+	for (cfg->mc_list_count = 0U; cfg->mc_list_count < count; ++cfg->mc_list_count) {
793
+		u32 i = cfg->mc_list_count;
784794 		u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
785795 		u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
786
-					(ar_mac[i][4] << 8) | ar_mac[i][5];
796
+			(ar_mac[i][4] << 8) | ar_mac[i][5];
787797 
788798 		hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC_MIN + i);
789799 
....@@ -796,7 +806,7 @@
796806 							HW_ATL_A0_MAC_MIN + i);
797807 
798808 		hw_atl_rpfl2_uc_flr_en_set(self,
799
-					   (self->aq_nic_cfg->is_mc_list_enabled),
809
+					   (cfg->is_mc_list_enabled),
800810 					   HW_ATL_A0_MAC_MIN + i);
801811 	}
802812 
....@@ -857,6 +867,7 @@
857867 static int hw_atl_a0_hw_stop(struct aq_hw_s *self)
858868 {
859869 	hw_atl_a0_hw_irq_disable(self, HW_ATL_A0_INT_MASK);
870
+
860871 	return aq_hw_err_from_flags(self);
861872 }
862873 
....@@ -864,6 +875,7 @@
864875 				     struct aq_ring_s *ring)
865876 {
866877 	hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx);
878
+
867879 	return aq_hw_err_from_flags(self);
868880 }
869881 
....@@ -871,13 +883,72 @@
871883 				     struct aq_ring_s *ring)
872884 {
873885 	hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx);
886
+
887
+	return aq_hw_err_from_flags(self);
888
+}
889
+
890
+static int hw_atl_a0_hw_fl3l4_clear(struct aq_hw_s *self,
891
+				    struct aq_rx_filter_l3l4 *data)
892
+{
893
+	u8 location = data->location;
894
+
895
+	if (!data->is_ipv6) {
896
+		hw_atl_rpfl3l4_cmd_clear(self, location);
897
+		hw_atl_rpf_l4_spd_set(self, 0U, location);
898
+		hw_atl_rpf_l4_dpd_set(self, 0U, location);
899
+		hw_atl_rpfl3l4_ipv4_src_addr_clear(self, location);
900
+		hw_atl_rpfl3l4_ipv4_dest_addr_clear(self, location);
901
+	} else {
902
+		int i;
903
+
904
+		for (i = 0; i < HW_ATL_RX_CNT_REG_ADDR_IPV6; ++i) {
905
+			hw_atl_rpfl3l4_cmd_clear(self, location + i);
906
+			hw_atl_rpf_l4_spd_set(self, 0U, location + i);
907
+			hw_atl_rpf_l4_dpd_set(self, 0U, location + i);
908
+		}
909
+		hw_atl_rpfl3l4_ipv6_src_addr_clear(self, location);
910
+		hw_atl_rpfl3l4_ipv6_dest_addr_clear(self, location);
911
+	}
912
+
913
+	return aq_hw_err_from_flags(self);
914
+}
915
+
916
+static int hw_atl_a0_hw_fl3l4_set(struct aq_hw_s *self,
917
+				  struct aq_rx_filter_l3l4 *data)
918
+{
919
+	u8 location = data->location;
920
+
921
+	hw_atl_a0_hw_fl3l4_clear(self, data);
922
+
923
+	if (data->cmd) {
924
+		if (!data->is_ipv6) {
925
+			hw_atl_rpfl3l4_ipv4_dest_addr_set(self,
926
+							  location,
927
+							  data->ip_dst[0]);
928
+			hw_atl_rpfl3l4_ipv4_src_addr_set(self,
929
+							 location,
930
+							 data->ip_src[0]);
931
+		} else {
932
+			hw_atl_rpfl3l4_ipv6_dest_addr_set(self,
933
+							  location,
934
+							  data->ip_dst);
935
+			hw_atl_rpfl3l4_ipv6_src_addr_set(self,
936
+							 location,
937
+							 data->ip_src);
938
+		}
939
+	}
940
+	hw_atl_rpf_l4_dpd_set(self, data->p_dst, location);
941
+	hw_atl_rpf_l4_spd_set(self, data->p_src, location);
942
+	hw_atl_rpfl3l4_cmd_set(self, location, data->cmd);
943
+
874944 	return aq_hw_err_from_flags(self);
875945 }
876946 
877947 const struct aq_hw_ops hw_atl_ops_a0 = {
948
+	.hw_soft_reset        = hw_atl_utils_soft_reset,
949
+	.hw_prepare           = hw_atl_utils_initfw,
878950 	.hw_set_mac_address   = hw_atl_a0_hw_mac_addr_set,
879951 	.hw_init              = hw_atl_a0_hw_init,
880
-	.hw_set_power         = hw_atl_utils_hw_set_power,
881952 	.hw_reset             = hw_atl_a0_hw_reset,
882953 	.hw_start             = hw_atl_a0_hw_start,
883954 	.hw_ring_tx_start     = hw_atl_a0_hw_ring_tx_start,
....@@ -899,6 +970,7 @@
899970 	.hw_ring_rx_init             = hw_atl_a0_hw_ring_rx_init,
900971 	.hw_ring_tx_init             = hw_atl_a0_hw_ring_tx_init,
901972 	.hw_packet_filter_set        = hw_atl_a0_hw_packet_filter_set,
973
+	.hw_filter_l3l4_set          = hw_atl_a0_hw_fl3l4_set,
902974 	.hw_multicast_list_set       = hw_atl_a0_hw_multicast_list_set,
903975 	.hw_interrupt_moderation_set = hw_atl_a0_hw_interrupt_moderation_set,
904976 	.hw_rss_set                  = hw_atl_a0_hw_rss_set,