~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,3 +1,4 @@
	1	+// SPDX-License-Identifier: GPL-2.0-or-later
1	2	/*
2	3	* Marvell 88e6xxx Ethernet switch single-chip support
3	4	*
..	..	@@ -7,13 +8,9 @@
7	8	*
8	9	* Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9	10	* Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10		- *
11		- * This program is free software; you can redistribute it and/or modify
12		- * it under the terms of the GNU General Public License as published by
13		- * the Free Software Foundation; either version 2 of the License, or
14		- * (at your option) any later version.
15	11	*/
16	12
	13	+#include <linux/bitfield.h>
17	14	#include <linux/delay.h>
18	15	#include <linux/etherdevice.h>
19	16	#include <linux/ethtool.h>
..	..	@@ -31,11 +28,11 @@
31	28	#include <linux/platform_data/mv88e6xxx.h>
32	29	#include <linux/netdevice.h>
33	30	#include <linux/gpio/consumer.h>
34		-#include <linux/phy.h>
35	31	#include <linux/phylink.h>
36	32	#include <net/dsa.h>
37	33
38	34	#include "chip.h"
	35	+#include "devlink.h"
39	36	#include "global1.h"
40	37	#include "global2.h"
41	38	#include "hwtstamp.h"
..	..	@@ -43,6 +40,7 @@
43	40	#include "port.h"
44	41	#include "ptp.h"
45	42	#include "serdes.h"
	43	+#include "smi.h"
46	44
47	45	static void assert_reg_lock(struct mv88e6xxx_chip *chip)
48	46	{
..	..	@@ -51,149 +49,6 @@
51	49	dump_stack();
52	50	}
53	51	}
54		-
55		-/* The switch ADDR[4:1] configuration pins define the chip SMI device address
56		- * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
57		- *
58		- * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
59		- * is the only device connected to the SMI master. In this mode it responds to
60		- * all 32 possible SMI addresses, and thus maps directly the internal devices.
61		- *
62		- * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
63		- * multiple devices to share the SMI interface. In this mode it responds to only
64		- * 2 registers, used to indirectly access the internal SMI devices.
65		- */
66		-
67		-static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
68		- int addr, int reg, u16 *val)
69		-{
70		- if (!chip->smi_ops)
71		- return -EOPNOTSUPP;
72		-
73		- return chip->smi_ops->read(chip, addr, reg, val);
74		-}
75		-
76		-static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
77		- int addr, int reg, u16 val)
78		-{
79		- if (!chip->smi_ops)
80		- return -EOPNOTSUPP;
81		-
82		- return chip->smi_ops->write(chip, addr, reg, val);
83		-}
84		-
85		-static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
86		- int addr, int reg, u16 *val)
87		-{
88		- int ret;
89		-
90		- ret = mdiobus_read_nested(chip->bus, addr, reg);
91		- if (ret < 0)
92		- return ret;
93		-
94		- *val = ret & 0xffff;
95		-
96		- return 0;
97		-}
98		-
99		-static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
100		- int addr, int reg, u16 val)
101		-{
102		- int ret;
103		-
104		- ret = mdiobus_write_nested(chip->bus, addr, reg, val);
105		- if (ret < 0)
106		- return ret;
107		-
108		- return 0;
109		-}
110		-
111		-static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
112		- .read = mv88e6xxx_smi_single_chip_read,
113		- .write = mv88e6xxx_smi_single_chip_write,
114		-};
115		-
116		-static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
117		-{
118		- int ret;
119		- int i;
120		-
121		- for (i = 0; i < 16; i++) {
122		- ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
123		- if (ret < 0)
124		- return ret;
125		-
126		- if ((ret & SMI_CMD_BUSY) == 0)
127		- return 0;
128		- }
129		-
130		- return -ETIMEDOUT;
131		-}
132		-
133		-static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
134		- int addr, int reg, u16 *val)
135		-{
136		- int ret;
137		-
138		- /* Wait for the bus to become free. */
139		- ret = mv88e6xxx_smi_multi_chip_wait(chip);
140		- if (ret < 0)
141		- return ret;
142		-
143		- /* Transmit the read command. */
144		- ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
145		- SMI_CMD_OP_22_READ \| (addr << 5) \| reg);
146		- if (ret < 0)
147		- return ret;
148		-
149		- /* Wait for the read command to complete. */
150		- ret = mv88e6xxx_smi_multi_chip_wait(chip);
151		- if (ret < 0)
152		- return ret;
153		-
154		- /* Read the data. */
155		- ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
156		- if (ret < 0)
157		- return ret;
158		-
159		- *val = ret & 0xffff;
160		-
161		- return 0;
162		-}
163		-
164		-static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
165		- int addr, int reg, u16 val)
166		-{
167		- int ret;
168		-
169		- /* Wait for the bus to become free. */
170		- ret = mv88e6xxx_smi_multi_chip_wait(chip);
171		- if (ret < 0)
172		- return ret;
173		-
174		- /* Transmit the data to write. */
175		- ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
176		- if (ret < 0)
177		- return ret;
178		-
179		- /* Transmit the write command. */
180		- ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
181		- SMI_CMD_OP_22_WRITE \| (addr << 5) \| reg);
182		- if (ret < 0)
183		- return ret;
184		-
185		- /* Wait for the write command to complete. */
186		- ret = mv88e6xxx_smi_multi_chip_wait(chip);
187		- if (ret < 0)
188		- return ret;
189		-
190		- return 0;
191		-}
192		-
193		-static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
194		- .read = mv88e6xxx_smi_multi_chip_read,
195		- .write = mv88e6xxx_smi_multi_chip_write,
196		-};
197	52
198	53	int mv88e6xxx_read(struct mv88e6xxx_chip chip, int addr, int reg, u16 val)
199	54	{
..	..	@@ -225,6 +80,36 @@
225	80	addr, reg, val);
226	81
227	82	return 0;
	83	+}
	84	+
	85	+int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
	86	+ u16 mask, u16 val)
	87	+{
	88	+ u16 data;
	89	+ int err;
	90	+ int i;
	91	+
	92	+ /* There's no bus specific operation to wait for a mask */
	93	+ for (i = 0; i < 16; i++) {
	94	+ err = mv88e6xxx_read(chip, addr, reg, &data);
	95	+ if (err)
	96	+ return err;
	97	+
	98	+ if ((data & mask) == val)
	99	+ return 0;
	100	+
	101	+ usleep_range(1000, 2000);
	102	+ }
	103	+
	104	+ dev_err(chip->dev, "Timeout while waiting for switch\n");
	105	+ return -ETIMEDOUT;
	106	+}
	107	+
	108	+int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
	109	+ int bit, int val)
	110	+{
	111	+ return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
	112	+ val ? BIT(bit) : 0x0000);
228	113	}
229	114
230	115	struct mii_bus mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip chip)
..	..	@@ -264,9 +149,9 @@
264	149	u16 ctl1;
265	150	int err;
266	151
267		- mutex_lock(&chip->reg_lock);
	152	+ mv88e6xxx_reg_lock(chip);
268	153	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
269		- mutex_unlock(&chip->reg_lock);
	154	+ mv88e6xxx_reg_unlock(chip);
270	155
271	156	if (err)
272	157	goto out;
..	..	@@ -281,13 +166,13 @@
281	166	}
282	167	}
283	168
284		- mutex_lock(&chip->reg_lock);
	169	+ mv88e6xxx_reg_lock(chip);
285	170	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
286	171	if (err)
287	172	goto unlock;
288	173	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
289	174	unlock:
290		- mutex_unlock(&chip->reg_lock);
	175	+ mv88e6xxx_reg_unlock(chip);
291	176	if (err)
292	177	goto out;
293	178	ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
..	..	@@ -308,7 +193,7 @@
308	193	{
309	194	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
310	195
311		- mutex_lock(&chip->reg_lock);
	196	+ mv88e6xxx_reg_lock(chip);
312	197	}
313	198
314	199	static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
..	..	@@ -330,7 +215,7 @@
330	215	goto out;
331	216
332	217	out:
333		- mutex_unlock(&chip->reg_lock);
	218	+ mv88e6xxx_reg_unlock(chip);
334	219	}
335	220
336	221	static const struct irq_chip mv88e6xxx_g1_irq_chip = {
..	..	@@ -385,9 +270,9 @@
385	270	*/
386	271	free_irq(chip->irq, chip);
387	272
388		- mutex_lock(&chip->reg_lock);
	273	+ mv88e6xxx_reg_lock(chip);
389	274	mv88e6xxx_g1_irq_free_common(chip);
390		- mutex_unlock(&chip->reg_lock);
	275	+ mv88e6xxx_reg_unlock(chip);
391	276	}
392	277
393	278	static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
..	..	@@ -456,12 +341,15 @@
456	341	*/
457	342	irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
458	343
459		- mutex_unlock(&chip->reg_lock);
	344	+ snprintf(chip->irq_name, sizeof(chip->irq_name),
	345	+ "mv88e6xxx-%s", dev_name(chip->dev));
	346	+
	347	+ mv88e6xxx_reg_unlock(chip);
460	348	err = request_threaded_irq(chip->irq, NULL,
461	349	mv88e6xxx_g1_irq_thread_fn,
462		- IRQF_ONESHOT,
463		- dev_name(chip->dev), chip);
464		- mutex_lock(&chip->reg_lock);
	350	+ IRQF_ONESHOT \| IRQF_SHARED,
	351	+ chip->irq_name, chip);
	352	+ mv88e6xxx_reg_lock(chip);
465	353	if (err)
466	354	mv88e6xxx_g1_irq_free_common(chip);
467	355
..	..	@@ -490,7 +378,7 @@
490	378	kthread_init_delayed_work(&chip->irq_poll_work,
491	379	mv88e6xxx_irq_poll);
492	380
493		- chip->kworker = kthread_create_worker(0, dev_name(chip->dev));
	381	+ chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
494	382	if (IS_ERR(chip->kworker))
495	383	return PTR_ERR(chip->kworker);
496	384
..	..	@@ -505,48 +393,31 @@
505	393	kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
506	394	kthread_destroy_worker(chip->kworker);
507	395
508		- mutex_lock(&chip->reg_lock);
	396	+ mv88e6xxx_reg_lock(chip);
509	397	mv88e6xxx_g1_irq_free_common(chip);
510		- mutex_unlock(&chip->reg_lock);
	398	+ mv88e6xxx_reg_unlock(chip);
511	399	}
512	400
513		-int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
	401	+static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
	402	+ int port, phy_interface_t interface)
514	403	{
515		- int i;
516		-
517		- for (i = 0; i < 16; i++) {
518		- u16 val;
519		- int err;
520		-
521		- err = mv88e6xxx_read(chip, addr, reg, &val);
522		- if (err)
523		- return err;
524		-
525		- if (!(val & mask))
526		- return 0;
527		-
528		- usleep_range(1000, 2000);
529		- }
530		-
531		- dev_err(chip->dev, "Timeout while waiting for switch\n");
532		- return -ETIMEDOUT;
533		-}
534		-
535		-/* Indirect write to single pointer-data register with an Update bit */
536		-int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
537		-{
538		- u16 val;
539	404	int err;
540	405
541		- /* Wait until the previous operation is completed */
542		- err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
543		- if (err)
544		- return err;
	406	+ if (chip->info->ops->port_set_rgmii_delay) {
	407	+ err = chip->info->ops->port_set_rgmii_delay(chip, port,
	408	+ interface);
	409	+ if (err && err != -EOPNOTSUPP)
	410	+ return err;
	411	+ }
545	412
546		- /* Set the Update bit to trigger a write operation */
547		- val = BIT(15) \| update;
	413	+ if (chip->info->ops->port_set_cmode) {
	414	+ err = chip->info->ops->port_set_cmode(chip, port,
	415	+ interface);
	416	+ if (err && err != -EOPNOTSUPP)
	417	+ return err;
	418	+ }
548	419
549		- return mv88e6xxx_write(chip, addr, reg, val);
	420	+ return 0;
550	421	}
551	422
552	423	static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
..	..	@@ -559,15 +430,19 @@
559	430	return 0;
560	431
561	432	/* Port's MAC control must not be changed unless the link is down */
562		- err = chip->info->ops->port_set_link(chip, port, 0);
	433	+ err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
563	434	if (err)
564	435	return err;
565	436
566		- if (chip->info->ops->port_set_speed) {
567		- err = chip->info->ops->port_set_speed(chip, port, speed);
	437	+ if (chip->info->ops->port_set_speed_duplex) {
	438	+ err = chip->info->ops->port_set_speed_duplex(chip, port,
	439	+ speed, duplex);
568	440	if (err && err != -EOPNOTSUPP)
569	441	goto restore_link;
570	442	}
	443	+
	444	+ if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
	445	+ mode = chip->info->ops->port_max_speed_mode(port);
571	446
572	447	if (chip->info->ops->port_set_pause) {
573	448	err = chip->info->ops->port_set_pause(chip, port, pause);
..	..	@@ -575,25 +450,7 @@
575	450	goto restore_link;
576	451	}
577	452
578		- if (chip->info->ops->port_set_duplex) {
579		- err = chip->info->ops->port_set_duplex(chip, port, duplex);
580		- if (err && err != -EOPNOTSUPP)
581		- goto restore_link;
582		- }
583		-
584		- if (chip->info->ops->port_set_rgmii_delay) {
585		- err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
586		- if (err && err != -EOPNOTSUPP)
587		- goto restore_link;
588		- }
589		-
590		- if (chip->info->ops->port_set_cmode) {
591		- err = chip->info->ops->port_set_cmode(chip, port, mode);
592		- if (err && err != -EOPNOTSUPP)
593		- goto restore_link;
594		- }
595		-
596		- err = 0;
	453	+ err = mv88e6xxx_port_config_interface(chip, port, mode);
597	454	restore_link:
598	455	if (chip->info->ops->port_set_link(chip, port, link))
599	456	dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
..	..	@@ -601,27 +458,102 @@
601	458	return err;
602	459	}
603	460
604		-/* We expect the switch to perform auto negotiation if there is a real
605		- * phy. However, in the case of a fixed link phy, we force the port
606		- * settings from the fixed link settings.
607		- */
608		-static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
609		- struct phy_device *phydev)
	461	+static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
610	462	{
611	463	struct mv88e6xxx_chip *chip = ds->priv;
	464	+
	465	+ return port < chip->info->num_internal_phys;
	466	+}
	467	+
	468	+static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
	469	+{
	470	+ u16 reg;
612	471	int err;
613	472
614		- if (!phy_is_pseudo_fixed_link(phydev))
615		- return;
	473	+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
	474	+ if (err) {
	475	+ dev_err(chip->dev,
	476	+ "p%d: %s: failed to read port status\n",
	477	+ port, __func__);
	478	+ return err;
	479	+ }
616	480
617		- mutex_lock(&chip->reg_lock);
618		- err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
619		- phydev->duplex, phydev->pause,
620		- phydev->interface);
621		- mutex_unlock(&chip->reg_lock);
	481	+ return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
	482	+}
622	483
623		- if (err && err != -EOPNOTSUPP)
624		- dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
	484	+static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
	485	+ struct phylink_link_state *state)
	486	+{
	487	+ struct mv88e6xxx_chip *chip = ds->priv;
	488	+ u8 lane;
	489	+ int err;
	490	+
	491	+ mv88e6xxx_reg_lock(chip);
	492	+ lane = mv88e6xxx_serdes_get_lane(chip, port);
	493	+ if (lane && chip->info->ops->serdes_pcs_get_state)
	494	+ err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
	495	+ state);
	496	+ else
	497	+ err = -EOPNOTSUPP;
	498	+ mv88e6xxx_reg_unlock(chip);
	499	+
	500	+ return err;
	501	+}
	502	+
	503	+static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
	504	+ unsigned int mode,
	505	+ phy_interface_t interface,
	506	+ const unsigned long *advertise)
	507	+{
	508	+ const struct mv88e6xxx_ops *ops = chip->info->ops;
	509	+ u8 lane;
	510	+
	511	+ if (ops->serdes_pcs_config) {
	512	+ lane = mv88e6xxx_serdes_get_lane(chip, port);
	513	+ if (lane)
	514	+ return ops->serdes_pcs_config(chip, port, lane, mode,
	515	+ interface, advertise);
	516	+ }
	517	+
	518	+ return 0;
	519	+}
	520	+
	521	+static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
	522	+{
	523	+ struct mv88e6xxx_chip *chip = ds->priv;
	524	+ const struct mv88e6xxx_ops *ops;
	525	+ int err = 0;
	526	+ u8 lane;
	527	+
	528	+ ops = chip->info->ops;
	529	+
	530	+ if (ops->serdes_pcs_an_restart) {
	531	+ mv88e6xxx_reg_lock(chip);
	532	+ lane = mv88e6xxx_serdes_get_lane(chip, port);
	533	+ if (lane)
	534	+ err = ops->serdes_pcs_an_restart(chip, port, lane);
	535	+ mv88e6xxx_reg_unlock(chip);
	536	+
	537	+ if (err)
	538	+ dev_err(ds->dev, "p%d: failed to restart AN\n", port);
	539	+ }
	540	+}
	541	+
	542	+static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
	543	+ unsigned int mode,
	544	+ int speed, int duplex)
	545	+{
	546	+ const struct mv88e6xxx_ops *ops = chip->info->ops;
	547	+ u8 lane;
	548	+
	549	+ if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
	550	+ lane = mv88e6xxx_serdes_get_lane(chip, port);
	551	+ if (lane)
	552	+ return ops->serdes_pcs_link_up(chip, port, lane,
	553	+ speed, duplex);
	554	+ }
	555	+
	556	+ return 0;
625	557	}
626	558
627	559	static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
..	..	@@ -650,6 +582,20 @@
650	582	mv88e6065_phylink_validate(chip, port, mask, state);
651	583	}
652	584
	585	+static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
	586	+ unsigned long *mask,
	587	+ struct phylink_link_state *state)
	588	+{
	589	+ if (port >= 5)
	590	+ phylink_set(mask, 2500baseX_Full);
	591	+
	592	+ /* No ethtool bits for 200Mbps */
	593	+ phylink_set(mask, 1000baseT_Full);
	594	+ phylink_set(mask, 1000baseX_Full);
	595	+
	596	+ mv88e6065_phylink_validate(chip, port, mask, state);
	597	+}
	598	+
653	599	static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
654	600	unsigned long *mask,
655	601	struct phylink_link_state *state)
..	..	@@ -665,8 +611,10 @@
665	611	unsigned long *mask,
666	612	struct phylink_link_state *state)
667	613	{
668		- if (port >= 9)
	614	+ if (port >= 9) {
669	615	phylink_set(mask, 2500baseX_Full);
	616	+ phylink_set(mask, 2500baseT_Full);
	617	+ }
670	618
671	619	/* No ethtool bits for 200Mbps */
672	620	phylink_set(mask, 1000baseT_Full);
..	..	@@ -712,79 +660,136 @@
712	660	phylink_helper_basex_speed(state);
713	661	}
714	662
715		-static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
716		- struct phylink_link_state *state)
717		-{
718		- struct mv88e6xxx_chip *chip = ds->priv;
719		- int err;
720		-
721		- mutex_lock(&chip->reg_lock);
722		- if (chip->info->ops->port_link_state)
723		- err = chip->info->ops->port_link_state(chip, port, state);
724		- else
725		- err = -EOPNOTSUPP;
726		- mutex_unlock(&chip->reg_lock);
727		-
728		- return err;
729		-}
730		-
731	663	static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
732	664	unsigned int mode,
733	665	const struct phylink_link_state *state)
734	666	{
735	667	struct mv88e6xxx_chip *chip = ds->priv;
736		- int speed, duplex, link, pause, err;
	668	+ struct mv88e6xxx_port *p;
	669	+ int err = 0;
737	670
738		- if (mode == MLO_AN_PHY)
739		- return;
	671	+ p = &chip->ports[port];
740	672
741		- if (mode == MLO_AN_FIXED) {
742		- link = LINK_FORCED_UP;
743		- speed = state->speed;
744		- duplex = state->duplex;
745		- } else {
746		- speed = SPEED_UNFORCED;
747		- duplex = DUPLEX_UNFORCED;
748		- link = LINK_UNFORCED;
	673	+ mv88e6xxx_reg_lock(chip);
	674	+
	675	+ if (mode != MLO_AN_PHY \|\| !mv88e6xxx_phy_is_internal(ds, port)) {
	676	+ /* In inband mode, the link may come up at any time while the
	677	+ * link is not forced down. Force the link down while we
	678	+ * reconfigure the interface mode.
	679	+ */
	680	+ if (mode == MLO_AN_INBAND &&
	681	+ p->interface != state->interface &&
	682	+ chip->info->ops->port_set_link)
	683	+ chip->info->ops->port_set_link(chip, port,
	684	+ LINK_FORCED_DOWN);
	685	+
	686	+ err = mv88e6xxx_port_config_interface(chip, port,
	687	+ state->interface);
	688	+ if (err && err != -EOPNOTSUPP)
	689	+ goto err_unlock;
	690	+
	691	+ err = mv88e6xxx_serdes_pcs_config(chip, port, mode,
	692	+ state->interface,
	693	+ state->advertising);
	694	+ /* FIXME: we should restart negotiation if something changed -
	695	+ * which is something we get if we convert to using phylinks
	696	+ * PCS operations.
	697	+ */
	698	+ if (err > 0)
	699	+ err = 0;
749	700	}
750		- pause = !!phylink_test(state->advertising, Pause);
751	701
752		- mutex_lock(&chip->reg_lock);
753		- err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause,
754		- state->interface);
755		- mutex_unlock(&chip->reg_lock);
	702	+ /* Undo the forced down state above after completing configuration
	703	+ * irrespective of its state on entry, which allows the link to come
	704	+ * up in the in-band case where there is no separate SERDES. Also
	705	+ * ensure that the link can come up if the PPU is in use and we are
	706	+ * in PHY mode (we treat the PPU as an effective in-band mechanism.)
	707	+ */
	708	+ if (chip->info->ops->port_set_link &&
	709	+ ((mode == MLO_AN_INBAND && p->interface != state->interface) \|\|
	710	+ (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
	711	+ chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
	712	+
	713	+ p->interface = state->interface;
	714	+
	715	+err_unlock:
	716	+ mv88e6xxx_reg_unlock(chip);
756	717
757	718	if (err && err != -EOPNOTSUPP)
758		- dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
759		-}
760		-
761		-static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
762		-{
763		- struct mv88e6xxx_chip *chip = ds->priv;
764		- int err;
765		-
766		- mutex_lock(&chip->reg_lock);
767		- err = chip->info->ops->port_set_link(chip, port, link);
768		- mutex_unlock(&chip->reg_lock);
769		-
770		- if (err)
771		- dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
	719	+ dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
772	720	}
773	721
774	722	static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
775	723	unsigned int mode,
776	724	phy_interface_t interface)
777	725	{
778		- if (mode == MLO_AN_FIXED)
779		- mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
	726	+ struct mv88e6xxx_chip *chip = ds->priv;
	727	+ const struct mv88e6xxx_ops *ops;
	728	+ int err = 0;
	729	+
	730	+ ops = chip->info->ops;
	731	+
	732	+ mv88e6xxx_reg_lock(chip);
	733	+ /* Internal PHYs propagate their configuration directly to the MAC.
	734	+ * External PHYs depend on whether the PPU is enabled for this port.
	735	+ */
	736	+ if (((!mv88e6xxx_phy_is_internal(ds, port) &&
	737	+ !mv88e6xxx_port_ppu_updates(chip, port)) \|\|
	738	+ mode == MLO_AN_FIXED) && ops->port_set_link)
	739	+ err = ops->port_set_link(chip, port, LINK_FORCED_DOWN);
	740	+ mv88e6xxx_reg_unlock(chip);
	741	+
	742	+ if (err)
	743	+ dev_err(chip->dev,
	744	+ "p%d: failed to force MAC link down\n", port);
780	745	}
781	746
782	747	static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
783	748	unsigned int mode, phy_interface_t interface,
784		- struct phy_device *phydev)
	749	+ struct phy_device *phydev,
	750	+ int speed, int duplex,
	751	+ bool tx_pause, bool rx_pause)
785	752	{
786		- if (mode == MLO_AN_FIXED)
787		- mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
	753	+ struct mv88e6xxx_chip *chip = ds->priv;
	754	+ const struct mv88e6xxx_ops *ops;
	755	+ int err = 0;
	756	+
	757	+ ops = chip->info->ops;
	758	+
	759	+ mv88e6xxx_reg_lock(chip);
	760	+ /* Internal PHYs propagate their configuration directly to the MAC.
	761	+ * External PHYs depend on whether the PPU is enabled for this port.
	762	+ */
	763	+ if ((!mv88e6xxx_phy_is_internal(ds, port) &&
	764	+ !mv88e6xxx_port_ppu_updates(chip, port)) \|\|
	765	+ mode == MLO_AN_FIXED) {
	766	+ /* FIXME: for an automedia port, should we force the link
	767	+ * down here - what if the link comes up due to "other" media
	768	+ * while we're bringing the port up, how is the exclusivity
	769	+ * handled in the Marvell hardware? E.g. port 2 on 88E6390
	770	+ * shared between internal PHY and Serdes.
	771	+ */
	772	+ err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
	773	+ duplex);
	774	+ if (err)
	775	+ goto error;
	776	+
	777	+ if (ops->port_set_speed_duplex) {
	778	+ err = ops->port_set_speed_duplex(chip, port,
	779	+ speed, duplex);
	780	+ if (err && err != -EOPNOTSUPP)
	781	+ goto error;
	782	+ }
	783	+
	784	+ if (ops->port_set_link)
	785	+ err = ops->port_set_link(chip, port, LINK_FORCED_UP);
	786	+ }
	787	+error:
	788	+ mv88e6xxx_reg_unlock(chip);
	789	+
	790	+ if (err && err != -EOPNOTSUPP)
	791	+ dev_err(ds->dev,
	792	+ "p%d: failed to configure MAC link up\n", port);
788	793	}
789	794
790	795	static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
..	..	@@ -884,7 +889,7 @@
884	889	break;
885	890	case STATS_TYPE_BANK1:
886	891	reg = bank1_select;
887		- /* fall through */
	892	+ fallthrough;
888	893	case STATS_TYPE_BANK0:
889	894	reg \|= s->reg \| histogram;
890	895	mv88e6xxx_g1_stats_read(chip, reg, &low);
..	..	@@ -923,6 +928,12 @@
923	928	STATS_TYPE_BANK0 \| STATS_TYPE_PORT);
924	929	}
925	930
	931	+static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
	932	+ uint8_t *data)
	933	+{
	934	+ return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
	935	+}
	936	+
926	937	static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
927	938	uint8_t *data)
928	939	{
..	..	@@ -957,7 +968,7 @@
957	968	if (stringset != ETH_SS_STATS)
958	969	return;
959	970
960		- mutex_lock(&chip->reg_lock);
	971	+ mv88e6xxx_reg_lock(chip);
961	972
962	973	if (chip->info->ops->stats_get_strings)
963	974	count = chip->info->ops->stats_get_strings(chip, data);
..	..	@@ -970,7 +981,7 @@
970	981	data += count * ETH_GSTRING_LEN;
971	982	mv88e6xxx_atu_vtu_get_strings(data);
972	983
973		- mutex_unlock(&chip->reg_lock);
	984	+ mv88e6xxx_reg_unlock(chip);
974	985	}
975	986
976	987	static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
..	..	@@ -993,6 +1004,11 @@
993	1004	STATS_TYPE_PORT);
994	1005	}
995	1006
	1007	+static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
	1008	+{
	1009	+ return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
	1010	+}
	1011	+
996	1012	static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
997	1013	{
998	1014	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 \|
..	..	@@ -1008,7 +1024,7 @@
1008	1024	if (sset != ETH_SS_STATS)
1009	1025	return 0;
1010	1026
1011		- mutex_lock(&chip->reg_lock);
	1027	+ mv88e6xxx_reg_lock(chip);
1012	1028	if (chip->info->ops->stats_get_sset_count)
1013	1029	count = chip->info->ops->stats_get_sset_count(chip);
1014	1030	if (count < 0)
..	..	@@ -1025,7 +1041,7 @@
1025	1041	count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1026	1042
1027	1043	out:
1028		- mutex_unlock(&chip->reg_lock);
	1044	+ mv88e6xxx_reg_unlock(chip);
1029	1045
1030	1046	return count;
1031	1047	}
..	..	@@ -1040,11 +1056,11 @@
1040	1056	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1041	1057	stat = &mv88e6xxx_hw_stats[i];
1042	1058	if (stat->type & types) {
1043		- mutex_lock(&chip->reg_lock);
	1059	+ mv88e6xxx_reg_lock(chip);
1044	1060	data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1045	1061	bank1_select,
1046	1062	histogram);
1047		- mutex_unlock(&chip->reg_lock);
	1063	+ mv88e6xxx_reg_unlock(chip);
1048	1064
1049	1065	j++;
1050	1066	}
..	..	@@ -1057,6 +1073,13 @@
1057	1073	{
1058	1074	return mv88e6xxx_stats_get_stats(chip, port, data,
1059	1075	STATS_TYPE_BANK0 \| STATS_TYPE_PORT,
	1076	+ 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
	1077	+}
	1078	+
	1079	+static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
	1080	+ uint64_t *data)
	1081	+{
	1082	+ return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1060	1083	0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1061	1084	}
1062	1085
..	..	@@ -1096,14 +1119,14 @@
1096	1119	if (chip->info->ops->stats_get_stats)
1097	1120	count = chip->info->ops->stats_get_stats(chip, port, data);
1098	1121
1099		- mutex_lock(&chip->reg_lock);
	1122	+ mv88e6xxx_reg_lock(chip);
1100	1123	if (chip->info->ops->serdes_get_stats) {
1101	1124	data += count;
1102	1125	count = chip->info->ops->serdes_get_stats(chip, port, data);
1103	1126	}
1104	1127	data += count;
1105	1128	mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1106		- mutex_unlock(&chip->reg_lock);
	1129	+ mv88e6xxx_reg_unlock(chip);
1107	1130	}
1108	1131
1109	1132	static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
..	..	@@ -1112,10 +1135,10 @@
1112	1135	struct mv88e6xxx_chip *chip = ds->priv;
1113	1136	int ret;
1114	1137
1115		- mutex_lock(&chip->reg_lock);
	1138	+ mv88e6xxx_reg_lock(chip);
1116	1139
1117	1140	ret = mv88e6xxx_stats_snapshot(chip, port);
1118		- mutex_unlock(&chip->reg_lock);
	1141	+ mv88e6xxx_reg_unlock(chip);
1119	1142
1120	1143	if (ret < 0)
1121	1144	return;
..	..	@@ -1126,7 +1149,14 @@
1126	1149
1127	1150	static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1128	1151	{
1129		- return 32 * sizeof(u16);
	1152	+ struct mv88e6xxx_chip *chip = ds->priv;
	1153	+ int len;
	1154	+
	1155	+ len = 32 * sizeof(u16);
	1156	+ if (chip->info->ops->serdes_get_regs_len)
	1157	+ len += chip->info->ops->serdes_get_regs_len(chip, port);
	1158	+
	1159	+ return len;
1130	1160	}
1131	1161
1132	1162	static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
..	..	@@ -1138,11 +1168,11 @@
1138	1168	u16 *p = _p;
1139	1169	int i;
1140	1170
1141		- regs->version = 0;
	1171	+ regs->version = chip->info->prod_num;
1142	1172
1143	1173	memset(p, 0xff, 32 * sizeof(u16));
1144	1174
1145		- mutex_lock(&chip->reg_lock);
	1175	+ mv88e6xxx_reg_lock(chip);
1146	1176
1147	1177	for (i = 0; i < 32; i++) {
1148	1178
..	..	@@ -1151,7 +1181,10 @@
1151	1181	p[i] = reg;
1152	1182	}
1153	1183
1154		- mutex_unlock(&chip->reg_lock);
	1184	+ if (chip->info->ops->serdes_get_regs)
	1185	+ chip->info->ops->serdes_get_regs(chip, port, &p[i]);
	1186	+
	1187	+ mv88e6xxx_reg_unlock(chip);
1155	1188	}
1156	1189
1157	1190	static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
..	..	@@ -1168,35 +1201,43 @@
1168	1201	return 0;
1169	1202	}
1170	1203
	1204	+/* Mask of the local ports allowed to receive frames from a given fabric port */
1171	1205	static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1172	1206	{
1173		- struct dsa_switch *ds = NULL;
	1207	+ struct dsa_switch *ds = chip->ds;
	1208	+ struct dsa_switch_tree *dst = ds->dst;
1174	1209	struct net_device *br;
	1210	+ struct dsa_port *dp;
	1211	+ bool found = false;
1175	1212	u16 pvlan;
1176		- int i;
1177	1213
1178		- if (dev < DSA_MAX_SWITCHES)
1179		- ds = chip->ds->dst->ds[dev];
	1214	+ list_for_each_entry(dp, &dst->ports, list) {
	1215	+ if (dp->ds->index == dev && dp->index == port) {
	1216	+ found = true;
	1217	+ break;
	1218	+ }
	1219	+ }
1180	1220
1181	1221	/* Prevent frames from unknown switch or port */
1182		- if (!ds \|\| port >= ds->num_ports)
	1222	+ if (!found)
1183	1223	return 0;
1184	1224
1185	1225	/* Frames from DSA links and CPU ports can egress any local port */
1186		- if (dsa_is_cpu_port(ds, port) \|\| dsa_is_dsa_port(ds, port))
	1226	+ if (dp->type == DSA_PORT_TYPE_CPU \|\| dp->type == DSA_PORT_TYPE_DSA)
1187	1227	return mv88e6xxx_port_mask(chip);
1188	1228
1189		- br = ds->ports[port].bridge_dev;
	1229	+ br = dp->bridge_dev;
1190	1230	pvlan = 0;
1191	1231
1192	1232	/* Frames from user ports can egress any local DSA links and CPU ports,
1193	1233	* as well as any local member of their bridge group.
1194	1234	*/
1195		- for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1196		- if (dsa_is_cpu_port(chip->ds, i) \|\|
1197		- dsa_is_dsa_port(chip->ds, i) \|\|
1198		- (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
1199		- pvlan \|= BIT(i);
	1235	+ list_for_each_entry(dp, &dst->ports, list)
	1236	+ if (dp->ds == ds &&
	1237	+ (dp->type == DSA_PORT_TYPE_CPU \|\|
	1238	+ dp->type == DSA_PORT_TYPE_DSA \|\|
	1239	+ (br && dp->bridge_dev == br)))
	1240	+ pvlan \|= BIT(dp->index);
1200	1241
1201	1242	return pvlan;
1202	1243	}
..	..	@@ -1217,9 +1258,9 @@
1217	1258	struct mv88e6xxx_chip *chip = ds->priv;
1218	1259	int err;
1219	1260
1220		- mutex_lock(&chip->reg_lock);
	1261	+ mv88e6xxx_reg_lock(chip);
1221	1262	err = mv88e6xxx_port_set_state(chip, port, state);
1222		- mutex_unlock(&chip->reg_lock);
	1263	+ mv88e6xxx_reg_unlock(chip);
1223	1264
1224	1265	if (err)
1225	1266	dev_err(ds->dev, "p%d: failed to update state\n", port);
..	..	@@ -1246,6 +1287,7 @@
1246	1287
1247	1288	static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1248	1289	{
	1290	+ struct dsa_switch *ds = chip->ds;
1249	1291	int target, port;
1250	1292	int err;
1251	1293
..	..	@@ -1254,10 +1296,9 @@
1254	1296
1255	1297	/* Initialize the routing port to the 32 possible target devices */
1256	1298	for (target = 0; target < 32; target++) {
1257		- port = 0x1f;
1258		- if (target < DSA_MAX_SWITCHES)
1259		- if (chip->ds->rtable[target] != DSA_RTABLE_NONE)
1260		- port = chip->ds->rtable[target];
	1299	+ port = dsa_routing_port(ds, target);
	1300	+ if (port == ds->num_ports)
	1301	+ port = 0x1f;
1261	1302
1262	1303	err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1263	1304	if (err)
..	..	@@ -1364,7 +1405,7 @@
1364	1405	u16 pvlan = 0;
1365	1406
1366	1407	if (!mv88e6xxx_has_pvt(chip))
1367		- return -EOPNOTSUPP;
	1408	+ return 0;
1368	1409
1369	1410	/* Skip the local source device, which uses in-chip port VLAN */
1370	1411	if (dev != chip->ds->index)
..	..	@@ -1404,9 +1445,9 @@
1404	1445	struct mv88e6xxx_chip *chip = ds->priv;
1405	1446	int err;
1406	1447
1407		- mutex_lock(&chip->reg_lock);
	1448	+ mv88e6xxx_reg_lock(chip);
1408	1449	err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1409		- mutex_unlock(&chip->reg_lock);
	1450	+ mv88e6xxx_reg_unlock(chip);
1410	1451
1411	1452	if (err)
1412	1453	dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
..	..	@@ -1438,26 +1479,27 @@
1438	1479	return chip->info->ops->vtu_loadpurge(chip, entry);
1439	1480	}
1440	1481
1441		-static int mv88e6xxx_atu_new(struct mv88e6xxx_chip chip, u16 fid)
	1482	+int mv88e6xxx_fid_map(struct mv88e6xxx_chip chip, unsigned long fid_bitmap)
1442	1483	{
1443		- DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1444		- struct mv88e6xxx_vtu_entry vlan = {
1445		- .vid = chip->info->max_vid,
1446		- };
	1484	+ struct mv88e6xxx_vtu_entry vlan;
1447	1485	int i, err;
	1486	+ u16 fid;
1448	1487
1449	1488	bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1450	1489
1451	1490	/* Set every FID bit used by the (un)bridged ports */
1452	1491	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1453		- err = mv88e6xxx_port_get_fid(chip, i, fid);
	1492	+ err = mv88e6xxx_port_get_fid(chip, i, &fid);
1454	1493	if (err)
1455	1494	return err;
1456	1495
1457		- set_bit(*fid, fid_bitmap);
	1496	+ set_bit(fid, fid_bitmap);
1458	1497	}
1459	1498
1460	1499	/* Set every FID bit used by the VLAN entries */
	1500	+ vlan.vid = chip->info->max_vid;
	1501	+ vlan.valid = false;
	1502	+
1461	1503	do {
1462	1504	err = mv88e6xxx_vtu_getnext(chip, &vlan);
1463	1505	if (err)
..	..	@@ -1468,6 +1510,18 @@
1468	1510
1469	1511	set_bit(vlan.fid, fid_bitmap);
1470	1512	} while (vlan.vid < chip->info->max_vid);
	1513	+
	1514	+ return 0;
	1515	+}
	1516	+
	1517	+static int mv88e6xxx_atu_new(struct mv88e6xxx_chip chip, u16 fid)
	1518	+{
	1519	+ DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
	1520	+ int err;
	1521	+
	1522	+ err = mv88e6xxx_fid_map(chip, fid_bitmap);
	1523	+ if (err)
	1524	+ return err;
1471	1525
1472	1526	/* The reset value 0x000 is used to indicate that multiple address
1473	1527	* databases are not needed. Return the next positive available.
..	..	@@ -1480,51 +1534,11 @@
1480	1534	return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1481	1535	}
1482	1536
1483		-static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1484		- struct mv88e6xxx_vtu_entry *entry, bool new)
1485		-{
1486		- int err;
1487		-
1488		- if (!vid)
1489		- return -EOPNOTSUPP;
1490		-
1491		- entry->vid = vid - 1;
1492		- entry->valid = false;
1493		-
1494		- err = mv88e6xxx_vtu_getnext(chip, entry);
1495		- if (err)
1496		- return err;
1497		-
1498		- if (entry->vid == vid && entry->valid)
1499		- return 0;
1500		-
1501		- if (new) {
1502		- int i;
1503		-
1504		- /* Initialize a fresh VLAN entry */
1505		- memset(entry, 0, sizeof(*entry));
1506		- entry->valid = true;
1507		- entry->vid = vid;
1508		-
1509		- /* Exclude all ports */
1510		- for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1511		- entry->member[i] =
1512		- MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1513		-
1514		- return mv88e6xxx_atu_new(chip, &entry->fid);
1515		- }
1516		-
1517		- /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1518		- return -EOPNOTSUPP;
1519		-}
1520		-
1521	1537	static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1522	1538	u16 vid_begin, u16 vid_end)
1523	1539	{
1524	1540	struct mv88e6xxx_chip *chip = ds->priv;
1525		- struct mv88e6xxx_vtu_entry vlan = {
1526		- .vid = vid_begin - 1,
1527		- };
	1541	+ struct mv88e6xxx_vtu_entry vlan;
1528	1542	int i, err;
1529	1543
1530	1544	/* DSA and CPU ports have to be members of multiple vlans */
..	..	@@ -1534,12 +1548,13 @@
1534	1548	if (!vid_begin)
1535	1549	return -EOPNOTSUPP;
1536	1550
1537		- mutex_lock(&chip->reg_lock);
	1551	+ vlan.vid = vid_begin - 1;
	1552	+ vlan.valid = false;
1538	1553
1539	1554	do {
1540	1555	err = mv88e6xxx_vtu_getnext(chip, &vlan);
1541	1556	if (err)
1542		- goto unlock;
	1557	+ return err;
1543	1558
1544	1559	if (!vlan.valid)
1545	1560	break;
..	..	@@ -1551,7 +1566,7 @@
1551	1566	if (dsa_is_dsa_port(ds, i) \|\| dsa_is_cpu_port(ds, i))
1552	1567	continue;
1553	1568
1554		- if (!ds->ports[i].slave)
	1569	+ if (!dsa_to_port(ds, i)->slave)
1555	1570	continue;
1556	1571
1557	1572	if (vlan.member[i] ==
..	..	@@ -1559,7 +1574,7 @@
1559	1574	continue;
1560	1575
1561	1576	if (dsa_to_port(ds, i)->bridge_dev ==
1562		- ds->ports[port].bridge_dev)
	1577	+ dsa_to_port(ds, port)->bridge_dev)
1563	1578	break; /* same bridge, check next VLAN */
1564	1579
1565	1580	if (!dsa_to_port(ds, i)->bridge_dev)
..	..	@@ -1568,31 +1583,28 @@
1568	1583	dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1569	1584	port, vlan.vid, i,
1570	1585	netdev_name(dsa_to_port(ds, i)->bridge_dev));
1571		- err = -EOPNOTSUPP;
1572		- goto unlock;
	1586	+ return -EOPNOTSUPP;
1573	1587	}
1574	1588	} while (vlan.vid < vid_end);
1575	1589
1576		-unlock:
1577		- mutex_unlock(&chip->reg_lock);
1578		-
1579		- return err;
	1590	+ return 0;
1580	1591	}
1581	1592
1582	1593	static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1583		- bool vlan_filtering)
	1594	+ bool vlan_filtering,
	1595	+ struct switchdev_trans *trans)
1584	1596	{
1585	1597	struct mv88e6xxx_chip *chip = ds->priv;
1586	1598	u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1587	1599	MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1588	1600	int err;
1589	1601
1590		- if (!chip->info->max_vid)
1591		- return -EOPNOTSUPP;
	1602	+ if (switchdev_trans_ph_prepare(trans))
	1603	+ return chip->info->max_vid ? 0 : -EOPNOTSUPP;
1592	1604
1593		- mutex_lock(&chip->reg_lock);
	1605	+ mv88e6xxx_reg_lock(chip);
1594	1606	err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1595		- mutex_unlock(&chip->reg_lock);
	1607	+ mv88e6xxx_reg_unlock(chip);
1596	1608
1597	1609	return err;
1598	1610	}
..	..	@@ -1610,53 +1622,65 @@
1610	1622	/* If the requested port doesn't belong to the same bridge as the VLAN
1611	1623	* members, do not support it (yet) and fallback to software VLAN.
1612	1624	*/
	1625	+ mv88e6xxx_reg_lock(chip);
1613	1626	err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1614	1627	vlan->vid_end);
1615		- if (err)
1616		- return err;
	1628	+ mv88e6xxx_reg_unlock(chip);
1617	1629
1618	1630	/* We don't need any dynamic resource from the kernel (yet),
1619	1631	* so skip the prepare phase.
1620	1632	*/
1621		- return 0;
	1633	+ return err;
1622	1634	}
1623	1635
1624	1636	static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1625	1637	const unsigned char *addr, u16 vid,
1626	1638	u8 state)
1627	1639	{
1628		- struct mv88e6xxx_vtu_entry vlan;
1629	1640	struct mv88e6xxx_atu_entry entry;
	1641	+ struct mv88e6xxx_vtu_entry vlan;
	1642	+ u16 fid;
1630	1643	int err;
1631	1644
1632	1645	/* Null VLAN ID corresponds to the port private database */
1633		- if (vid == 0)
1634		- err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1635		- else
1636		- err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1637		- if (err)
1638		- return err;
	1646	+ if (vid == 0) {
	1647	+ err = mv88e6xxx_port_get_fid(chip, port, &fid);
	1648	+ if (err)
	1649	+ return err;
	1650	+ } else {
	1651	+ vlan.vid = vid - 1;
	1652	+ vlan.valid = false;
1639	1653
1640		- entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	1654	+ err = mv88e6xxx_vtu_getnext(chip, &vlan);
	1655	+ if (err)
	1656	+ return err;
	1657	+
	1658	+ /* switchdev expects -EOPNOTSUPP to honor software VLANs */
	1659	+ if (vlan.vid != vid \|\| !vlan.valid)
	1660	+ return -EOPNOTSUPP;
	1661	+
	1662	+ fid = vlan.fid;
	1663	+ }
	1664	+
	1665	+ entry.state = 0;
1641	1666	ether_addr_copy(entry.mac, addr);
1642	1667	eth_addr_dec(entry.mac);
1643	1668
1644		- err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
	1669	+ err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1645	1670	if (err)
1646	1671	return err;
1647	1672
1648	1673	/* Initialize a fresh ATU entry if it isn't found */
1649		- if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED \|\|
1650		- !ether_addr_equal(entry.mac, addr)) {
	1674	+ if (!entry.state \|\| !ether_addr_equal(entry.mac, addr)) {
1651	1675	memset(&entry, 0, sizeof(entry));
1652	1676	ether_addr_copy(entry.mac, addr);
1653	1677	}
1654	1678
1655	1679	/* Purge the ATU entry only if no port is using it anymore */
1656		- if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
	1680	+ if (!state) {
1657	1681	entry.portvec &= ~BIT(port);
1658	1682	if (!entry.portvec)
1659		- entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	1683	+ entry.state = 0;
1660	1684	} else {
1661	1685	if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
1662	1686	entry.portvec = BIT(port);
..	..	@@ -1666,7 +1690,217 @@
1666	1690	entry.state = state;
1667	1691	}
1668	1692
1669		- return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
	1693	+ return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
	1694	+}
	1695	+
	1696	+static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
	1697	+ const struct mv88e6xxx_policy *policy)
	1698	+{
	1699	+ enum mv88e6xxx_policy_mapping mapping = policy->mapping;
	1700	+ enum mv88e6xxx_policy_action action = policy->action;
	1701	+ const u8 *addr = policy->addr;
	1702	+ u16 vid = policy->vid;
	1703	+ u8 state;
	1704	+ int err;
	1705	+ int id;
	1706	+
	1707	+ if (!chip->info->ops->port_set_policy)
	1708	+ return -EOPNOTSUPP;
	1709	+
	1710	+ switch (mapping) {
	1711	+ case MV88E6XXX_POLICY_MAPPING_DA:
	1712	+ case MV88E6XXX_POLICY_MAPPING_SA:
	1713	+ if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
	1714	+ state = 0; /* Dissociate the port and address */
	1715	+ else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
	1716	+ is_multicast_ether_addr(addr))
	1717	+ state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
	1718	+ else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
	1719	+ is_unicast_ether_addr(addr))
	1720	+ state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
	1721	+ else
	1722	+ return -EOPNOTSUPP;
	1723	+
	1724	+ err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
	1725	+ state);
	1726	+ if (err)
	1727	+ return err;
	1728	+ break;
	1729	+ default:
	1730	+ return -EOPNOTSUPP;
	1731	+ }
	1732	+
	1733	+ /* Skip the port's policy clearing if the mapping is still in use */
	1734	+ if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
	1735	+ idr_for_each_entry(&chip->policies, policy, id)
	1736	+ if (policy->port == port &&
	1737	+ policy->mapping == mapping &&
	1738	+ policy->action != action)
	1739	+ return 0;
	1740	+
	1741	+ return chip->info->ops->port_set_policy(chip, port, mapping, action);
	1742	+}
	1743	+
	1744	+static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
	1745	+ struct ethtool_rx_flow_spec *fs)
	1746	+{
	1747	+ struct ethhdr *mac_entry = &fs->h_u.ether_spec;
	1748	+ struct ethhdr *mac_mask = &fs->m_u.ether_spec;
	1749	+ enum mv88e6xxx_policy_mapping mapping;
	1750	+ enum mv88e6xxx_policy_action action;
	1751	+ struct mv88e6xxx_policy *policy;
	1752	+ u16 vid = 0;
	1753	+ u8 *addr;
	1754	+ int err;
	1755	+ int id;
	1756	+
	1757	+ if (fs->location != RX_CLS_LOC_ANY)
	1758	+ return -EINVAL;
	1759	+
	1760	+ if (fs->ring_cookie == RX_CLS_FLOW_DISC)
	1761	+ action = MV88E6XXX_POLICY_ACTION_DISCARD;
	1762	+ else
	1763	+ return -EOPNOTSUPP;
	1764	+
	1765	+ switch (fs->flow_type & ~FLOW_EXT) {
	1766	+ case ETHER_FLOW:
	1767	+ if (!is_zero_ether_addr(mac_mask->h_dest) &&
	1768	+ is_zero_ether_addr(mac_mask->h_source)) {
	1769	+ mapping = MV88E6XXX_POLICY_MAPPING_DA;
	1770	+ addr = mac_entry->h_dest;
	1771	+ } else if (is_zero_ether_addr(mac_mask->h_dest) &&
	1772	+ !is_zero_ether_addr(mac_mask->h_source)) {
	1773	+ mapping = MV88E6XXX_POLICY_MAPPING_SA;
	1774	+ addr = mac_entry->h_source;
	1775	+ } else {
	1776	+ /* Cannot support DA and SA mapping in the same rule */
	1777	+ return -EOPNOTSUPP;
	1778	+ }
	1779	+ break;
	1780	+ default:
	1781	+ return -EOPNOTSUPP;
	1782	+ }
	1783	+
	1784	+ if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
	1785	+ if (fs->m_ext.vlan_tci != htons(0xffff))
	1786	+ return -EOPNOTSUPP;
	1787	+ vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
	1788	+ }
	1789	+
	1790	+ idr_for_each_entry(&chip->policies, policy, id) {
	1791	+ if (policy->port == port && policy->mapping == mapping &&
	1792	+ policy->action == action && policy->vid == vid &&
	1793	+ ether_addr_equal(policy->addr, addr))
	1794	+ return -EEXIST;
	1795	+ }
	1796	+
	1797	+ policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
	1798	+ if (!policy)
	1799	+ return -ENOMEM;
	1800	+
	1801	+ fs->location = 0;
	1802	+ err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
	1803	+ GFP_KERNEL);
	1804	+ if (err) {
	1805	+ devm_kfree(chip->dev, policy);
	1806	+ return err;
	1807	+ }
	1808	+
	1809	+ memcpy(&policy->fs, fs, sizeof(*fs));
	1810	+ ether_addr_copy(policy->addr, addr);
	1811	+ policy->mapping = mapping;
	1812	+ policy->action = action;
	1813	+ policy->port = port;
	1814	+ policy->vid = vid;
	1815	+
	1816	+ err = mv88e6xxx_policy_apply(chip, port, policy);
	1817	+ if (err) {
	1818	+ idr_remove(&chip->policies, fs->location);
	1819	+ devm_kfree(chip->dev, policy);
	1820	+ return err;
	1821	+ }
	1822	+
	1823	+ return 0;
	1824	+}
	1825	+
	1826	+static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
	1827	+ struct ethtool_rxnfc rxnfc, u32 rule_locs)
	1828	+{
	1829	+ struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
	1830	+ struct mv88e6xxx_chip *chip = ds->priv;
	1831	+ struct mv88e6xxx_policy *policy;
	1832	+ int err;
	1833	+ int id;
	1834	+
	1835	+ mv88e6xxx_reg_lock(chip);
	1836	+
	1837	+ switch (rxnfc->cmd) {
	1838	+ case ETHTOOL_GRXCLSRLCNT:
	1839	+ rxnfc->data = 0;
	1840	+ rxnfc->data \|= RX_CLS_LOC_SPECIAL;
	1841	+ rxnfc->rule_cnt = 0;
	1842	+ idr_for_each_entry(&chip->policies, policy, id)
	1843	+ if (policy->port == port)
	1844	+ rxnfc->rule_cnt++;
	1845	+ err = 0;
	1846	+ break;
	1847	+ case ETHTOOL_GRXCLSRULE:
	1848	+ err = -ENOENT;
	1849	+ policy = idr_find(&chip->policies, fs->location);
	1850	+ if (policy) {
	1851	+ memcpy(fs, &policy->fs, sizeof(*fs));
	1852	+ err = 0;
	1853	+ }
	1854	+ break;
	1855	+ case ETHTOOL_GRXCLSRLALL:
	1856	+ rxnfc->data = 0;
	1857	+ rxnfc->rule_cnt = 0;
	1858	+ idr_for_each_entry(&chip->policies, policy, id)
	1859	+ if (policy->port == port)
	1860	+ rule_locs[rxnfc->rule_cnt++] = id;
	1861	+ err = 0;
	1862	+ break;
	1863	+ default:
	1864	+ err = -EOPNOTSUPP;
	1865	+ break;
	1866	+ }
	1867	+
	1868	+ mv88e6xxx_reg_unlock(chip);
	1869	+
	1870	+ return err;
	1871	+}
	1872	+
	1873	+static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
	1874	+ struct ethtool_rxnfc *rxnfc)
	1875	+{
	1876	+ struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
	1877	+ struct mv88e6xxx_chip *chip = ds->priv;
	1878	+ struct mv88e6xxx_policy *policy;
	1879	+ int err;
	1880	+
	1881	+ mv88e6xxx_reg_lock(chip);
	1882	+
	1883	+ switch (rxnfc->cmd) {
	1884	+ case ETHTOOL_SRXCLSRLINS:
	1885	+ err = mv88e6xxx_policy_insert(chip, port, fs);
	1886	+ break;
	1887	+ case ETHTOOL_SRXCLSRLDEL:
	1888	+ err = -ENOENT;
	1889	+ policy = idr_remove(&chip->policies, fs->location);
	1890	+ if (policy) {
	1891	+ policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
	1892	+ err = mv88e6xxx_policy_apply(chip, port, policy);
	1893	+ devm_kfree(chip->dev, policy);
	1894	+ }
	1895	+ break;
	1896	+ default:
	1897	+ err = -EOPNOTSUPP;
	1898	+ break;
	1899	+ }
	1900	+
	1901	+ mv88e6xxx_reg_unlock(chip);
	1902	+
	1903	+ return err;
1670	1904	}
1671	1905
1672	1906	static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
..	..	@@ -1692,23 +1926,58 @@
1692	1926	return 0;
1693	1927	}
1694	1928
1695		-static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1696		- u16 vid, u8 member)
	1929	+static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
	1930	+ u16 vid, u8 member, bool warn)
1697	1931	{
	1932	+ const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1698	1933	struct mv88e6xxx_vtu_entry vlan;
1699		- int err;
	1934	+ int i, err;
1700	1935
1701		- err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
	1936	+ if (!vid)
	1937	+ return -EOPNOTSUPP;
	1938	+
	1939	+ vlan.vid = vid - 1;
	1940	+ vlan.valid = false;
	1941	+
	1942	+ err = mv88e6xxx_vtu_getnext(chip, &vlan);
1702	1943	if (err)
1703	1944	return err;
1704	1945
1705		- vlan.member[port] = member;
	1946	+ if (vlan.vid != vid \|\| !vlan.valid) {
	1947	+ memset(&vlan, 0, sizeof(vlan));
1706	1948
1707		- err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1708		- if (err)
1709		- return err;
	1949	+ err = mv88e6xxx_atu_new(chip, &vlan.fid);
	1950	+ if (err)
	1951	+ return err;
1710	1952
1711		- return mv88e6xxx_broadcast_setup(chip, vid);
	1953	+ for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
	1954	+ if (i == port)
	1955	+ vlan.member[i] = member;
	1956	+ else
	1957	+ vlan.member[i] = non_member;
	1958	+
	1959	+ vlan.vid = vid;
	1960	+ vlan.valid = true;
	1961	+
	1962	+ err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
	1963	+ if (err)
	1964	+ return err;
	1965	+
	1966	+ err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
	1967	+ if (err)
	1968	+ return err;
	1969	+ } else if (vlan.member[port] != member) {
	1970	+ vlan.member[port] = member;
	1971	+
	1972	+ err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
	1973	+ if (err)
	1974	+ return err;
	1975	+ } else if (warn) {
	1976	+ dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
	1977	+ port, vid);
	1978	+ }
	1979	+
	1980	+ return 0;
1712	1981	}
1713	1982
1714	1983	static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
..	..	@@ -1717,6 +1986,7 @@
1717	1986	struct mv88e6xxx_chip *chip = ds->priv;
1718	1987	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1719	1988	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
	1989	+ bool warn;
1720	1990	u8 member;
1721	1991	u16 vid;
1722	1992
..	..	@@ -1730,10 +2000,15 @@
1730	2000	else
1731	2001	member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1732	2002
1733		- mutex_lock(&chip->reg_lock);
	2003	+ /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
	2004	+ * and then the CPU port. Do not warn for duplicates for the CPU port.
	2005	+ */
	2006	+ warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
	2007	+
	2008	+ mv88e6xxx_reg_lock(chip);
1734	2009
1735	2010	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1736		- if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
	2011	+ if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn))
1737	2012	dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1738	2013	vid, untagged ? 'u' : 't');
1739	2014
..	..	@@ -1741,21 +2016,30 @@
1741	2016	dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1742	2017	vlan->vid_end);
1743	2018
1744		- mutex_unlock(&chip->reg_lock);
	2019	+ mv88e6xxx_reg_unlock(chip);
1745	2020	}
1746	2021
1747		-static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1748		- int port, u16 vid)
	2022	+static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
	2023	+ int port, u16 vid)
1749	2024	{
1750	2025	struct mv88e6xxx_vtu_entry vlan;
1751	2026	int i, err;
1752	2027
1753		- err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
	2028	+ if (!vid)
	2029	+ return -EOPNOTSUPP;
	2030	+
	2031	+ vlan.vid = vid - 1;
	2032	+ vlan.valid = false;
	2033	+
	2034	+ err = mv88e6xxx_vtu_getnext(chip, &vlan);
1754	2035	if (err)
1755	2036	return err;
1756	2037
1757		- /* Tell switchdev if this VLAN is handled in software */
1758		- if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
	2038	+ /* If the VLAN doesn't exist in hardware or the port isn't a member,
	2039	+ * tell switchdev that this VLAN is likely handled in software.
	2040	+ */
	2041	+ if (vlan.vid != vid \|\| !vlan.valid \|\|
	2042	+ vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1759	2043	return -EOPNOTSUPP;
1760	2044
1761	2045	vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
..	..	@@ -1787,14 +2071,14 @@
1787	2071	if (!chip->info->max_vid)
1788	2072	return -EOPNOTSUPP;
1789	2073
1790		- mutex_lock(&chip->reg_lock);
	2074	+ mv88e6xxx_reg_lock(chip);
1791	2075
1792	2076	err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1793	2077	if (err)
1794	2078	goto unlock;
1795	2079
1796	2080	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1797		- err = _mv88e6xxx_port_vlan_del(chip, port, vid);
	2081	+ err = mv88e6xxx_port_vlan_leave(chip, port, vid);
1798	2082	if (err)
1799	2083	goto unlock;
1800	2084
..	..	@@ -1806,7 +2090,7 @@
1806	2090	}
1807	2091
1808	2092	unlock:
1809		- mutex_unlock(&chip->reg_lock);
	2093	+ mv88e6xxx_reg_unlock(chip);
1810	2094
1811	2095	return err;
1812	2096	}
..	..	@@ -1817,10 +2101,10 @@
1817	2101	struct mv88e6xxx_chip *chip = ds->priv;
1818	2102	int err;
1819	2103
1820		- mutex_lock(&chip->reg_lock);
	2104	+ mv88e6xxx_reg_lock(chip);
1821	2105	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1822	2106	MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1823		- mutex_unlock(&chip->reg_lock);
	2107	+ mv88e6xxx_reg_unlock(chip);
1824	2108
1825	2109	return err;
1826	2110	}
..	..	@@ -1831,10 +2115,9 @@
1831	2115	struct mv88e6xxx_chip *chip = ds->priv;
1832	2116	int err;
1833	2117
1834		- mutex_lock(&chip->reg_lock);
1835		- err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1836		- MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1837		- mutex_unlock(&chip->reg_lock);
	2118	+ mv88e6xxx_reg_lock(chip);
	2119	+ err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
	2120	+ mv88e6xxx_reg_unlock(chip);
1838	2121
1839	2122	return err;
1840	2123	}
..	..	@@ -1847,17 +2130,15 @@
1847	2130	bool is_static;
1848	2131	int err;
1849	2132
1850		- addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
	2133	+ addr.state = 0;
1851	2134	eth_broadcast_addr(addr.mac);
1852	2135
1853	2136	do {
1854		- mutex_lock(&chip->reg_lock);
1855	2137	err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1856		- mutex_unlock(&chip->reg_lock);
1857	2138	if (err)
1858	2139	return err;
1859	2140
1860		- if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
	2141	+ if (!addr.state)
1861	2142	break;
1862	2143
1863	2144	if (addr.trunk \|\| (addr.portvec & BIT(port)) == 0)
..	..	@@ -1879,17 +2160,12 @@
1879	2160	static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1880	2161	dsa_fdb_dump_cb_t cb, void data)
1881	2162	{
1882		- struct mv88e6xxx_vtu_entry vlan = {
1883		- .vid = chip->info->max_vid,
1884		- };
	2163	+ struct mv88e6xxx_vtu_entry vlan;
1885	2164	u16 fid;
1886	2165	int err;
1887	2166
1888	2167	/* Dump port's default Filtering Information Database (VLAN ID 0) */
1889		- mutex_lock(&chip->reg_lock);
1890	2168	err = mv88e6xxx_port_get_fid(chip, port, &fid);
1891		- mutex_unlock(&chip->reg_lock);
1892		-
1893	2169	if (err)
1894	2170	return err;
1895	2171
..	..	@@ -1898,10 +2174,11 @@
1898	2174	return err;
1899	2175
1900	2176	/* Dump VLANs' Filtering Information Databases */
	2177	+ vlan.vid = chip->info->max_vid;
	2178	+ vlan.valid = false;
	2179	+
1901	2180	do {
1902		- mutex_lock(&chip->reg_lock);
1903	2181	err = mv88e6xxx_vtu_getnext(chip, &vlan);
1904		- mutex_unlock(&chip->reg_lock);
1905	2182	if (err)
1906	2183	return err;
1907	2184
..	..	@@ -1921,39 +2198,38 @@
1921	2198	dsa_fdb_dump_cb_t cb, void data)
1922	2199	{
1923	2200	struct mv88e6xxx_chip *chip = ds->priv;
	2201	+ int err;
1924	2202
1925		- return mv88e6xxx_port_db_dump(chip, port, cb, data);
	2203	+ mv88e6xxx_reg_lock(chip);
	2204	+ err = mv88e6xxx_port_db_dump(chip, port, cb, data);
	2205	+ mv88e6xxx_reg_unlock(chip);
	2206	+
	2207	+ return err;
1926	2208	}
1927	2209
1928	2210	static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1929	2211	struct net_device *br)
1930	2212	{
1931		- struct dsa_switch *ds;
1932		- int port;
1933		- int dev;
	2213	+ struct dsa_switch *ds = chip->ds;
	2214	+ struct dsa_switch_tree *dst = ds->dst;
	2215	+ struct dsa_port *dp;
1934	2216	int err;
1935	2217
1936		- /* Remap the Port VLAN of each local bridge group member */
1937		- for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1938		- if (chip->ds->ports[port].bridge_dev == br) {
1939		- err = mv88e6xxx_port_vlan_map(chip, port);
1940		- if (err)
1941		- return err;
1942		- }
1943		- }
1944		-
1945		- if (!mv88e6xxx_has_pvt(chip))
1946		- return 0;
1947		-
1948		- /* Remap the Port VLAN of each cross-chip bridge group member */
1949		- for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1950		- ds = chip->ds->dst->ds[dev];
1951		- if (!ds)
1952		- break;
1953		-
1954		- for (port = 0; port < ds->num_ports; ++port) {
1955		- if (ds->ports[port].bridge_dev == br) {
1956		- err = mv88e6xxx_pvt_map(chip, dev, port);
	2218	+ list_for_each_entry(dp, &dst->ports, list) {
	2219	+ if (dp->bridge_dev == br) {
	2220	+ if (dp->ds == ds) {
	2221	+ /* This is a local bridge group member,
	2222	+ * remap its Port VLAN Map.
	2223	+ */
	2224	+ err = mv88e6xxx_port_vlan_map(chip, dp->index);
	2225	+ if (err)
	2226	+ return err;
	2227	+ } else {
	2228	+ /* This is an external bridge group member,
	2229	+ * remap its cross-chip Port VLAN Table entry.
	2230	+ */
	2231	+ err = mv88e6xxx_pvt_map(chip, dp->ds->index,
	2232	+ dp->index);
1957	2233	if (err)
1958	2234	return err;
1959	2235	}
..	..	@@ -1969,9 +2245,9 @@
1969	2245	struct mv88e6xxx_chip *chip = ds->priv;
1970	2246	int err;
1971	2247
1972		- mutex_lock(&chip->reg_lock);
	2248	+ mv88e6xxx_reg_lock(chip);
1973	2249	err = mv88e6xxx_bridge_map(chip, br);
1974		- mutex_unlock(&chip->reg_lock);
	2250	+ mv88e6xxx_reg_unlock(chip);
1975	2251
1976	2252	return err;
1977	2253	}
..	..	@@ -1981,41 +2257,43 @@
1981	2257	{
1982	2258	struct mv88e6xxx_chip *chip = ds->priv;
1983	2259
1984		- mutex_lock(&chip->reg_lock);
	2260	+ mv88e6xxx_reg_lock(chip);
1985	2261	if (mv88e6xxx_bridge_map(chip, br) \|\|
1986	2262	mv88e6xxx_port_vlan_map(chip, port))
1987	2263	dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1988		- mutex_unlock(&chip->reg_lock);
	2264	+ mv88e6xxx_reg_unlock(chip);
1989	2265	}
1990	2266
1991		-static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
	2267	+static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
	2268	+ int tree_index, int sw_index,
1992	2269	int port, struct net_device *br)
1993	2270	{
1994	2271	struct mv88e6xxx_chip *chip = ds->priv;
1995	2272	int err;
1996	2273
1997		- if (!mv88e6xxx_has_pvt(chip))
	2274	+ if (tree_index != ds->dst->index)
1998	2275	return 0;
1999	2276
2000		- mutex_lock(&chip->reg_lock);
2001		- err = mv88e6xxx_pvt_map(chip, dev, port);
2002		- mutex_unlock(&chip->reg_lock);
	2277	+ mv88e6xxx_reg_lock(chip);
	2278	+ err = mv88e6xxx_pvt_map(chip, sw_index, port);
	2279	+ mv88e6xxx_reg_unlock(chip);
2003	2280
2004	2281	return err;
2005	2282	}
2006	2283
2007		-static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
	2284	+static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
	2285	+ int tree_index, int sw_index,
2008	2286	int port, struct net_device *br)
2009	2287	{
2010	2288	struct mv88e6xxx_chip *chip = ds->priv;
2011	2289
2012		- if (!mv88e6xxx_has_pvt(chip))
	2290	+ if (tree_index != ds->dst->index)
2013	2291	return;
2014	2292
2015		- mutex_lock(&chip->reg_lock);
2016		- if (mv88e6xxx_pvt_map(chip, dev, port))
	2293	+ mv88e6xxx_reg_lock(chip);
	2294	+ if (mv88e6xxx_pvt_map(chip, sw_index, port))
2017	2295	dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2018		- mutex_unlock(&chip->reg_lock);
	2296	+ mv88e6xxx_reg_unlock(chip);
2019	2297	}
2020	2298
2021	2299	static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
..	..	@@ -2036,6 +2314,8 @@
2036	2314	usleep_range(10000, 20000);
2037	2315	gpiod_set_value_cansleep(gpiod, 0);
2038	2316	usleep_range(10000, 20000);
	2317	+
	2318	+ mv88e6xxx_g1_wait_eeprom_done(chip);
2039	2319	}
2040	2320	}
2041	2321
..	..	@@ -2155,13 +2435,100 @@
2155	2435	return 0;
2156	2436	}
2157	2437
	2438	+static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
	2439	+{
	2440	+ struct mv88e6xxx_port *mvp = dev_id;
	2441	+ struct mv88e6xxx_chip *chip = mvp->chip;
	2442	+ irqreturn_t ret = IRQ_NONE;
	2443	+ int port = mvp->port;
	2444	+ u8 lane;
	2445	+
	2446	+ mv88e6xxx_reg_lock(chip);
	2447	+ lane = mv88e6xxx_serdes_get_lane(chip, port);
	2448	+ if (lane)
	2449	+ ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
	2450	+ mv88e6xxx_reg_unlock(chip);
	2451	+
	2452	+ return ret;
	2453	+}
	2454	+
	2455	+static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
	2456	+ u8 lane)
	2457	+{
	2458	+ struct mv88e6xxx_port *dev_id = &chip->ports[port];
	2459	+ unsigned int irq;
	2460	+ int err;
	2461	+
	2462	+ /* Nothing to request if this SERDES port has no IRQ */
	2463	+ irq = mv88e6xxx_serdes_irq_mapping(chip, port);
	2464	+ if (!irq)
	2465	+ return 0;
	2466	+
	2467	+ snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
	2468	+ "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
	2469	+
	2470	+ /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
	2471	+ mv88e6xxx_reg_unlock(chip);
	2472	+ err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
	2473	+ IRQF_ONESHOT, dev_id->serdes_irq_name,
	2474	+ dev_id);
	2475	+ mv88e6xxx_reg_lock(chip);
	2476	+ if (err)
	2477	+ return err;
	2478	+
	2479	+ dev_id->serdes_irq = irq;
	2480	+
	2481	+ return mv88e6xxx_serdes_irq_enable(chip, port, lane);
	2482	+}
	2483	+
	2484	+static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
	2485	+ u8 lane)
	2486	+{
	2487	+ struct mv88e6xxx_port *dev_id = &chip->ports[port];
	2488	+ unsigned int irq = dev_id->serdes_irq;
	2489	+ int err;
	2490	+
	2491	+ /* Nothing to free if no IRQ has been requested */
	2492	+ if (!irq)
	2493	+ return 0;
	2494	+
	2495	+ err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
	2496	+
	2497	+ /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
	2498	+ mv88e6xxx_reg_unlock(chip);
	2499	+ free_irq(irq, dev_id);
	2500	+ mv88e6xxx_reg_lock(chip);
	2501	+
	2502	+ dev_id->serdes_irq = 0;
	2503	+
	2504	+ return err;
	2505	+}
	2506	+
2158	2507	static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2159	2508	bool on)
2160	2509	{
2161		- if (chip->info->ops->serdes_power)
2162		- return chip->info->ops->serdes_power(chip, port, on);
	2510	+ u8 lane;
	2511	+ int err;
2163	2512
2164		- return 0;
	2513	+ lane = mv88e6xxx_serdes_get_lane(chip, port);
	2514	+ if (!lane)
	2515	+ return 0;
	2516	+
	2517	+ if (on) {
	2518	+ err = mv88e6xxx_serdes_power_up(chip, port, lane);
	2519	+ if (err)
	2520	+ return err;
	2521	+
	2522	+ err = mv88e6xxx_serdes_irq_request(chip, port, lane);
	2523	+ } else {
	2524	+ err = mv88e6xxx_serdes_irq_free(chip, port, lane);
	2525	+ if (err)
	2526	+ return err;
	2527	+
	2528	+ err = mv88e6xxx_serdes_power_down(chip, port, lane);
	2529	+ }
	2530	+
	2531	+ return err;
2165	2532	}
2166	2533
2167	2534	static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
..	..	@@ -2188,7 +2555,14 @@
2188	2555
2189	2556	if (chip->info->ops->set_egress_port) {
2190	2557	err = chip->info->ops->set_egress_port(chip,
2191		- upstream_port);
	2558	+ MV88E6XXX_EGRESS_DIR_INGRESS,
	2559	+ upstream_port);
	2560	+ if (err)
	2561	+ return err;
	2562	+
	2563	+ err = chip->info->ops->set_egress_port(chip,
	2564	+ MV88E6XXX_EGRESS_DIR_EGRESS,
	2565	+ upstream_port);
2192	2566	if (err)
2193	2567	return err;
2194	2568	}
..	..	@@ -2252,18 +2626,8 @@
2252	2626	if (err)
2253	2627	return err;
2254	2628
2255		- /* Enable the SERDES interface for DSA and CPU ports. Normal
2256		- * ports SERDES are enabled when the port is enabled, thus
2257		- * saving a bit of power.
2258		- */
2259		- if ((dsa_is_cpu_port(ds, port) \|\| dsa_is_dsa_port(ds, port))) {
2260		- err = mv88e6xxx_serdes_power(chip, port, true);
2261		- if (err)
2262		- return err;
2263		- }
2264		-
2265		- /* Port Control 2: don't force a good FCS, set the maximum frame size to
2266		- * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
	2629	+ /* Port Control 2: don't force a good FCS, set the MTU size to
	2630	+ * 10222 bytes, disable 802.1q tags checking, don't discard tagged or
2267	2631	* untagged frames on this port, do a destination address lookup on all
2268	2632	* received packets as usual, disable ARP mirroring and don't send a
2269	2633	* copy of all transmitted/received frames on this port to the CPU.
..	..	@@ -2282,7 +2646,7 @@
2282	2646	return err;
2283	2647
2284	2648	if (chip->info->ops->port_set_jumbo_size) {
2285		- err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
	2649	+ err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
2286	2650	if (err)
2287	2651	return err;
2288	2652	}
..	..	@@ -2338,9 +2702,11 @@
2338	2702	return err;
2339	2703	}
2340	2704
2341		- err = mv88e6xxx_setup_message_port(chip, port);
2342		- if (err)
2343		- return err;
	2705	+ if (chip->info->ops->port_setup_message_port) {
	2706	+ err = chip->info->ops->port_setup_message_port(chip, port);
	2707	+ if (err)
	2708	+ return err;
	2709	+ }
2344	2710
2345	2711	/* Port based VLAN map: give each port the same default address
2346	2712	* database, and allow bidirectional communication between the
..	..	@@ -2360,38 +2726,59 @@
2360	2726	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2361	2727	}
2362	2728
	2729	+static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
	2730	+{
	2731	+ struct mv88e6xxx_chip *chip = ds->priv;
	2732	+
	2733	+ if (chip->info->ops->port_set_jumbo_size)
	2734	+ return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
	2735	+ else if (chip->info->ops->set_max_frame_size)
	2736	+ return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
	2737	+ return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
	2738	+}
	2739	+
	2740	+static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
	2741	+{
	2742	+ struct mv88e6xxx_chip *chip = ds->priv;
	2743	+ int ret = 0;
	2744	+
	2745	+ if (dsa_is_dsa_port(ds, port) \|\| dsa_is_cpu_port(ds, port))
	2746	+ new_mtu += EDSA_HLEN;
	2747	+
	2748	+ mv88e6xxx_reg_lock(chip);
	2749	+ if (chip->info->ops->port_set_jumbo_size)
	2750	+ ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
	2751	+ else if (chip->info->ops->set_max_frame_size)
	2752	+ ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
	2753	+ else
	2754	+ if (new_mtu > 1522)
	2755	+ ret = -EINVAL;
	2756	+ mv88e6xxx_reg_unlock(chip);
	2757	+
	2758	+ return ret;
	2759	+}
	2760	+
2363	2761	static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2364	2762	struct phy_device *phydev)
2365	2763	{
2366	2764	struct mv88e6xxx_chip *chip = ds->priv;
2367	2765	int err;
2368	2766
2369		- mutex_lock(&chip->reg_lock);
2370		-
	2767	+ mv88e6xxx_reg_lock(chip);
2371	2768	err = mv88e6xxx_serdes_power(chip, port, true);
2372		-
2373		- if (!err && chip->info->ops->serdes_irq_setup)
2374		- err = chip->info->ops->serdes_irq_setup(chip, port);
2375		-
2376		- mutex_unlock(&chip->reg_lock);
	2769	+ mv88e6xxx_reg_unlock(chip);
2377	2770
2378	2771	return err;
2379	2772	}
2380	2773
2381		-static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
2382		- struct phy_device *phydev)
	2774	+static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2383	2775	{
2384	2776	struct mv88e6xxx_chip *chip = ds->priv;
2385	2777
2386		- mutex_lock(&chip->reg_lock);
2387		-
2388		- if (chip->info->ops->serdes_irq_free)
2389		- chip->info->ops->serdes_irq_free(chip, port);
2390		-
	2778	+ mv88e6xxx_reg_lock(chip);
2391	2779	if (mv88e6xxx_serdes_power(chip, port, false))
2392	2780	dev_err(chip->dev, "failed to power off SERDES\n");
2393		-
2394		- mutex_unlock(&chip->reg_lock);
	2781	+ mv88e6xxx_reg_unlock(chip);
2395	2782	}
2396	2783
2397	2784	static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
..	..	@@ -2400,9 +2787,9 @@
2400	2787	struct mv88e6xxx_chip *chip = ds->priv;
2401	2788	int err;
2402	2789
2403		- mutex_lock(&chip->reg_lock);
	2790	+ mv88e6xxx_reg_lock(chip);
2404	2791	err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2405		- mutex_unlock(&chip->reg_lock);
	2792	+ mv88e6xxx_reg_unlock(chip);
2406	2793
2407	2794	return err;
2408	2795	}
..	..	@@ -2421,58 +2808,6 @@
2421	2808	return mv88e6xxx_g1_stats_clear(chip);
2422	2809	}
2423	2810
2424		-/* The mv88e6390 has some hidden registers used for debug and
2425		- * development. The errata also makes use of them.
2426		- */
2427		-static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port,
2428		- int reg, u16 val)
2429		-{
2430		- u16 ctrl;
2431		- int err;
2432		-
2433		- err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT,
2434		- PORT_RESERVED_1A, val);
2435		- if (err)
2436		- return err;
2437		-
2438		- ctrl = PORT_RESERVED_1A_BUSY \| PORT_RESERVED_1A_WRITE \|
2439		- PORT_RESERVED_1A_BLOCK \| port << PORT_RESERVED_1A_PORT_SHIFT \|
2440		- reg;
2441		-
2442		- return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2443		- PORT_RESERVED_1A, ctrl);
2444		-}
2445		-
2446		-static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip)
2447		-{
2448		- return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT,
2449		- PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY);
2450		-}
2451		-
2452		-
2453		-static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port,
2454		- int reg, u16 *val)
2455		-{
2456		- u16 ctrl;
2457		- int err;
2458		-
2459		- ctrl = PORT_RESERVED_1A_BUSY \| PORT_RESERVED_1A_READ \|
2460		- PORT_RESERVED_1A_BLOCK \| port << PORT_RESERVED_1A_PORT_SHIFT \|
2461		- reg;
2462		-
2463		- err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2464		- PORT_RESERVED_1A, ctrl);
2465		- if (err)
2466		- return err;
2467		-
2468		- err = mv88e6390_hidden_wait(chip);
2469		- if (err)
2470		- return err;
2471		-
2472		- return mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT,
2473		- PORT_RESERVED_1A, val);
2474		-}
2475		-
2476	2811	/* Check if the errata has already been applied. */
2477	2812	static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2478	2813	{
..	..	@@ -2481,7 +2816,7 @@
2481	2816	u16 val;
2482	2817
2483	2818	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2484		- err = mv88e6390_hidden_read(chip, port, 0, &val);
	2819	+ err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2485	2820	if (err) {
2486	2821	dev_err(chip->dev,
2487	2822	"Error reading hidden register: %d\n", err);
..	..	@@ -2514,12 +2849,19 @@
2514	2849	}
2515	2850
2516	2851	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2517		- err = mv88e6390_hidden_write(chip, port, 0, 0x01c0);
	2852	+ err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
2518	2853	if (err)
2519	2854	return err;
2520	2855	}
2521	2856
2522	2857	return mv88e6xxx_software_reset(chip);
	2858	+}
	2859	+
	2860	+static void mv88e6xxx_teardown(struct dsa_switch *ds)
	2861	+{
	2862	+ mv88e6xxx_teardown_devlink_params(ds);
	2863	+ dsa_devlink_resources_unregister(ds);
	2864	+ mv88e6xxx_teardown_devlink_regions(ds);
2523	2865	}
2524	2866
2525	2867	static int mv88e6xxx_setup(struct dsa_switch *ds)
..	..	@@ -2532,7 +2874,7 @@
2532	2874	chip->ds = ds;
2533	2875	ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2534	2876
2535		- mutex_lock(&chip->reg_lock);
	2877	+ mv88e6xxx_reg_lock(chip);
2536	2878
2537	2879	if (chip->info->ops->setup_errata) {
2538	2880	err = chip->info->ops->setup_errata(chip);
..	..	@@ -2555,6 +2897,13 @@
2555	2897	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2556	2898	if (dsa_is_unused_port(ds, i))
2557	2899	continue;
	2900	+
	2901	+ /* Prevent the use of an invalid port. */
	2902	+ if (mv88e6xxx_is_invalid_port(chip, i)) {
	2903	+ dev_err(chip->dev, "port %d is invalid\n", i);
	2904	+ err = -EINVAL;
	2905	+ goto unlock;
	2906	+ }
2558	2907
2559	2908	err = mv88e6xxx_setup_port(chip, i);
2560	2909	if (err)
..	..	@@ -2629,7 +2978,34 @@
2629	2978	goto unlock;
2630	2979
2631	2980	unlock:
2632		- mutex_unlock(&chip->reg_lock);
	2981	+ mv88e6xxx_reg_unlock(chip);
	2982	+
	2983	+ if (err)
	2984	+ return err;
	2985	+
	2986	+ /* Have to be called without holding the register lock, since
	2987	+ * they take the devlink lock, and we later take the locks in
	2988	+ * the reverse order when getting/setting parameters or
	2989	+ * resource occupancy.
	2990	+ */
	2991	+ err = mv88e6xxx_setup_devlink_resources(ds);
	2992	+ if (err)
	2993	+ return err;
	2994	+
	2995	+ err = mv88e6xxx_setup_devlink_params(ds);
	2996	+ if (err)
	2997	+ goto out_resources;
	2998	+
	2999	+ err = mv88e6xxx_setup_devlink_regions(ds);
	3000	+ if (err)
	3001	+ goto out_params;
	3002	+
	3003	+ return 0;
	3004	+
	3005	+out_params:
	3006	+ mv88e6xxx_teardown_devlink_params(ds);
	3007	+out_resources:
	3008	+ dsa_devlink_resources_unregister(ds);
2633	3009
2634	3010	return err;
2635	3011	}
..	..	@@ -2651,9 +3027,9 @@
2651	3027	if (!chip->info->ops->phy_read)
2652	3028	return -EOPNOTSUPP;
2653	3029
2654		- mutex_lock(&chip->reg_lock);
	3030	+ mv88e6xxx_reg_lock(chip);
2655	3031	err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2656		- mutex_unlock(&chip->reg_lock);
	3032	+ mv88e6xxx_reg_unlock(chip);
2657	3033
2658	3034	/* Some internal PHYs don't have a model number. */
2659	3035	if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
..	..	@@ -2675,9 +3051,9 @@
2675	3051	if (!chip->info->ops->phy_write)
2676	3052	return -EOPNOTSUPP;
2677	3053
2678		- mutex_lock(&chip->reg_lock);
	3054	+ mv88e6xxx_reg_lock(chip);
2679	3055	err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2680		- mutex_unlock(&chip->reg_lock);
	3056	+ mv88e6xxx_reg_unlock(chip);
2681	3057
2682	3058	return err;
2683	3059	}
..	..	@@ -2692,15 +3068,15 @@
2692	3068	int err;
2693	3069
2694	3070	if (external) {
2695		- mutex_lock(&chip->reg_lock);
	3071	+ mv88e6xxx_reg_lock(chip);
2696	3072	err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
2697		- mutex_unlock(&chip->reg_lock);
	3073	+ mv88e6xxx_reg_unlock(chip);
2698	3074
2699	3075	if (err)
2700	3076	return err;
2701	3077	}
2702	3078
2703		- bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
	3079	+ bus = mdiobus_alloc_size(sizeof(*mdio_bus));
2704	3080	if (!bus)
2705	3081	return -ENOMEM;
2706	3082
..	..	@@ -2725,14 +3101,14 @@
2725	3101	if (!external) {
2726	3102	err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
2727	3103	if (err)
2728		- return err;
	3104	+ goto out;
2729	3105	}
2730	3106
2731	3107	err = of_mdiobus_register(bus, np);
2732	3108	if (err) {
2733	3109	dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2734	3110	mv88e6xxx_g2_irq_mdio_free(chip, bus);
2735		- return err;
	3111	+ goto out;
2736	3112	}
2737	3113
2738	3114	if (external)
..	..	@@ -2741,34 +3117,32 @@
2741	3117	list_add(&mdio_bus->list, &chip->mdios);
2742	3118
2743	3119	return 0;
2744		-}
2745	3120
2746		-static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2747		- { .compatible = "marvell,mv88e6xxx-mdio-external",
2748		- .data = (void *)true },
2749		- { },
2750		-};
	3121	+out:
	3122	+ mdiobus_free(bus);
	3123	+ return err;
	3124	+}
2751	3125
2752	3126	static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2753	3127
2754	3128	{
2755		- struct mv88e6xxx_mdio_bus *mdio_bus;
	3129	+ struct mv88e6xxx_mdio_bus mdio_bus, p;
2756	3130	struct mii_bus *bus;
2757	3131
2758		- list_for_each_entry(mdio_bus, &chip->mdios, list) {
	3132	+ list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
2759	3133	bus = mdio_bus->bus;
2760	3134
2761	3135	if (!mdio_bus->external)
2762	3136	mv88e6xxx_g2_irq_mdio_free(chip, bus);
2763	3137
2764	3138	mdiobus_unregister(bus);
	3139	+ mdiobus_free(bus);
2765	3140	}
2766	3141	}
2767	3142
2768	3143	static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2769	3144	struct device_node *np)
2770	3145	{
2771		- const struct of_device_id *match;
2772	3146	struct device_node *child;
2773	3147	int err;
2774	3148
..	..	@@ -2778,6 +3152,7 @@
2778	3152	*/
2779	3153	child = of_get_child_by_name(np, "mdio");
2780	3154	err = mv88e6xxx_mdio_register(chip, child, false);
	3155	+ of_node_put(child);
2781	3156	if (err)
2782	3157	return err;
2783	3158
..	..	@@ -2786,11 +3161,12 @@
2786	3161	* bus.
2787	3162	*/
2788	3163	for_each_available_child_of_node(np, child) {
2789		- match = of_match_node(mv88e6xxx_mdio_external_match, child);
2790		- if (match) {
	3164	+ if (of_device_is_compatible(
	3165	+ child, "marvell,mv88e6xxx-mdio-external")) {
2791	3166	err = mv88e6xxx_mdio_register(chip, child, true);
2792	3167	if (err) {
2793	3168	mv88e6xxx_mdios_unregister(chip);
	3169	+ of_node_put(child);
2794	3170	return err;
2795	3171	}
2796	3172	}
..	..	@@ -2815,9 +3191,9 @@
2815	3191	if (!chip->info->ops->get_eeprom)
2816	3192	return -EOPNOTSUPP;
2817	3193
2818		- mutex_lock(&chip->reg_lock);
	3194	+ mv88e6xxx_reg_lock(chip);
2819	3195	err = chip->info->ops->get_eeprom(chip, eeprom, data);
2820		- mutex_unlock(&chip->reg_lock);
	3196	+ mv88e6xxx_reg_unlock(chip);
2821	3197
2822	3198	if (err)
2823	3199	return err;
..	..	@@ -2839,9 +3215,9 @@
2839	3215	if (eeprom->magic != 0xc3ec4951)
2840	3216	return -EINVAL;
2841	3217
2842		- mutex_lock(&chip->reg_lock);
	3218	+ mv88e6xxx_reg_lock(chip);
2843	3219	err = chip->info->ops->set_eeprom(chip, eeprom, data);
2844		- mutex_unlock(&chip->reg_lock);
	3220	+ mv88e6xxx_reg_unlock(chip);
2845	3221
2846	3222	return err;
2847	3223	}
..	..	@@ -2855,8 +3231,7 @@
2855	3231	.phy_read = mv88e6185_phy_ppu_read,
2856	3232	.phy_write = mv88e6185_phy_ppu_write,
2857	3233	.port_set_link = mv88e6xxx_port_set_link,
2858		- .port_set_duplex = mv88e6xxx_port_set_duplex,
2859		- .port_set_speed = mv88e6185_port_set_speed,
	3234	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
2860	3235	.port_tag_remap = mv88e6095_port_tag_remap,
2861	3236	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2862	3237	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -2865,8 +3240,8 @@
2865	3240	.port_pause_limit = mv88e6097_port_pause_limit,
2866	3241	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2867	3242	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2868		- .port_link_state = mv88e6352_port_link_state,
2869	3243	.port_get_cmode = mv88e6185_port_get_cmode,
	3244	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
2870	3245	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2871	3246	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2872	3247	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -2884,6 +3259,7 @@
2884	3259	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2885	3260	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2886	3261	.phylink_validate = mv88e6185_phylink_validate,
	3262	+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
2887	3263	};
2888	3264
2889	3265	static const struct mv88e6xxx_ops mv88e6095_ops = {
..	..	@@ -2894,13 +3270,12 @@
2894	3270	.phy_read = mv88e6185_phy_ppu_read,
2895	3271	.phy_write = mv88e6185_phy_ppu_write,
2896	3272	.port_set_link = mv88e6xxx_port_set_link,
2897		- .port_set_duplex = mv88e6xxx_port_set_duplex,
2898		- .port_set_speed = mv88e6185_port_set_speed,
	3273	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
2899	3274	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2900	3275	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2901	3276	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2902		- .port_link_state = mv88e6185_port_link_state,
2903	3277	.port_get_cmode = mv88e6185_port_get_cmode,
	3278	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
2904	3279	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2905	3280	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2906	3281	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -2913,6 +3288,7 @@
2913	3288	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2914	3289	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2915	3290	.phylink_validate = mv88e6185_phylink_validate,
	3291	+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
2916	3292	};
2917	3293
2918	3294	static const struct mv88e6xxx_ops mv88e6097_ops = {
..	..	@@ -2924,9 +3300,9 @@
2924	3300	.phy_read = mv88e6xxx_g2_smi_phy_read,
2925	3301	.phy_write = mv88e6xxx_g2_smi_phy_write,
2926	3302	.port_set_link = mv88e6xxx_port_set_link,
2927		- .port_set_duplex = mv88e6xxx_port_set_duplex,
2928		- .port_set_speed = mv88e6185_port_set_speed,
	3303	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
2929	3304	.port_tag_remap = mv88e6095_port_tag_remap,
	3305	+ .port_set_policy = mv88e6352_port_set_policy,
2930	3306	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2931	3307	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2932	3308	.port_set_ether_type = mv88e6351_port_set_ether_type,
..	..	@@ -2934,8 +3310,8 @@
2934	3310	.port_pause_limit = mv88e6097_port_pause_limit,
2935	3311	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2936	3312	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2937		- .port_link_state = mv88e6352_port_link_state,
2938	3313	.port_get_cmode = mv88e6185_port_get_cmode,
	3314	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
2939	3315	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2940	3316	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2941	3317	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -2951,6 +3327,7 @@
2951	3327	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2952	3328	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2953	3329	.phylink_validate = mv88e6185_phylink_validate,
	3330	+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
2954	3331	};
2955	3332
2956	3333	static const struct mv88e6xxx_ops mv88e6123_ops = {
..	..	@@ -2962,14 +3339,13 @@
2962	3339	.phy_read = mv88e6xxx_g2_smi_phy_read,
2963	3340	.phy_write = mv88e6xxx_g2_smi_phy_write,
2964	3341	.port_set_link = mv88e6xxx_port_set_link,
2965		- .port_set_duplex = mv88e6xxx_port_set_duplex,
2966		- .port_set_speed = mv88e6185_port_set_speed,
	3342	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
2967	3343	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2968	3344	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2969	3345	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2970	3346	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2971		- .port_link_state = mv88e6352_port_link_state,
2972	3347	.port_get_cmode = mv88e6185_port_get_cmode,
	3348	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
2973	3349	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2974	3350	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2975	3351	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -2981,9 +3357,12 @@
2981	3357	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2982	3358	.pot_clear = mv88e6xxx_g2_pot_clear,
2983	3359	.reset = mv88e6352_g1_reset,
	3360	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3361	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
2984	3362	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2985	3363	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2986	3364	.phylink_validate = mv88e6185_phylink_validate,
	3365	+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
2987	3366	};
2988	3367
2989	3368	static const struct mv88e6xxx_ops mv88e6131_ops = {
..	..	@@ -2994,8 +3373,7 @@
2994	3373	.phy_read = mv88e6185_phy_ppu_read,
2995	3374	.phy_write = mv88e6185_phy_ppu_write,
2996	3375	.port_set_link = mv88e6xxx_port_set_link,
2997		- .port_set_duplex = mv88e6xxx_port_set_duplex,
2998		- .port_set_speed = mv88e6185_port_set_speed,
	3376	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
2999	3377	.port_tag_remap = mv88e6095_port_tag_remap,
3000	3378	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3001	3379	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
..	..	@@ -3005,8 +3383,8 @@
3005	3383	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3006	3384	.port_pause_limit = mv88e6097_port_pause_limit,
3007	3385	.port_set_pause = mv88e6185_port_set_pause,
3008		- .port_link_state = mv88e6352_port_link_state,
3009	3386	.port_get_cmode = mv88e6185_port_get_cmode,
	3387	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3010	3388	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3011	3389	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3012	3390	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3036,9 +3414,9 @@
3036	3414	.phy_read = mv88e6xxx_g2_smi_phy_read,
3037	3415	.phy_write = mv88e6xxx_g2_smi_phy_write,
3038	3416	.port_set_link = mv88e6xxx_port_set_link,
3039		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3040	3417	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3041		- .port_set_speed = mv88e6341_port_set_speed,
	3418	+ .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
	3419	+ .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3042	3420	.port_tag_remap = mv88e6095_port_tag_remap,
3043	3421	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3044	3422	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -3048,8 +3426,9 @@
3048	3426	.port_pause_limit = mv88e6097_port_pause_limit,
3049	3427	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3050	3428	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3051		- .port_link_state = mv88e6352_port_link_state,
3052	3429	.port_get_cmode = mv88e6352_port_get_cmode,
	3430	+ .port_set_cmode = mv88e6341_port_set_cmode,
	3431	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3053	3432	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3054	3433	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3055	3434	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3061,11 +3440,28 @@
3061	3440	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3062	3441	.pot_clear = mv88e6xxx_g2_pot_clear,
3063	3442	.reset = mv88e6352_g1_reset,
	3443	+ .rmu_disable = mv88e6390_g1_rmu_disable,
	3444	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3445	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3064	3446	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3065	3447	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3066		- .serdes_power = mv88e6341_serdes_power,
	3448	+ .serdes_power = mv88e6390_serdes_power,
	3449	+ .serdes_get_lane = mv88e6341_serdes_get_lane,
	3450	+ /* Check status register pause & lpa register */
	3451	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	3452	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	3453	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	3454	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	3455	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	3456	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	3457	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
3067	3458	.gpio_ops = &mv88e6352_gpio_ops,
3068		- .phylink_validate = mv88e6390_phylink_validate,
	3459	+ .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
	3460	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	3461	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	3462	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	3463	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
	3464	+ .phylink_validate = mv88e6341_phylink_validate,
3069	3465	};
3070	3466
3071	3467	static const struct mv88e6xxx_ops mv88e6161_ops = {
..	..	@@ -3077,19 +3473,17 @@
3077	3473	.phy_read = mv88e6xxx_g2_smi_phy_read,
3078	3474	.phy_write = mv88e6xxx_g2_smi_phy_write,
3079	3475	.port_set_link = mv88e6xxx_port_set_link,
3080		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3081		- .port_set_speed = mv88e6185_port_set_speed,
	3476	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3082	3477	.port_tag_remap = mv88e6095_port_tag_remap,
3083	3478	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3084	3479	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3085	3480	.port_set_ether_type = mv88e6351_port_set_ether_type,
3086		- .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3087	3481	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3088	3482	.port_pause_limit = mv88e6097_port_pause_limit,
3089	3483	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3090	3484	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3091		- .port_link_state = mv88e6352_port_link_state,
3092	3485	.port_get_cmode = mv88e6185_port_get_cmode,
	3486	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3093	3487	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3094	3488	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3095	3489	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3101,11 +3495,14 @@
3101	3495	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3102	3496	.pot_clear = mv88e6xxx_g2_pot_clear,
3103	3497	.reset = mv88e6352_g1_reset,
	3498	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3499	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3104	3500	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3105	3501	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3106	3502	.avb_ops = &mv88e6165_avb_ops,
3107	3503	.ptp_ops = &mv88e6165_ptp_ops,
3108	3504	.phylink_validate = mv88e6185_phylink_validate,
	3505	+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3109	3506	};
3110	3507
3111	3508	static const struct mv88e6xxx_ops mv88e6165_ops = {
..	..	@@ -3117,12 +3514,11 @@
3117	3514	.phy_read = mv88e6165_phy_read,
3118	3515	.phy_write = mv88e6165_phy_write,
3119	3516	.port_set_link = mv88e6xxx_port_set_link,
3120		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3121		- .port_set_speed = mv88e6185_port_set_speed,
	3517	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3122	3518	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3123	3519	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3124		- .port_link_state = mv88e6352_port_link_state,
3125	3520	.port_get_cmode = mv88e6185_port_get_cmode,
	3521	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3126	3522	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3127	3523	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3128	3524	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3134,6 +3530,8 @@
3134	3530	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3135	3531	.pot_clear = mv88e6xxx_g2_pot_clear,
3136	3532	.reset = mv88e6352_g1_reset,
	3533	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3534	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3137	3535	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3138	3536	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3139	3537	.avb_ops = &mv88e6165_avb_ops,
..	..	@@ -3150,9 +3548,8 @@
3150	3548	.phy_read = mv88e6xxx_g2_smi_phy_read,
3151	3549	.phy_write = mv88e6xxx_g2_smi_phy_write,
3152	3550	.port_set_link = mv88e6xxx_port_set_link,
3153		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3154	3551	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3155		- .port_set_speed = mv88e6185_port_set_speed,
	3552	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3156	3553	.port_tag_remap = mv88e6095_port_tag_remap,
3157	3554	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3158	3555	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -3162,8 +3559,8 @@
3162	3559	.port_pause_limit = mv88e6097_port_pause_limit,
3163	3560	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3164	3561	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3165		- .port_link_state = mv88e6352_port_link_state,
3166	3562	.port_get_cmode = mv88e6352_port_get_cmode,
	3563	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3167	3564	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3168	3565	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3169	3566	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3175,6 +3572,8 @@
3175	3572	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3176	3573	.pot_clear = mv88e6xxx_g2_pot_clear,
3177	3574	.reset = mv88e6352_g1_reset,
	3575	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3576	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3178	3577	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3179	3578	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3180	3579	.phylink_validate = mv88e6185_phylink_validate,
..	..	@@ -3191,10 +3590,10 @@
3191	3590	.phy_read = mv88e6xxx_g2_smi_phy_read,
3192	3591	.phy_write = mv88e6xxx_g2_smi_phy_write,
3193	3592	.port_set_link = mv88e6xxx_port_set_link,
3194		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3195	3593	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3196		- .port_set_speed = mv88e6352_port_set_speed,
	3594	+ .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3197	3595	.port_tag_remap = mv88e6095_port_tag_remap,
	3596	+ .port_set_policy = mv88e6352_port_set_policy,
3198	3597	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3199	3598	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3200	3599	.port_set_ether_type = mv88e6351_port_set_ether_type,
..	..	@@ -3203,8 +3602,8 @@
3203	3602	.port_pause_limit = mv88e6097_port_pause_limit,
3204	3603	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3205	3604	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3206		- .port_link_state = mv88e6352_port_link_state,
3207	3605	.port_get_cmode = mv88e6352_port_get_cmode,
	3606	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3208	3607	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3209	3608	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3210	3609	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3217,9 +3616,18 @@
3217	3616	.pot_clear = mv88e6xxx_g2_pot_clear,
3218	3617	.reset = mv88e6352_g1_reset,
3219	3618	.rmu_disable = mv88e6352_g1_rmu_disable,
	3619	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3620	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3220	3621	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3221	3622	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
	3623	+ .serdes_get_lane = mv88e6352_serdes_get_lane,
	3624	+ .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
	3625	+ .serdes_pcs_config = mv88e6352_serdes_pcs_config,
	3626	+ .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
	3627	+ .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3222	3628	.serdes_power = mv88e6352_serdes_power,
	3629	+ .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
	3630	+ .serdes_get_regs = mv88e6352_serdes_get_regs,
3223	3631	.gpio_ops = &mv88e6352_gpio_ops,
3224	3632	.phylink_validate = mv88e6352_phylink_validate,
3225	3633	};
..	..	@@ -3233,10 +3641,10 @@
3233	3641	.phy_read = mv88e6xxx_g2_smi_phy_read,
3234	3642	.phy_write = mv88e6xxx_g2_smi_phy_write,
3235	3643	.port_set_link = mv88e6xxx_port_set_link,
3236		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3237	3644	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3238		- .port_set_speed = mv88e6185_port_set_speed,
	3645	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3239	3646	.port_tag_remap = mv88e6095_port_tag_remap,
	3647	+ .port_set_policy = mv88e6352_port_set_policy,
3240	3648	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3241	3649	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3242	3650	.port_set_ether_type = mv88e6351_port_set_ether_type,
..	..	@@ -3245,8 +3653,8 @@
3245	3653	.port_pause_limit = mv88e6097_port_pause_limit,
3246	3654	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3247	3655	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3248		- .port_link_state = mv88e6352_port_link_state,
3249	3656	.port_get_cmode = mv88e6352_port_get_cmode,
	3657	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3250	3658	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3251	3659	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3252	3660	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3258,6 +3666,8 @@
3258	3666	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3259	3667	.pot_clear = mv88e6xxx_g2_pot_clear,
3260	3668	.reset = mv88e6352_g1_reset,
	3669	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3670	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3261	3671	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3262	3672	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3263	3673	.phylink_validate = mv88e6185_phylink_validate,
..	..	@@ -3274,10 +3684,10 @@
3274	3684	.phy_read = mv88e6xxx_g2_smi_phy_read,
3275	3685	.phy_write = mv88e6xxx_g2_smi_phy_write,
3276	3686	.port_set_link = mv88e6xxx_port_set_link,
3277		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3278	3687	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3279		- .port_set_speed = mv88e6352_port_set_speed,
	3688	+ .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3280	3689	.port_tag_remap = mv88e6095_port_tag_remap,
	3690	+ .port_set_policy = mv88e6352_port_set_policy,
3281	3691	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3282	3692	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3283	3693	.port_set_ether_type = mv88e6351_port_set_ether_type,
..	..	@@ -3286,8 +3696,8 @@
3286	3696	.port_pause_limit = mv88e6097_port_pause_limit,
3287	3697	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3288	3698	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3289		- .port_link_state = mv88e6352_port_link_state,
3290	3699	.port_get_cmode = mv88e6352_port_get_cmode,
	3700	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3291	3701	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3292	3702	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3293	3703	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3300,9 +3710,21 @@
3300	3710	.pot_clear = mv88e6xxx_g2_pot_clear,
3301	3711	.reset = mv88e6352_g1_reset,
3302	3712	.rmu_disable = mv88e6352_g1_rmu_disable,
	3713	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3714	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3303	3715	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3304	3716	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
	3717	+ .serdes_get_lane = mv88e6352_serdes_get_lane,
	3718	+ .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
	3719	+ .serdes_pcs_config = mv88e6352_serdes_pcs_config,
	3720	+ .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
	3721	+ .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3305	3722	.serdes_power = mv88e6352_serdes_power,
	3723	+ .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
	3724	+ .serdes_irq_enable = mv88e6352_serdes_irq_enable,
	3725	+ .serdes_irq_status = mv88e6352_serdes_irq_status,
	3726	+ .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
	3727	+ .serdes_get_regs = mv88e6352_serdes_get_regs,
3306	3728	.gpio_ops = &mv88e6352_gpio_ops,
3307	3729	.phylink_validate = mv88e6352_phylink_validate,
3308	3730	};
..	..	@@ -3315,15 +3737,14 @@
3315	3737	.phy_read = mv88e6185_phy_ppu_read,
3316	3738	.phy_write = mv88e6185_phy_ppu_write,
3317	3739	.port_set_link = mv88e6xxx_port_set_link,
3318		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3319		- .port_set_speed = mv88e6185_port_set_speed,
	3740	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3320	3741	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
3321	3742	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
3322	3743	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3323	3744	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
3324	3745	.port_set_pause = mv88e6185_port_set_pause,
3325		- .port_link_state = mv88e6185_port_link_state,
3326	3746	.port_get_cmode = mv88e6185_port_get_cmode,
	3747	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3327	3748	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3328	3749	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3329	3750	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3340,6 +3761,7 @@
3340	3761	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3341	3762	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3342	3763	.phylink_validate = mv88e6185_phylink_validate,
	3764	+ .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
3343	3765	};
3344	3766
3345	3767	static const struct mv88e6xxx_ops mv88e6190_ops = {
..	..	@@ -3352,18 +3774,21 @@
3352	3774	.phy_read = mv88e6xxx_g2_smi_phy_read,
3353	3775	.phy_write = mv88e6xxx_g2_smi_phy_write,
3354	3776	.port_set_link = mv88e6xxx_port_set_link,
3355		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3356	3777	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3357		- .port_set_speed = mv88e6390_port_set_speed,
	3778	+ .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
	3779	+ .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3358	3780	.port_tag_remap = mv88e6390_port_tag_remap,
	3781	+ .port_set_policy = mv88e6352_port_set_policy,
3359	3782	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3360	3783	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3361	3784	.port_set_ether_type = mv88e6351_port_set_ether_type,
	3785	+ .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3362	3786	.port_pause_limit = mv88e6390_port_pause_limit,
3363	3787	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3364	3788	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3365		- .port_link_state = mv88e6352_port_link_state,
3366	3789	.port_get_cmode = mv88e6352_port_get_cmode,
	3790	+ .port_set_cmode = mv88e6390_port_set_cmode,
	3791	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3367	3792	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3368	3793	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3369	3794	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3376,11 +3801,24 @@
3376	3801	.pot_clear = mv88e6xxx_g2_pot_clear,
3377	3802	.reset = mv88e6352_g1_reset,
3378	3803	.rmu_disable = mv88e6390_g1_rmu_disable,
	3804	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3805	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3379	3806	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3380	3807	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3381	3808	.serdes_power = mv88e6390_serdes_power,
3382		- .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3383		- .serdes_irq_free = mv88e6390_serdes_irq_free,
	3809	+ .serdes_get_lane = mv88e6390_serdes_get_lane,
	3810	+ /* Check status register pause & lpa register */
	3811	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	3812	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	3813	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	3814	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	3815	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	3816	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	3817	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
	3818	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	3819	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	3820	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	3821	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
3384	3822	.gpio_ops = &mv88e6352_gpio_ops,
3385	3823	.phylink_validate = mv88e6390_phylink_validate,
3386	3824	};
..	..	@@ -3395,18 +3833,21 @@
3395	3833	.phy_read = mv88e6xxx_g2_smi_phy_read,
3396	3834	.phy_write = mv88e6xxx_g2_smi_phy_write,
3397	3835	.port_set_link = mv88e6xxx_port_set_link,
3398		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3399	3836	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3400		- .port_set_speed = mv88e6390x_port_set_speed,
	3837	+ .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
	3838	+ .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3401	3839	.port_tag_remap = mv88e6390_port_tag_remap,
	3840	+ .port_set_policy = mv88e6352_port_set_policy,
3402	3841	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3403	3842	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3404	3843	.port_set_ether_type = mv88e6351_port_set_ether_type,
	3844	+ .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3405	3845	.port_pause_limit = mv88e6390_port_pause_limit,
3406	3846	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3407	3847	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3408		- .port_link_state = mv88e6352_port_link_state,
3409	3848	.port_get_cmode = mv88e6352_port_get_cmode,
	3849	+ .port_set_cmode = mv88e6390x_port_set_cmode,
	3850	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3410	3851	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3411	3852	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3412	3853	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3419,11 +3860,24 @@
3419	3860	.pot_clear = mv88e6xxx_g2_pot_clear,
3420	3861	.reset = mv88e6352_g1_reset,
3421	3862	.rmu_disable = mv88e6390_g1_rmu_disable,
	3863	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3864	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3422	3865	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3423	3866	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3424		- .serdes_power = mv88e6390x_serdes_power,
3425		- .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3426		- .serdes_irq_free = mv88e6390_serdes_irq_free,
	3867	+ .serdes_power = mv88e6390_serdes_power,
	3868	+ .serdes_get_lane = mv88e6390x_serdes_get_lane,
	3869	+ /* Check status register pause & lpa register */
	3870	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	3871	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	3872	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	3873	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	3874	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	3875	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	3876	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
	3877	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	3878	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	3879	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	3880	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
3427	3881	.gpio_ops = &mv88e6352_gpio_ops,
3428	3882	.phylink_validate = mv88e6390x_phylink_validate,
3429	3883	};
..	..	@@ -3438,9 +3892,9 @@
3438	3892	.phy_read = mv88e6xxx_g2_smi_phy_read,
3439	3893	.phy_write = mv88e6xxx_g2_smi_phy_write,
3440	3894	.port_set_link = mv88e6xxx_port_set_link,
3441		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3442	3895	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3443		- .port_set_speed = mv88e6390_port_set_speed,
	3896	+ .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
	3897	+ .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3444	3898	.port_tag_remap = mv88e6390_port_tag_remap,
3445	3899	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3446	3900	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -3448,8 +3902,9 @@
3448	3902	.port_pause_limit = mv88e6390_port_pause_limit,
3449	3903	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3450	3904	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3451		- .port_link_state = mv88e6352_port_link_state,
3452	3905	.port_get_cmode = mv88e6352_port_get_cmode,
	3906	+ .port_set_cmode = mv88e6390_port_set_cmode,
	3907	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3453	3908	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3454	3909	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3455	3910	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3462,11 +3917,24 @@
3462	3917	.pot_clear = mv88e6xxx_g2_pot_clear,
3463	3918	.reset = mv88e6352_g1_reset,
3464	3919	.rmu_disable = mv88e6390_g1_rmu_disable,
	3920	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3921	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3465	3922	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3466	3923	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3467	3924	.serdes_power = mv88e6390_serdes_power,
3468		- .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3469		- .serdes_irq_free = mv88e6390_serdes_irq_free,
	3925	+ .serdes_get_lane = mv88e6390_serdes_get_lane,
	3926	+ /* Check status register pause & lpa register */
	3927	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	3928	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	3929	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	3930	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	3931	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	3932	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	3933	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
	3934	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	3935	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	3936	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	3937	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
3470	3938	.avb_ops = &mv88e6390_avb_ops,
3471	3939	.ptp_ops = &mv88e6352_ptp_ops,
3472	3940	.phylink_validate = mv88e6390_phylink_validate,
..	..	@@ -3483,10 +3951,10 @@
3483	3951	.phy_read = mv88e6xxx_g2_smi_phy_read,
3484	3952	.phy_write = mv88e6xxx_g2_smi_phy_write,
3485	3953	.port_set_link = mv88e6xxx_port_set_link,
3486		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3487	3954	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3488		- .port_set_speed = mv88e6352_port_set_speed,
	3955	+ .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3489	3956	.port_tag_remap = mv88e6095_port_tag_remap,
	3957	+ .port_set_policy = mv88e6352_port_set_policy,
3490	3958	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3491	3959	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3492	3960	.port_set_ether_type = mv88e6351_port_set_ether_type,
..	..	@@ -3495,8 +3963,8 @@
3495	3963	.port_pause_limit = mv88e6097_port_pause_limit,
3496	3964	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3497	3965	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3498		- .port_link_state = mv88e6352_port_link_state,
3499	3966	.port_get_cmode = mv88e6352_port_get_cmode,
	3967	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3500	3968	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3501	3969	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3502	3970	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3509,13 +3977,63 @@
3509	3977	.pot_clear = mv88e6xxx_g2_pot_clear,
3510	3978	.reset = mv88e6352_g1_reset,
3511	3979	.rmu_disable = mv88e6352_g1_rmu_disable,
	3980	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	3981	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3512	3982	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3513	3983	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
	3984	+ .serdes_get_lane = mv88e6352_serdes_get_lane,
	3985	+ .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
	3986	+ .serdes_pcs_config = mv88e6352_serdes_pcs_config,
	3987	+ .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
	3988	+ .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3514	3989	.serdes_power = mv88e6352_serdes_power,
	3990	+ .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
	3991	+ .serdes_irq_enable = mv88e6352_serdes_irq_enable,
	3992	+ .serdes_irq_status = mv88e6352_serdes_irq_status,
	3993	+ .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
	3994	+ .serdes_get_regs = mv88e6352_serdes_get_regs,
3515	3995	.gpio_ops = &mv88e6352_gpio_ops,
3516	3996	.avb_ops = &mv88e6352_avb_ops,
3517	3997	.ptp_ops = &mv88e6352_ptp_ops,
3518	3998	.phylink_validate = mv88e6352_phylink_validate,
	3999	+};
	4000	+
	4001	+static const struct mv88e6xxx_ops mv88e6250_ops = {
	4002	+ /* MV88E6XXX_FAMILY_6250 */
	4003	+ .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
	4004	+ .ip_pri_map = mv88e6085_g1_ip_pri_map,
	4005	+ .irl_init_all = mv88e6352_g2_irl_init_all,
	4006	+ .get_eeprom = mv88e6xxx_g2_get_eeprom16,
	4007	+ .set_eeprom = mv88e6xxx_g2_set_eeprom16,
	4008	+ .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	4009	+ .phy_read = mv88e6xxx_g2_smi_phy_read,
	4010	+ .phy_write = mv88e6xxx_g2_smi_phy_write,
	4011	+ .port_set_link = mv88e6xxx_port_set_link,
	4012	+ .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
	4013	+ .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
	4014	+ .port_tag_remap = mv88e6095_port_tag_remap,
	4015	+ .port_set_frame_mode = mv88e6351_port_set_frame_mode,
	4016	+ .port_set_egress_floods = mv88e6352_port_set_egress_floods,
	4017	+ .port_set_ether_type = mv88e6351_port_set_ether_type,
	4018	+ .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
	4019	+ .port_pause_limit = mv88e6097_port_pause_limit,
	4020	+ .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	4021	+ .stats_snapshot = mv88e6320_g1_stats_snapshot,
	4022	+ .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
	4023	+ .stats_get_sset_count = mv88e6250_stats_get_sset_count,
	4024	+ .stats_get_strings = mv88e6250_stats_get_strings,
	4025	+ .stats_get_stats = mv88e6250_stats_get_stats,
	4026	+ .set_cpu_port = mv88e6095_g1_set_cpu_port,
	4027	+ .set_egress_port = mv88e6095_g1_set_egress_port,
	4028	+ .watchdog_ops = &mv88e6250_watchdog_ops,
	4029	+ .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
	4030	+ .pot_clear = mv88e6xxx_g2_pot_clear,
	4031	+ .reset = mv88e6250_g1_reset,
	4032	+ .vtu_getnext = mv88e6250_g1_vtu_getnext,
	4033	+ .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge,
	4034	+ .avb_ops = &mv88e6352_avb_ops,
	4035	+ .ptp_ops = &mv88e6250_ptp_ops,
	4036	+ .phylink_validate = mv88e6065_phylink_validate,
3519	4037	};
3520	4038
3521	4039	static const struct mv88e6xxx_ops mv88e6290_ops = {
..	..	@@ -3528,19 +4046,20 @@
3528	4046	.phy_read = mv88e6xxx_g2_smi_phy_read,
3529	4047	.phy_write = mv88e6xxx_g2_smi_phy_write,
3530	4048	.port_set_link = mv88e6xxx_port_set_link,
3531		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3532	4049	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3533		- .port_set_speed = mv88e6390_port_set_speed,
	4050	+ .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
	4051	+ .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3534	4052	.port_tag_remap = mv88e6390_port_tag_remap,
	4053	+ .port_set_policy = mv88e6352_port_set_policy,
3535	4054	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3536	4055	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3537	4056	.port_set_ether_type = mv88e6351_port_set_ether_type,
3538	4057	.port_pause_limit = mv88e6390_port_pause_limit,
3539		- .port_set_cmode = mv88e6390x_port_set_cmode,
3540	4058	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3541	4059	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3542		- .port_link_state = mv88e6352_port_link_state,
3543	4060	.port_get_cmode = mv88e6352_port_get_cmode,
	4061	+ .port_set_cmode = mv88e6390_port_set_cmode,
	4062	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3544	4063	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3545	4064	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3546	4065	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3553,11 +4072,24 @@
3553	4072	.pot_clear = mv88e6xxx_g2_pot_clear,
3554	4073	.reset = mv88e6352_g1_reset,
3555	4074	.rmu_disable = mv88e6390_g1_rmu_disable,
	4075	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	4076	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3556	4077	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3557	4078	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3558	4079	.serdes_power = mv88e6390_serdes_power,
3559		- .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3560		- .serdes_irq_free = mv88e6390_serdes_irq_free,
	4080	+ .serdes_get_lane = mv88e6390_serdes_get_lane,
	4081	+ /* Check status register pause & lpa register */
	4082	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	4083	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	4084	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	4085	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	4086	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	4087	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	4088	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
	4089	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	4090	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	4091	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	4092	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
3561	4093	.gpio_ops = &mv88e6352_gpio_ops,
3562	4094	.avb_ops = &mv88e6390_avb_ops,
3563	4095	.ptp_ops = &mv88e6352_ptp_ops,
..	..	@@ -3575,8 +4107,7 @@
3575	4107	.phy_read = mv88e6xxx_g2_smi_phy_read,
3576	4108	.phy_write = mv88e6xxx_g2_smi_phy_write,
3577	4109	.port_set_link = mv88e6xxx_port_set_link,
3578		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3579		- .port_set_speed = mv88e6185_port_set_speed,
	4110	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3580	4111	.port_tag_remap = mv88e6095_port_tag_remap,
3581	4112	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3582	4113	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -3586,8 +4117,8 @@
3586	4117	.port_pause_limit = mv88e6097_port_pause_limit,
3587	4118	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3588	4119	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3589		- .port_link_state = mv88e6352_port_link_state,
3590	4120	.port_get_cmode = mv88e6352_port_get_cmode,
	4121	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3591	4122	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3592	4123	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3593	4124	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3595,6 +4126,7 @@
3595	4126	.stats_get_stats = mv88e6320_stats_get_stats,
3596	4127	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3597	4128	.set_egress_port = mv88e6095_g1_set_egress_port,
	4129	+ .watchdog_ops = &mv88e6390_watchdog_ops,
3598	4130	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3599	4131	.pot_clear = mv88e6xxx_g2_pot_clear,
3600	4132	.reset = mv88e6352_g1_reset,
..	..	@@ -3617,8 +4149,7 @@
3617	4149	.phy_read = mv88e6xxx_g2_smi_phy_read,
3618	4150	.phy_write = mv88e6xxx_g2_smi_phy_write,
3619	4151	.port_set_link = mv88e6xxx_port_set_link,
3620		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3621		- .port_set_speed = mv88e6185_port_set_speed,
	4152	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3622	4153	.port_tag_remap = mv88e6095_port_tag_remap,
3623	4154	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3624	4155	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -3628,8 +4159,8 @@
3628	4159	.port_pause_limit = mv88e6097_port_pause_limit,
3629	4160	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3630	4161	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3631		- .port_link_state = mv88e6352_port_link_state,
3632	4162	.port_get_cmode = mv88e6352_port_get_cmode,
	4163	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3633	4164	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3634	4165	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3635	4166	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3637,6 +4168,7 @@
3637	4168	.stats_get_stats = mv88e6320_stats_get_stats,
3638	4169	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3639	4170	.set_egress_port = mv88e6095_g1_set_egress_port,
	4171	+ .watchdog_ops = &mv88e6390_watchdog_ops,
3640	4172	.reset = mv88e6352_g1_reset,
3641	4173	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3642	4174	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
..	..	@@ -3657,9 +4189,9 @@
3657	4189	.phy_read = mv88e6xxx_g2_smi_phy_read,
3658	4190	.phy_write = mv88e6xxx_g2_smi_phy_write,
3659	4191	.port_set_link = mv88e6xxx_port_set_link,
3660		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3661	4192	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3662		- .port_set_speed = mv88e6341_port_set_speed,
	4193	+ .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
	4194	+ .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3663	4195	.port_tag_remap = mv88e6095_port_tag_remap,
3664	4196	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3665	4197	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -3669,8 +4201,9 @@
3669	4201	.port_pause_limit = mv88e6097_port_pause_limit,
3670	4202	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3671	4203	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3672		- .port_link_state = mv88e6352_port_link_state,
3673	4204	.port_get_cmode = mv88e6352_port_get_cmode,
	4205	+ .port_set_cmode = mv88e6341_port_set_cmode,
	4206	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3674	4207	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3675	4208	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3676	4209	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3683,13 +4216,29 @@
3683	4216	.pot_clear = mv88e6xxx_g2_pot_clear,
3684	4217	.reset = mv88e6352_g1_reset,
3685	4218	.rmu_disable = mv88e6390_g1_rmu_disable,
	4219	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	4220	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3686	4221	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3687	4222	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3688		- .serdes_power = mv88e6341_serdes_power,
	4223	+ .serdes_power = mv88e6390_serdes_power,
	4224	+ .serdes_get_lane = mv88e6341_serdes_get_lane,
	4225	+ /* Check status register pause & lpa register */
	4226	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	4227	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	4228	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	4229	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	4230	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	4231	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	4232	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
3689	4233	.gpio_ops = &mv88e6352_gpio_ops,
3690	4234	.avb_ops = &mv88e6390_avb_ops,
3691	4235	.ptp_ops = &mv88e6352_ptp_ops,
3692		- .phylink_validate = mv88e6390_phylink_validate,
	4236	+ .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
	4237	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	4238	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	4239	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	4240	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
	4241	+ .phylink_validate = mv88e6341_phylink_validate,
3693	4242	};
3694	4243
3695	4244	static const struct mv88e6xxx_ops mv88e6350_ops = {
..	..	@@ -3701,9 +4250,8 @@
3701	4250	.phy_read = mv88e6xxx_g2_smi_phy_read,
3702	4251	.phy_write = mv88e6xxx_g2_smi_phy_write,
3703	4252	.port_set_link = mv88e6xxx_port_set_link,
3704		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3705	4253	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3706		- .port_set_speed = mv88e6185_port_set_speed,
	4254	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3707	4255	.port_tag_remap = mv88e6095_port_tag_remap,
3708	4256	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3709	4257	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
..	..	@@ -3713,8 +4261,8 @@
3713	4261	.port_pause_limit = mv88e6097_port_pause_limit,
3714	4262	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3715	4263	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3716		- .port_link_state = mv88e6352_port_link_state,
3717	4264	.port_get_cmode = mv88e6352_port_get_cmode,
	4265	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3718	4266	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3719	4267	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3720	4268	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3726,6 +4274,8 @@
3726	4274	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3727	4275	.pot_clear = mv88e6xxx_g2_pot_clear,
3728	4276	.reset = mv88e6352_g1_reset,
	4277	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	4278	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3729	4279	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3730	4280	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3731	4281	.phylink_validate = mv88e6185_phylink_validate,
..	..	@@ -3740,10 +4290,10 @@
3740	4290	.phy_read = mv88e6xxx_g2_smi_phy_read,
3741	4291	.phy_write = mv88e6xxx_g2_smi_phy_write,
3742	4292	.port_set_link = mv88e6xxx_port_set_link,
3743		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3744	4293	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3745		- .port_set_speed = mv88e6185_port_set_speed,
	4294	+ .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
3746	4295	.port_tag_remap = mv88e6095_port_tag_remap,
	4296	+ .port_set_policy = mv88e6352_port_set_policy,
3747	4297	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3748	4298	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3749	4299	.port_set_ether_type = mv88e6351_port_set_ether_type,
..	..	@@ -3752,8 +4302,8 @@
3752	4302	.port_pause_limit = mv88e6097_port_pause_limit,
3753	4303	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3754	4304	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3755		- .port_link_state = mv88e6352_port_link_state,
3756	4305	.port_get_cmode = mv88e6352_port_get_cmode,
	4306	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3757	4307	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3758	4308	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3759	4309	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3765,7 +4315,8 @@
3765	4315	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3766	4316	.pot_clear = mv88e6xxx_g2_pot_clear,
3767	4317	.reset = mv88e6352_g1_reset,
3768		- .rmu_disable = mv88e6390_g1_rmu_disable,
	4318	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	4319	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3769	4320	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3770	4321	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3771	4322	.avb_ops = &mv88e6352_avb_ops,
..	..	@@ -3784,10 +4335,10 @@
3784	4335	.phy_read = mv88e6xxx_g2_smi_phy_read,
3785	4336	.phy_write = mv88e6xxx_g2_smi_phy_write,
3786	4337	.port_set_link = mv88e6xxx_port_set_link,
3787		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3788	4338	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3789		- .port_set_speed = mv88e6352_port_set_speed,
	4339	+ .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
3790	4340	.port_tag_remap = mv88e6095_port_tag_remap,
	4341	+ .port_set_policy = mv88e6352_port_set_policy,
3791	4342	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3792	4343	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3793	4344	.port_set_ether_type = mv88e6351_port_set_ether_type,
..	..	@@ -3796,8 +4347,8 @@
3796	4347	.port_pause_limit = mv88e6097_port_pause_limit,
3797	4348	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3798	4349	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3799		- .port_link_state = mv88e6352_port_link_state,
3800	4350	.port_get_cmode = mv88e6352_port_get_cmode,
	4351	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3801	4352	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3802	4353	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3803	4354	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
..	..	@@ -3810,15 +4361,27 @@
3810	4361	.pot_clear = mv88e6xxx_g2_pot_clear,
3811	4362	.reset = mv88e6352_g1_reset,
3812	4363	.rmu_disable = mv88e6352_g1_rmu_disable,
	4364	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	4365	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3813	4366	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3814	4367	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
	4368	+ .serdes_get_lane = mv88e6352_serdes_get_lane,
	4369	+ .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
	4370	+ .serdes_pcs_config = mv88e6352_serdes_pcs_config,
	4371	+ .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
	4372	+ .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
3815	4373	.serdes_power = mv88e6352_serdes_power,
	4374	+ .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
	4375	+ .serdes_irq_enable = mv88e6352_serdes_irq_enable,
	4376	+ .serdes_irq_status = mv88e6352_serdes_irq_status,
3816	4377	.gpio_ops = &mv88e6352_gpio_ops,
3817	4378	.avb_ops = &mv88e6352_avb_ops,
3818	4379	.ptp_ops = &mv88e6352_ptp_ops,
3819	4380	.serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
3820	4381	.serdes_get_strings = mv88e6352_serdes_get_strings,
3821	4382	.serdes_get_stats = mv88e6352_serdes_get_stats,
	4383	+ .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
	4384	+ .serdes_get_regs = mv88e6352_serdes_get_regs,
3822	4385	.phylink_validate = mv88e6352_phylink_validate,
3823	4386	};
3824	4387
..	..	@@ -3832,21 +4395,22 @@
3832	4395	.phy_read = mv88e6xxx_g2_smi_phy_read,
3833	4396	.phy_write = mv88e6xxx_g2_smi_phy_write,
3834	4397	.port_set_link = mv88e6xxx_port_set_link,
3835		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3836	4398	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3837		- .port_set_speed = mv88e6390_port_set_speed,
	4399	+ .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
	4400	+ .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3838	4401	.port_tag_remap = mv88e6390_port_tag_remap,
	4402	+ .port_set_policy = mv88e6352_port_set_policy,
3839	4403	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3840	4404	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3841	4405	.port_set_ether_type = mv88e6351_port_set_ether_type,
3842	4406	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3843	4407	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3844	4408	.port_pause_limit = mv88e6390_port_pause_limit,
3845		- .port_set_cmode = mv88e6390x_port_set_cmode,
3846	4409	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3847	4410	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3848		- .port_link_state = mv88e6352_port_link_state,
3849	4411	.port_get_cmode = mv88e6352_port_get_cmode,
	4412	+ .port_set_cmode = mv88e6390_port_set_cmode,
	4413	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3850	4414	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3851	4415	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3852	4416	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3859,14 +4423,28 @@
3859	4423	.pot_clear = mv88e6xxx_g2_pot_clear,
3860	4424	.reset = mv88e6352_g1_reset,
3861	4425	.rmu_disable = mv88e6390_g1_rmu_disable,
	4426	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	4427	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3862	4428	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3863	4429	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3864	4430	.serdes_power = mv88e6390_serdes_power,
3865		- .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3866		- .serdes_irq_free = mv88e6390_serdes_irq_free,
	4431	+ .serdes_get_lane = mv88e6390_serdes_get_lane,
	4432	+ /* Check status register pause & lpa register */
	4433	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	4434	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	4435	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	4436	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	4437	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	4438	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	4439	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
3867	4440	.gpio_ops = &mv88e6352_gpio_ops,
3868	4441	.avb_ops = &mv88e6390_avb_ops,
3869	4442	.ptp_ops = &mv88e6352_ptp_ops,
	4443	+ .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
	4444	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	4445	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	4446	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	4447	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
3870	4448	.phylink_validate = mv88e6390_phylink_validate,
3871	4449	};
3872	4450
..	..	@@ -3880,21 +4458,22 @@
3880	4458	.phy_read = mv88e6xxx_g2_smi_phy_read,
3881	4459	.phy_write = mv88e6xxx_g2_smi_phy_write,
3882	4460	.port_set_link = mv88e6xxx_port_set_link,
3883		- .port_set_duplex = mv88e6xxx_port_set_duplex,
3884	4461	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3885		- .port_set_speed = mv88e6390x_port_set_speed,
	4462	+ .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
	4463	+ .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3886	4464	.port_tag_remap = mv88e6390_port_tag_remap,
	4465	+ .port_set_policy = mv88e6352_port_set_policy,
3887	4466	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3888	4467	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3889	4468	.port_set_ether_type = mv88e6351_port_set_ether_type,
3890	4469	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3891	4470	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3892	4471	.port_pause_limit = mv88e6390_port_pause_limit,
3893		- .port_set_cmode = mv88e6390x_port_set_cmode,
3894	4472	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3895	4473	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3896		- .port_link_state = mv88e6352_port_link_state,
3897	4474	.port_get_cmode = mv88e6352_port_get_cmode,
	4475	+ .port_set_cmode = mv88e6390x_port_set_cmode,
	4476	+ .port_setup_message_port = mv88e6xxx_setup_message_port,
3898	4477	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3899	4478	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3900	4479	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
..	..	@@ -3907,11 +4486,24 @@
3907	4486	.pot_clear = mv88e6xxx_g2_pot_clear,
3908	4487	.reset = mv88e6352_g1_reset,
3909	4488	.rmu_disable = mv88e6390_g1_rmu_disable,
	4489	+ .atu_get_hash = mv88e6165_g1_atu_get_hash,
	4490	+ .atu_set_hash = mv88e6165_g1_atu_set_hash,
3910	4491	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3911	4492	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3912		- .serdes_power = mv88e6390x_serdes_power,
3913		- .serdes_irq_setup = mv88e6390_serdes_irq_setup,
3914		- .serdes_irq_free = mv88e6390_serdes_irq_free,
	4493	+ .serdes_power = mv88e6390_serdes_power,
	4494	+ .serdes_get_lane = mv88e6390x_serdes_get_lane,
	4495	+ .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
	4496	+ .serdes_pcs_config = mv88e6390_serdes_pcs_config,
	4497	+ .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
	4498	+ .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
	4499	+ .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
	4500	+ .serdes_irq_enable = mv88e6390_serdes_irq_enable,
	4501	+ .serdes_irq_status = mv88e6390_serdes_irq_status,
	4502	+ .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
	4503	+ .serdes_get_strings = mv88e6390_serdes_get_strings,
	4504	+ .serdes_get_stats = mv88e6390_serdes_get_stats,
	4505	+ .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
	4506	+ .serdes_get_regs = mv88e6390_serdes_get_regs,
3915	4507	.gpio_ops = &mv88e6352_gpio_ops,
3916	4508	.avb_ops = &mv88e6390_avb_ops,
3917	4509	.ptp_ops = &mv88e6352_ptp_ops,
..	..	@@ -3924,6 +4516,7 @@
3924	4516	.family = MV88E6XXX_FAMILY_6097,
3925	4517	.name = "Marvell 88E6085",
3926	4518	.num_databases = 4096,
	4519	+ .num_macs = 8192,
3927	4520	.num_ports = 10,
3928	4521	.num_internal_phys = 5,
3929	4522	.max_vid = 4095,
..	..	@@ -3946,6 +4539,7 @@
3946	4539	.family = MV88E6XXX_FAMILY_6095,
3947	4540	.name = "Marvell 88E6095/88E6095F",
3948	4541	.num_databases = 256,
	4542	+ .num_macs = 8192,
3949	4543	.num_ports = 11,
3950	4544	.num_internal_phys = 0,
3951	4545	.max_vid = 4095,
..	..	@@ -3966,6 +4560,7 @@
3966	4560	.family = MV88E6XXX_FAMILY_6097,
3967	4561	.name = "Marvell 88E6097/88E6097F",
3968	4562	.num_databases = 4096,
	4563	+ .num_macs = 8192,
3969	4564	.num_ports = 11,
3970	4565	.num_internal_phys = 8,
3971	4566	.max_vid = 4095,
..	..	@@ -3988,6 +4583,7 @@
3988	4583	.family = MV88E6XXX_FAMILY_6165,
3989	4584	.name = "Marvell 88E6123",
3990	4585	.num_databases = 4096,
	4586	+ .num_macs = 1024,
3991	4587	.num_ports = 3,
3992	4588	.num_internal_phys = 5,
3993	4589	.max_vid = 4095,
..	..	@@ -4010,6 +4606,7 @@
4010	4606	.family = MV88E6XXX_FAMILY_6185,
4011	4607	.name = "Marvell 88E6131",
4012	4608	.num_databases = 256,
	4609	+ .num_macs = 8192,
4013	4610	.num_ports = 8,
4014	4611	.num_internal_phys = 0,
4015	4612	.max_vid = 4095,
..	..	@@ -4030,6 +4627,7 @@
4030	4627	.family = MV88E6XXX_FAMILY_6341,
4031	4628	.name = "Marvell 88E6141",
4032	4629	.num_databases = 4096,
	4630	+ .num_macs = 2048,
4033	4631	.num_ports = 6,
4034	4632	.num_internal_phys = 5,
4035	4633	.num_gpio = 11,
..	..	@@ -4053,6 +4651,7 @@
4053	4651	.family = MV88E6XXX_FAMILY_6165,
4054	4652	.name = "Marvell 88E6161",
4055	4653	.num_databases = 4096,
	4654	+ .num_macs = 1024,
4056	4655	.num_ports = 6,
4057	4656	.num_internal_phys = 5,
4058	4657	.max_vid = 4095,
..	..	@@ -4076,6 +4675,7 @@
4076	4675	.family = MV88E6XXX_FAMILY_6165,
4077	4676	.name = "Marvell 88E6165",
4078	4677	.num_databases = 4096,
	4678	+ .num_macs = 8192,
4079	4679	.num_ports = 6,
4080	4680	.num_internal_phys = 0,
4081	4681	.max_vid = 4095,
..	..	@@ -4099,6 +4699,7 @@
4099	4699	.family = MV88E6XXX_FAMILY_6351,
4100	4700	.name = "Marvell 88E6171",
4101	4701	.num_databases = 4096,
	4702	+ .num_macs = 8192,
4102	4703	.num_ports = 7,
4103	4704	.num_internal_phys = 5,
4104	4705	.max_vid = 4095,
..	..	@@ -4121,6 +4722,7 @@
4121	4722	.family = MV88E6XXX_FAMILY_6352,
4122	4723	.name = "Marvell 88E6172",
4123	4724	.num_databases = 4096,
	4725	+ .num_macs = 8192,
4124	4726	.num_ports = 7,
4125	4727	.num_internal_phys = 5,
4126	4728	.num_gpio = 15,
..	..	@@ -4144,6 +4746,7 @@
4144	4746	.family = MV88E6XXX_FAMILY_6351,
4145	4747	.name = "Marvell 88E6175",
4146	4748	.num_databases = 4096,
	4749	+ .num_macs = 8192,
4147	4750	.num_ports = 7,
4148	4751	.num_internal_phys = 5,
4149	4752	.max_vid = 4095,
..	..	@@ -4166,6 +4769,7 @@
4166	4769	.family = MV88E6XXX_FAMILY_6352,
4167	4770	.name = "Marvell 88E6176",
4168	4771	.num_databases = 4096,
	4772	+ .num_macs = 8192,
4169	4773	.num_ports = 7,
4170	4774	.num_internal_phys = 5,
4171	4775	.num_gpio = 15,
..	..	@@ -4189,6 +4793,7 @@
4189	4793	.family = MV88E6XXX_FAMILY_6185,
4190	4794	.name = "Marvell 88E6185",
4191	4795	.num_databases = 256,
	4796	+ .num_macs = 8192,
4192	4797	.num_ports = 10,
4193	4798	.num_internal_phys = 0,
4194	4799	.max_vid = 4095,
..	..	@@ -4209,6 +4814,7 @@
4209	4814	.family = MV88E6XXX_FAMILY_6390,
4210	4815	.name = "Marvell 88E6190",
4211	4816	.num_databases = 4096,
	4817	+ .num_macs = 16384,
4212	4818	.num_ports = 11, /* 10 + Z80 */
4213	4819	.num_internal_phys = 9,
4214	4820	.num_gpio = 16,
..	..	@@ -4232,6 +4838,7 @@
4232	4838	.family = MV88E6XXX_FAMILY_6390,
4233	4839	.name = "Marvell 88E6190X",
4234	4840	.num_databases = 4096,
	4841	+ .num_macs = 16384,
4235	4842	.num_ports = 11, /* 10 + Z80 */
4236	4843	.num_internal_phys = 9,
4237	4844	.num_gpio = 16,
..	..	@@ -4255,6 +4862,7 @@
4255	4862	.family = MV88E6XXX_FAMILY_6390,
4256	4863	.name = "Marvell 88E6191",
4257	4864	.num_databases = 4096,
	4865	+ .num_macs = 16384,
4258	4866	.num_ports = 11, /* 10 + Z80 */
4259	4867	.num_internal_phys = 9,
4260	4868	.max_vid = 8191,
..	..	@@ -4273,11 +4881,39 @@
4273	4881	.ops = &mv88e6191_ops,
4274	4882	},
4275	4883
	4884	+ [MV88E6220] = {
	4885	+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
	4886	+ .family = MV88E6XXX_FAMILY_6250,
	4887	+ .name = "Marvell 88E6220",
	4888	+ .num_databases = 64,
	4889	+
	4890	+ /* Ports 2-4 are not routed to pins
	4891	+ * => usable ports 0, 1, 5, 6
	4892	+ */
	4893	+ .num_ports = 7,
	4894	+ .num_internal_phys = 2,
	4895	+ .invalid_port_mask = BIT(2) \| BIT(3) \| BIT(4),
	4896	+ .max_vid = 4095,
	4897	+ .port_base_addr = 0x08,
	4898	+ .phy_base_addr = 0x00,
	4899	+ .global1_addr = 0x0f,
	4900	+ .global2_addr = 0x07,
	4901	+ .age_time_coeff = 15000,
	4902	+ .g1_irqs = 9,
	4903	+ .g2_irqs = 10,
	4904	+ .atu_move_port_mask = 0xf,
	4905	+ .dual_chip = true,
	4906	+ .tag_protocol = DSA_TAG_PROTO_DSA,
	4907	+ .ptp_support = true,
	4908	+ .ops = &mv88e6250_ops,
	4909	+ },
	4910	+
4276	4911	[MV88E6240] = {
4277	4912	.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
4278	4913	.family = MV88E6XXX_FAMILY_6352,
4279	4914	.name = "Marvell 88E6240",
4280	4915	.num_databases = 4096,
	4916	+ .num_macs = 8192,
4281	4917	.num_ports = 7,
4282	4918	.num_internal_phys = 5,
4283	4919	.num_gpio = 15,
..	..	@@ -4295,6 +4931,28 @@
4295	4931	.tag_protocol = DSA_TAG_PROTO_EDSA,
4296	4932	.ptp_support = true,
4297	4933	.ops = &mv88e6240_ops,
	4934	+ },
	4935	+
	4936	+ [MV88E6250] = {
	4937	+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
	4938	+ .family = MV88E6XXX_FAMILY_6250,
	4939	+ .name = "Marvell 88E6250",
	4940	+ .num_databases = 64,
	4941	+ .num_ports = 7,
	4942	+ .num_internal_phys = 5,
	4943	+ .max_vid = 4095,
	4944	+ .port_base_addr = 0x08,
	4945	+ .phy_base_addr = 0x00,
	4946	+ .global1_addr = 0x0f,
	4947	+ .global2_addr = 0x07,
	4948	+ .age_time_coeff = 15000,
	4949	+ .g1_irqs = 9,
	4950	+ .g2_irqs = 10,
	4951	+ .atu_move_port_mask = 0xf,
	4952	+ .dual_chip = true,
	4953	+ .tag_protocol = DSA_TAG_PROTO_DSA,
	4954	+ .ptp_support = true,
	4955	+ .ops = &mv88e6250_ops,
4298	4956	},
4299	4957
4300	4958	[MV88E6290] = {
..	..	@@ -4326,6 +4984,7 @@
4326	4984	.family = MV88E6XXX_FAMILY_6320,
4327	4985	.name = "Marvell 88E6320",
4328	4986	.num_databases = 4096,
	4987	+ .num_macs = 8192,
4329	4988	.num_ports = 7,
4330	4989	.num_internal_phys = 5,
4331	4990	.num_gpio = 15,
..	..	@@ -4350,6 +5009,7 @@
4350	5009	.family = MV88E6XXX_FAMILY_6320,
4351	5010	.name = "Marvell 88E6321",
4352	5011	.num_databases = 4096,
	5012	+ .num_macs = 8192,
4353	5013	.num_ports = 7,
4354	5014	.num_internal_phys = 5,
4355	5015	.num_gpio = 15,
..	..	@@ -4373,6 +5033,7 @@
4373	5033	.family = MV88E6XXX_FAMILY_6341,
4374	5034	.name = "Marvell 88E6341",
4375	5035	.num_databases = 4096,
	5036	+ .num_macs = 2048,
4376	5037	.num_internal_phys = 5,
4377	5038	.num_ports = 6,
4378	5039	.num_gpio = 11,
..	..	@@ -4397,6 +5058,7 @@
4397	5058	.family = MV88E6XXX_FAMILY_6351,
4398	5059	.name = "Marvell 88E6350",
4399	5060	.num_databases = 4096,
	5061	+ .num_macs = 8192,
4400	5062	.num_ports = 7,
4401	5063	.num_internal_phys = 5,
4402	5064	.max_vid = 4095,
..	..	@@ -4419,6 +5081,7 @@
4419	5081	.family = MV88E6XXX_FAMILY_6351,
4420	5082	.name = "Marvell 88E6351",
4421	5083	.num_databases = 4096,
	5084	+ .num_macs = 8192,
4422	5085	.num_ports = 7,
4423	5086	.num_internal_phys = 5,
4424	5087	.max_vid = 4095,
..	..	@@ -4441,6 +5104,7 @@
4441	5104	.family = MV88E6XXX_FAMILY_6352,
4442	5105	.name = "Marvell 88E6352",
4443	5106	.num_databases = 4096,
	5107	+ .num_macs = 8192,
4444	5108	.num_ports = 7,
4445	5109	.num_internal_phys = 5,
4446	5110	.num_gpio = 15,
..	..	@@ -4464,6 +5128,7 @@
4464	5128	.family = MV88E6XXX_FAMILY_6390,
4465	5129	.name = "Marvell 88E6390",
4466	5130	.num_databases = 4096,
	5131	+ .num_macs = 16384,
4467	5132	.num_ports = 11, /* 10 + Z80 */
4468	5133	.num_internal_phys = 9,
4469	5134	.num_gpio = 16,
..	..	@@ -4487,6 +5152,7 @@
4487	5152	.family = MV88E6XXX_FAMILY_6390,
4488	5153	.name = "Marvell 88E6390X",
4489	5154	.num_databases = 4096,
	5155	+ .num_macs = 16384,
4490	5156	.num_ports = 11, /* 10 + Z80 */
4491	5157	.num_internal_phys = 9,
4492	5158	.num_gpio = 16,
..	..	@@ -4525,9 +5191,9 @@
4525	5191	u16 id;
4526	5192	int err;
4527	5193
4528		- mutex_lock(&chip->reg_lock);
	5194	+ mv88e6xxx_reg_lock(chip);
4529	5195	err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
4530		- mutex_unlock(&chip->reg_lock);
	5196	+ mv88e6xxx_reg_unlock(chip);
4531	5197	if (err)
4532	5198	return err;
4533	5199
..	..	@@ -4563,93 +5229,19 @@
4563	5229
4564	5230	mutex_init(&chip->reg_lock);
4565	5231	INIT_LIST_HEAD(&chip->mdios);
	5232	+ idr_init(&chip->policies);
4566	5233
4567	5234	return chip;
4568	5235	}
4569	5236
4570		-static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4571		- struct mii_bus *bus, int sw_addr)
4572		-{
4573		- if (sw_addr == 0)
4574		- chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4575		- else if (chip->info->multi_chip)
4576		- chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4577		- else
4578		- return -EINVAL;
4579		-
4580		- chip->bus = bus;
4581		- chip->sw_addr = sw_addr;
4582		-
4583		- return 0;
4584		-}
4585		-
4586		-static void mv88e6xxx_ports_cmode_init(struct mv88e6xxx_chip *chip)
4587		-{
4588		- int i;
4589		-
4590		- for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
4591		- chip->ports[i].cmode = MV88E6XXX_PORT_STS_CMODE_INVALID;
4592		-}
4593		-
4594	5237	static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
4595		- int port)
	5238	+ int port,
	5239	+ enum dsa_tag_protocol m)
4596	5240	{
4597	5241	struct mv88e6xxx_chip *chip = ds->priv;
4598	5242
4599	5243	return chip->info->tag_protocol;
4600	5244	}
4601		-
4602		-#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4603		-static const char mv88e6xxx_drv_probe(struct device dsa_dev,
4604		- struct device *host_dev, int sw_addr,
4605		- void **priv)
4606		-{
4607		- struct mv88e6xxx_chip *chip;
4608		- struct mii_bus *bus;
4609		- int err;
4610		-
4611		- bus = dsa_host_dev_to_mii_bus(host_dev);
4612		- if (!bus)
4613		- return NULL;
4614		-
4615		- chip = mv88e6xxx_alloc_chip(dsa_dev);
4616		- if (!chip)
4617		- return NULL;
4618		-
4619		- /* Legacy SMI probing will only support chips similar to 88E6085 */
4620		- chip->info = &mv88e6xxx_table[MV88E6085];
4621		-
4622		- err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4623		- if (err)
4624		- goto free;
4625		-
4626		- err = mv88e6xxx_detect(chip);
4627		- if (err)
4628		- goto free;
4629		-
4630		- mv88e6xxx_ports_cmode_init(chip);
4631		-
4632		- mutex_lock(&chip->reg_lock);
4633		- err = mv88e6xxx_switch_reset(chip);
4634		- mutex_unlock(&chip->reg_lock);
4635		- if (err)
4636		- goto free;
4637		-
4638		- mv88e6xxx_phy_init(chip);
4639		-
4640		- err = mv88e6xxx_mdios_register(chip, NULL);
4641		- if (err)
4642		- goto free;
4643		-
4644		- *priv = chip;
4645		-
4646		- return chip->info->name;
4647		-free:
4648		- devm_kfree(dsa_dev, chip);
4649		-
4650		- return NULL;
4651		-}
4652		-#endif
4653	5245
4654	5246	static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4655	5247	const struct switchdev_obj_port_mdb *mdb)
..	..	@@ -4666,12 +5258,12 @@
4666	5258	{
4667	5259	struct mv88e6xxx_chip *chip = ds->priv;
4668	5260
4669		- mutex_lock(&chip->reg_lock);
	5261	+ mv88e6xxx_reg_lock(chip);
4670	5262	if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4671	5263	MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4672	5264	dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
4673	5265	port);
4674		- mutex_unlock(&chip->reg_lock);
	5266	+ mv88e6xxx_reg_unlock(chip);
4675	5267	}
4676	5268
4677	5269	static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
..	..	@@ -4680,24 +5272,111 @@
4680	5272	struct mv88e6xxx_chip *chip = ds->priv;
4681	5273	int err;
4682	5274
	5275	+ mv88e6xxx_reg_lock(chip);
	5276	+ err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
	5277	+ mv88e6xxx_reg_unlock(chip);
	5278	+
	5279	+ return err;
	5280	+}
	5281	+
	5282	+static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
	5283	+ struct dsa_mall_mirror_tc_entry *mirror,
	5284	+ bool ingress)
	5285	+{
	5286	+ enum mv88e6xxx_egress_direction direction = ingress ?
	5287	+ MV88E6XXX_EGRESS_DIR_INGRESS :
	5288	+ MV88E6XXX_EGRESS_DIR_EGRESS;
	5289	+ struct mv88e6xxx_chip *chip = ds->priv;
	5290	+ bool other_mirrors = false;
	5291	+ int i;
	5292	+ int err;
	5293	+
	5294	+ if (!chip->info->ops->set_egress_port)
	5295	+ return -EOPNOTSUPP;
	5296	+
4683	5297	mutex_lock(&chip->reg_lock);
4684		- err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4685		- MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
	5298	+ if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
	5299	+ mirror->to_local_port) {
	5300	+ for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
	5301	+ other_mirrors \|= ingress ?
	5302	+ chip->ports[i].mirror_ingress :
	5303	+ chip->ports[i].mirror_egress;
	5304	+
	5305	+ /* Can't change egress port when other mirror is active */
	5306	+ if (other_mirrors) {
	5307	+ err = -EBUSY;
	5308	+ goto out;
	5309	+ }
	5310	+
	5311	+ err = chip->info->ops->set_egress_port(chip,
	5312	+ direction,
	5313	+ mirror->to_local_port);
	5314	+ if (err)
	5315	+ goto out;
	5316	+ }
	5317	+
	5318	+ err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
	5319	+out:
4686	5320	mutex_unlock(&chip->reg_lock);
4687	5321
4688	5322	return err;
4689	5323	}
4690	5324
	5325	+static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
	5326	+ struct dsa_mall_mirror_tc_entry *mirror)
	5327	+{
	5328	+ enum mv88e6xxx_egress_direction direction = mirror->ingress ?
	5329	+ MV88E6XXX_EGRESS_DIR_INGRESS :
	5330	+ MV88E6XXX_EGRESS_DIR_EGRESS;
	5331	+ struct mv88e6xxx_chip *chip = ds->priv;
	5332	+ bool other_mirrors = false;
	5333	+ int i;
	5334	+
	5335	+ mutex_lock(&chip->reg_lock);
	5336	+ if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
	5337	+ dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
	5338	+
	5339	+ for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
	5340	+ other_mirrors \|= mirror->ingress ?
	5341	+ chip->ports[i].mirror_ingress :
	5342	+ chip->ports[i].mirror_egress;
	5343	+
	5344	+ /* Reset egress port when no other mirror is active */
	5345	+ if (!other_mirrors) {
	5346	+ if (chip->info->ops->set_egress_port(chip,
	5347	+ direction,
	5348	+ dsa_upstream_port(ds,
	5349	+ port)))
	5350	+ dev_err(ds->dev, "failed to set egress port\n");
	5351	+ }
	5352	+
	5353	+ mutex_unlock(&chip->reg_lock);
	5354	+}
	5355	+
	5356	+static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
	5357	+ bool unicast, bool multicast)
	5358	+{
	5359	+ struct mv88e6xxx_chip *chip = ds->priv;
	5360	+ int err = -EOPNOTSUPP;
	5361	+
	5362	+ mv88e6xxx_reg_lock(chip);
	5363	+ if (chip->info->ops->port_set_egress_floods)
	5364	+ err = chip->info->ops->port_set_egress_floods(chip, port,
	5365	+ unicast,
	5366	+ multicast);
	5367	+ mv88e6xxx_reg_unlock(chip);
	5368	+
	5369	+ return err;
	5370	+}
	5371	+
4691	5372	static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4692		-#if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4693		- .probe = mv88e6xxx_drv_probe,
4694		-#endif
4695	5373	.get_tag_protocol = mv88e6xxx_get_tag_protocol,
4696	5374	.setup = mv88e6xxx_setup,
4697		- .adjust_link = mv88e6xxx_adjust_link,
	5375	+ .teardown = mv88e6xxx_teardown,
4698	5376	.phylink_validate = mv88e6xxx_validate,
4699		- .phylink_mac_link_state = mv88e6xxx_link_state,
	5377	+ .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
4700	5378	.phylink_mac_config = mv88e6xxx_mac_config,
	5379	+ .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
4701	5380	.phylink_mac_link_down = mv88e6xxx_mac_link_down,
4702	5381	.phylink_mac_link_up = mv88e6xxx_mac_link_up,
4703	5382	.get_strings = mv88e6xxx_get_strings,
..	..	@@ -4705,6 +5384,8 @@
4705	5384	.get_sset_count = mv88e6xxx_get_sset_count,
4706	5385	.port_enable = mv88e6xxx_port_enable,
4707	5386	.port_disable = mv88e6xxx_port_disable,
	5387	+ .port_max_mtu = mv88e6xxx_get_max_mtu,
	5388	+ .port_change_mtu = mv88e6xxx_change_mtu,
4708	5389	.get_mac_eee = mv88e6xxx_get_mac_eee,
4709	5390	.set_mac_eee = mv88e6xxx_set_mac_eee,
4710	5391	.get_eeprom_len = mv88e6xxx_get_eeprom_len,
..	..	@@ -4712,9 +5393,12 @@
4712	5393	.set_eeprom = mv88e6xxx_set_eeprom,
4713	5394	.get_regs_len = mv88e6xxx_get_regs_len,
4714	5395	.get_regs = mv88e6xxx_get_regs,
	5396	+ .get_rxnfc = mv88e6xxx_get_rxnfc,
	5397	+ .set_rxnfc = mv88e6xxx_set_rxnfc,
4715	5398	.set_ageing_time = mv88e6xxx_set_ageing_time,
4716	5399	.port_bridge_join = mv88e6xxx_port_bridge_join,
4717	5400	.port_bridge_leave = mv88e6xxx_port_bridge_leave,
	5401	+ .port_egress_floods = mv88e6xxx_port_egress_floods,
4718	5402	.port_stp_state_set = mv88e6xxx_port_stp_state_set,
4719	5403	.port_fast_age = mv88e6xxx_port_fast_age,
4720	5404	.port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
..	..	@@ -4727,6 +5411,8 @@
4727	5411	.port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4728	5412	.port_mdb_add = mv88e6xxx_port_mdb_add,
4729	5413	.port_mdb_del = mv88e6xxx_port_mdb_del,
	5414	+ .port_mirror_add = mv88e6xxx_port_mirror_add,
	5415	+ .port_mirror_del = mv88e6xxx_port_mirror_del,
4730	5416	.crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
4731	5417	.crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
4732	5418	.port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
..	..	@@ -4734,10 +5420,9 @@
4734	5420	.port_txtstamp = mv88e6xxx_port_txtstamp,
4735	5421	.port_rxtstamp = mv88e6xxx_port_rxtstamp,
4736	5422	.get_ts_info = mv88e6xxx_get_ts_info,
4737		-};
4738		-
4739		-static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4740		- .ops = &mv88e6xxx_switch_ops,
	5423	+ .devlink_param_get = mv88e6xxx_devlink_param_get,
	5424	+ .devlink_param_set = mv88e6xxx_devlink_param_set,
	5425	+ .devlink_info_get = mv88e6xxx_devlink_info_get,
4741	5426	};
4742	5427
4743	5428	static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
..	..	@@ -4745,10 +5430,12 @@
4745	5430	struct device *dev = chip->dev;
4746	5431	struct dsa_switch *ds;
4747	5432
4748		- ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
	5433	+ ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4749	5434	if (!ds)
4750	5435	return -ENOMEM;
4751	5436
	5437	+ ds->dev = dev;
	5438	+ ds->num_ports = mv88e6xxx_num_ports(chip);
4752	5439	ds->priv = chip;
4753	5440	ds->dev = dev;
4754	5441	ds->ops = &mv88e6xxx_switch_ops;
..	..	@@ -4777,6 +5464,21 @@
4777	5464	}
4778	5465	return NULL;
4779	5466	}
	5467	+
	5468	+/* There is no suspend to RAM support at DSA level yet, the switch configuration
	5469	+ * would be lost after a power cycle so prevent it to be suspended.
	5470	+ */
	5471	+static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
	5472	+{
	5473	+ return -EOPNOTSUPP;
	5474	+}
	5475	+
	5476	+static int __maybe_unused mv88e6xxx_resume(struct device *dev)
	5477	+{
	5478	+ return 0;
	5479	+}
	5480	+
	5481	+static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
4780	5482
4781	5483	static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4782	5484	{
..	..	@@ -4837,7 +5539,6 @@
4837	5539	if (err)
4838	5540	goto out;
4839	5541
4840		- mv88e6xxx_ports_cmode_init(chip);
4841	5542	mv88e6xxx_phy_init(chip);
4842	5543
4843	5544	if (chip->info->ops->get_eeprom) {
..	..	@@ -4848,28 +5549,33 @@
4848	5549	chip->eeprom_len = pdata->eeprom_len;
4849	5550	}
4850	5551
4851		- mutex_lock(&chip->reg_lock);
	5552	+ mv88e6xxx_reg_lock(chip);
4852	5553	err = mv88e6xxx_switch_reset(chip);
4853		- mutex_unlock(&chip->reg_lock);
	5554	+ mv88e6xxx_reg_unlock(chip);
4854	5555	if (err)
4855	5556	goto out;
4856	5557
4857		- chip->irq = of_irq_get(np, 0);
4858		- if (chip->irq == -EPROBE_DEFER) {
4859		- err = chip->irq;
4860		- goto out;
	5558	+ if (np) {
	5559	+ chip->irq = of_irq_get(np, 0);
	5560	+ if (chip->irq == -EPROBE_DEFER) {
	5561	+ err = chip->irq;
	5562	+ goto out;
	5563	+ }
4861	5564	}
	5565	+
	5566	+ if (pdata)
	5567	+ chip->irq = pdata->irq;
4862	5568
4863	5569	/* Has to be performed before the MDIO bus is created, because
4864	5570	* the PHYs will link their interrupts to these interrupt
4865	5571	* controllers
4866	5572	*/
4867		- mutex_lock(&chip->reg_lock);
	5573	+ mv88e6xxx_reg_lock(chip);
4868	5574	if (chip->irq > 0)
4869	5575	err = mv88e6xxx_g1_irq_setup(chip);
4870	5576	else
4871	5577	err = mv88e6xxx_irq_poll_setup(chip);
4872		- mutex_unlock(&chip->reg_lock);
	5578	+ mv88e6xxx_reg_unlock(chip);
4873	5579
4874	5580	if (err)
4875	5581	goto out;
..	..	@@ -4954,6 +5660,10 @@
4954	5660	.compatible = "marvell,mv88e6190",
4955	5661	.data = &mv88e6xxx_table[MV88E6190],
4956	5662	},
	5663	+ {
	5664	+ .compatible = "marvell,mv88e6250",
	5665	+ .data = &mv88e6xxx_table[MV88E6250],
	5666	+ },
4957	5667	{ /* sentinel */ },
4958	5668	};
4959	5669
..	..	@@ -4965,22 +5675,11 @@
4965	5675	.mdiodrv.driver = {
4966	5676	.name = "mv88e6085",
4967	5677	.of_match_table = mv88e6xxx_of_match,
	5678	+ .pm = &mv88e6xxx_pm_ops,
4968	5679	},
4969	5680	};
4970	5681
4971		-static int __init mv88e6xxx_init(void)
4972		-{
4973		- register_switch_driver(&mv88e6xxx_switch_drv);
4974		- return mdio_driver_register(&mv88e6xxx_driver);
4975		-}
4976		-module_init(mv88e6xxx_init);
4977		-
4978		-static void __exit mv88e6xxx_cleanup(void)
4979		-{
4980		- mdio_driver_unregister(&mv88e6xxx_driver);
4981		- unregister_switch_driver(&mv88e6xxx_switch_drv);
4982		-}
4983		-module_exit(mv88e6xxx_cleanup);
	5682	+mdio_module_driver(mv88e6xxx_driver);
4984	5683
4985	5684	MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4986	5685	MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");