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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (C) 2006-2007 PA Semi, Inc |
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| 3 | 4 | * |
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| .. | .. |
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| 5 | 6 | * Maintained by: Olof Johansson <olof@lixom.net> |
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| 6 | 7 | * |
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| 7 | 8 | * Driver for the PWRficient onchip NAND flash interface |
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| 8 | | - * |
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| 9 | | - * This program is free software; you can redistribute it and/or modify |
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| 10 | | - * it under the terms of the GNU General Public License version 2 as |
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| 11 | | - * published by the Free Software Foundation. |
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| 12 | | - * |
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| 13 | | - * This program is distributed in the hope that it will be useful, |
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| 14 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 15 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 16 | | - * GNU General Public License for more details. |
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| 17 | | - * |
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| 18 | | - * You should have received a copy of the GNU General Public License |
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| 19 | | - * along with this program; if not, write to the Free Software |
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| 20 | | - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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| 21 | 9 | */ |
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| 22 | 10 | |
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| 23 | 11 | #undef DEBUG |
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| .. | .. |
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| 41 | 29 | |
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| 42 | 30 | static unsigned int lpcctl; |
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| 43 | 31 | static struct mtd_info *pasemi_nand_mtd; |
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| 32 | +static struct nand_controller controller; |
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| 44 | 33 | static const char driver_name[] = "pasemi-nand"; |
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| 45 | 34 | |
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| 46 | | -static void pasemi_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
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| 35 | +static void pasemi_read_buf(struct nand_chip *chip, u_char *buf, int len) |
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| 47 | 36 | { |
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| 48 | | - struct nand_chip *chip = mtd_to_nand(mtd); |
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| 49 | | - |
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| 50 | 37 | while (len > 0x800) { |
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| 51 | | - memcpy_fromio(buf, chip->IO_ADDR_R, 0x800); |
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| 38 | + memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800); |
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| 52 | 39 | buf += 0x800; |
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| 53 | 40 | len -= 0x800; |
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| 54 | 41 | } |
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| 55 | | - memcpy_fromio(buf, chip->IO_ADDR_R, len); |
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| 42 | + memcpy_fromio(buf, chip->legacy.IO_ADDR_R, len); |
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| 56 | 43 | } |
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| 57 | 44 | |
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| 58 | | -static void pasemi_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
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| 45 | +static void pasemi_write_buf(struct nand_chip *chip, const u_char *buf, |
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| 46 | + int len) |
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| 59 | 47 | { |
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| 60 | | - struct nand_chip *chip = mtd_to_nand(mtd); |
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| 61 | | - |
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| 62 | 48 | while (len > 0x800) { |
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| 63 | | - memcpy_toio(chip->IO_ADDR_R, buf, 0x800); |
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| 49 | + memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800); |
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| 64 | 50 | buf += 0x800; |
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| 65 | 51 | len -= 0x800; |
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| 66 | 52 | } |
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| 67 | | - memcpy_toio(chip->IO_ADDR_R, buf, len); |
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| 53 | + memcpy_toio(chip->legacy.IO_ADDR_R, buf, len); |
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| 68 | 54 | } |
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| 69 | 55 | |
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| 70 | | -static void pasemi_hwcontrol(struct mtd_info *mtd, int cmd, |
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| 56 | +static void pasemi_hwcontrol(struct nand_chip *chip, int cmd, |
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| 71 | 57 | unsigned int ctrl) |
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| 72 | 58 | { |
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| 73 | | - struct nand_chip *chip = mtd_to_nand(mtd); |
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| 74 | | - |
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| 75 | 59 | if (cmd == NAND_CMD_NONE) |
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| 76 | 60 | return; |
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| 77 | 61 | |
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| 78 | 62 | if (ctrl & NAND_CLE) |
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| 79 | | - out_8(chip->IO_ADDR_W + (1 << CLE_PIN_CTL), cmd); |
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| 63 | + out_8(chip->legacy.IO_ADDR_W + (1 << CLE_PIN_CTL), cmd); |
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| 80 | 64 | else |
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| 81 | | - out_8(chip->IO_ADDR_W + (1 << ALE_PIN_CTL), cmd); |
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| 65 | + out_8(chip->legacy.IO_ADDR_W + (1 << ALE_PIN_CTL), cmd); |
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| 82 | 66 | |
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| 83 | 67 | /* Push out posted writes */ |
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| 84 | 68 | eieio(); |
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| 85 | 69 | inl(lpcctl); |
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| 86 | 70 | } |
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| 87 | 71 | |
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| 88 | | -int pasemi_device_ready(struct mtd_info *mtd) |
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| 72 | +static int pasemi_device_ready(struct nand_chip *chip) |
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| 89 | 73 | { |
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| 90 | 74 | return !!(inl(lpcctl) & LBICTRL_LPCCTL_NR); |
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| 91 | 75 | } |
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| 76 | + |
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| 77 | +static int pasemi_attach_chip(struct nand_chip *chip) |
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| 78 | +{ |
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| 79 | + if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && |
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| 80 | + chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) |
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| 81 | + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; |
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| 82 | + |
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| 83 | + return 0; |
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| 84 | +} |
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| 85 | + |
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| 86 | +static const struct nand_controller_ops pasemi_ops = { |
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| 87 | + .attach_chip = pasemi_attach_chip, |
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| 88 | +}; |
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| 92 | 89 | |
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| 93 | 90 | static int pasemi_nand_probe(struct platform_device *ofdev) |
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| 94 | 91 | { |
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| .. | .. |
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| 117 | 114 | goto out; |
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| 118 | 115 | } |
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| 119 | 116 | |
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| 117 | + controller.ops = &pasemi_ops; |
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| 118 | + nand_controller_init(&controller); |
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| 119 | + chip->controller = &controller; |
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| 120 | + |
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| 120 | 121 | pasemi_nand_mtd = nand_to_mtd(chip); |
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| 121 | 122 | |
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| 122 | 123 | /* Link the private data with the MTD structure */ |
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| 123 | 124 | pasemi_nand_mtd->dev.parent = dev; |
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| 124 | 125 | |
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| 125 | | - chip->IO_ADDR_R = of_iomap(np, 0); |
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| 126 | | - chip->IO_ADDR_W = chip->IO_ADDR_R; |
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| 126 | + chip->legacy.IO_ADDR_R = of_iomap(np, 0); |
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| 127 | + chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R; |
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| 127 | 128 | |
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| 128 | | - if (!chip->IO_ADDR_R) { |
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| 129 | + if (!chip->legacy.IO_ADDR_R) { |
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| 129 | 130 | err = -EIO; |
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| 130 | 131 | goto out_mtd; |
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| 131 | 132 | } |
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| .. | .. |
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| 144 | 145 | goto out_ior; |
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| 145 | 146 | } |
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| 146 | 147 | |
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| 147 | | - chip->cmd_ctrl = pasemi_hwcontrol; |
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| 148 | | - chip->dev_ready = pasemi_device_ready; |
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| 149 | | - chip->read_buf = pasemi_read_buf; |
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| 150 | | - chip->write_buf = pasemi_write_buf; |
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| 151 | | - chip->chip_delay = 0; |
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| 152 | | - chip->ecc.mode = NAND_ECC_SOFT; |
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| 153 | | - chip->ecc.algo = NAND_ECC_HAMMING; |
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| 148 | + chip->legacy.cmd_ctrl = pasemi_hwcontrol; |
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| 149 | + chip->legacy.dev_ready = pasemi_device_ready; |
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| 150 | + chip->legacy.read_buf = pasemi_read_buf; |
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| 151 | + chip->legacy.write_buf = pasemi_write_buf; |
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| 152 | + chip->legacy.chip_delay = 0; |
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| 154 | 153 | |
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| 155 | 154 | /* Enable the following for a flash based bad block table */ |
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| 156 | 155 | chip->bbt_options = NAND_BBT_USE_FLASH; |
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| 156 | + |
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| 157 | + /* |
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| 158 | + * This driver assumes that the default ECC engine should be TYPE_SOFT. |
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| 159 | + * Set ->engine_type before registering the NAND devices in order to |
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| 160 | + * provide a driver specific default value. |
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| 161 | + */ |
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| 162 | + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; |
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| 157 | 163 | |
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| 158 | 164 | /* Scan to find existence of the device */ |
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| 159 | 165 | err = nand_scan(chip, 1); |
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| .. | .. |
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| 176 | 182 | out_lpc: |
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| 177 | 183 | release_region(lpcctl, 4); |
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| 178 | 184 | out_ior: |
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| 179 | | - iounmap(chip->IO_ADDR_R); |
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| 185 | + iounmap(chip->legacy.IO_ADDR_R); |
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| 180 | 186 | out_mtd: |
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| 181 | 187 | kfree(chip); |
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| 182 | 188 | out: |
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| .. | .. |
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| 186 | 192 | static int pasemi_nand_remove(struct platform_device *ofdev) |
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| 187 | 193 | { |
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| 188 | 194 | struct nand_chip *chip; |
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| 195 | + int ret; |
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| 189 | 196 | |
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| 190 | 197 | if (!pasemi_nand_mtd) |
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| 191 | 198 | return 0; |
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| .. | .. |
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| 193 | 200 | chip = mtd_to_nand(pasemi_nand_mtd); |
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| 194 | 201 | |
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| 195 | 202 | /* Release resources, unregister device */ |
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| 196 | | - nand_release(chip); |
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| 203 | + ret = mtd_device_unregister(pasemi_nand_mtd); |
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| 204 | + WARN_ON(ret); |
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| 205 | + nand_cleanup(chip); |
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| 197 | 206 | |
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| 198 | 207 | release_region(lpcctl, 4); |
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| 199 | 208 | |
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| 200 | | - iounmap(chip->IO_ADDR_R); |
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| 209 | + iounmap(chip->legacy.IO_ADDR_R); |
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| 201 | 210 | |
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| 202 | 211 | /* Free the MTD device structure */ |
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| 203 | 212 | kfree(chip); |
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