forked from ~ljy/RK356X_SDK_RELEASE

hc
2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c
kernel/drivers/mtd/nand/raw/pasemi_nand.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23 * Copyright (C) 2006-2007 PA Semi, Inc
34 *
....@@ -5,19 +6,6 @@
56 * Maintained by: Olof Johansson <olof@lixom.net>
67 *
78 * Driver for the PWRficient onchip NAND flash interface
8
- *
9
- * This program is free software; you can redistribute it and/or modify
10
- * it under the terms of the GNU General Public License version 2 as
11
- * published by the Free Software Foundation.
12
- *
13
- * This program is distributed in the hope that it will be useful,
14
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
15
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16
- * GNU General Public License for more details.
17
- *
18
- * You should have received a copy of the GNU General Public License
19
- * along with this program; if not, write to the Free Software
20
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
219 */
2210
2311 #undef DEBUG
....@@ -41,54 +29,63 @@
4129
4230 static unsigned int lpcctl;
4331 static struct mtd_info *pasemi_nand_mtd;
32
+static struct nand_controller controller;
4433 static const char driver_name[] = "pasemi-nand";
4534
46
-static void pasemi_read_buf(struct mtd_info *mtd, u_char *buf, int len)
35
+static void pasemi_read_buf(struct nand_chip *chip, u_char *buf, int len)
4736 {
48
- struct nand_chip *chip = mtd_to_nand(mtd);
49
-
5037 while (len > 0x800) {
51
- memcpy_fromio(buf, chip->IO_ADDR_R, 0x800);
38
+ memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800);
5239 buf += 0x800;
5340 len -= 0x800;
5441 }
55
- memcpy_fromio(buf, chip->IO_ADDR_R, len);
42
+ memcpy_fromio(buf, chip->legacy.IO_ADDR_R, len);
5643 }
5744
58
-static void pasemi_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
45
+static void pasemi_write_buf(struct nand_chip *chip, const u_char *buf,
46
+ int len)
5947 {
60
- struct nand_chip *chip = mtd_to_nand(mtd);
61
-
6248 while (len > 0x800) {
63
- memcpy_toio(chip->IO_ADDR_R, buf, 0x800);
49
+ memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800);
6450 buf += 0x800;
6551 len -= 0x800;
6652 }
67
- memcpy_toio(chip->IO_ADDR_R, buf, len);
53
+ memcpy_toio(chip->legacy.IO_ADDR_R, buf, len);
6854 }
6955
70
-static void pasemi_hwcontrol(struct mtd_info *mtd, int cmd,
56
+static void pasemi_hwcontrol(struct nand_chip *chip, int cmd,
7157 unsigned int ctrl)
7258 {
73
- struct nand_chip *chip = mtd_to_nand(mtd);
74
-
7559 if (cmd == NAND_CMD_NONE)
7660 return;
7761
7862 if (ctrl & NAND_CLE)
79
- out_8(chip->IO_ADDR_W + (1 << CLE_PIN_CTL), cmd);
63
+ out_8(chip->legacy.IO_ADDR_W + (1 << CLE_PIN_CTL), cmd);
8064 else
81
- out_8(chip->IO_ADDR_W + (1 << ALE_PIN_CTL), cmd);
65
+ out_8(chip->legacy.IO_ADDR_W + (1 << ALE_PIN_CTL), cmd);
8266
8367 /* Push out posted writes */
8468 eieio();
8569 inl(lpcctl);
8670 }
8771
88
-int pasemi_device_ready(struct mtd_info *mtd)
72
+static int pasemi_device_ready(struct nand_chip *chip)
8973 {
9074 return !!(inl(lpcctl) & LBICTRL_LPCCTL_NR);
9175 }
76
+
77
+static int pasemi_attach_chip(struct nand_chip *chip)
78
+{
79
+ if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
80
+ chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
81
+ chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
82
+
83
+ return 0;
84
+}
85
+
86
+static const struct nand_controller_ops pasemi_ops = {
87
+ .attach_chip = pasemi_attach_chip,
88
+};
9289
9390 static int pasemi_nand_probe(struct platform_device *ofdev)
9491 {
....@@ -117,15 +114,19 @@
117114 goto out;
118115 }
119116
117
+ controller.ops = &pasemi_ops;
118
+ nand_controller_init(&controller);
119
+ chip->controller = &controller;
120
+
120121 pasemi_nand_mtd = nand_to_mtd(chip);
121122
122123 /* Link the private data with the MTD structure */
123124 pasemi_nand_mtd->dev.parent = dev;
124125
125
- chip->IO_ADDR_R = of_iomap(np, 0);
126
- chip->IO_ADDR_W = chip->IO_ADDR_R;
126
+ chip->legacy.IO_ADDR_R = of_iomap(np, 0);
127
+ chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
127128
128
- if (!chip->IO_ADDR_R) {
129
+ if (!chip->legacy.IO_ADDR_R) {
129130 err = -EIO;
130131 goto out_mtd;
131132 }
....@@ -144,16 +145,21 @@
144145 goto out_ior;
145146 }
146147
147
- chip->cmd_ctrl = pasemi_hwcontrol;
148
- chip->dev_ready = pasemi_device_ready;
149
- chip->read_buf = pasemi_read_buf;
150
- chip->write_buf = pasemi_write_buf;
151
- chip->chip_delay = 0;
152
- chip->ecc.mode = NAND_ECC_SOFT;
153
- chip->ecc.algo = NAND_ECC_HAMMING;
148
+ chip->legacy.cmd_ctrl = pasemi_hwcontrol;
149
+ chip->legacy.dev_ready = pasemi_device_ready;
150
+ chip->legacy.read_buf = pasemi_read_buf;
151
+ chip->legacy.write_buf = pasemi_write_buf;
152
+ chip->legacy.chip_delay = 0;
154153
155154 /* Enable the following for a flash based bad block table */
156155 chip->bbt_options = NAND_BBT_USE_FLASH;
156
+
157
+ /*
158
+ * This driver assumes that the default ECC engine should be TYPE_SOFT.
159
+ * Set ->engine_type before registering the NAND devices in order to
160
+ * provide a driver specific default value.
161
+ */
162
+ chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
157163
158164 /* Scan to find existence of the device */
159165 err = nand_scan(chip, 1);
....@@ -176,7 +182,7 @@
176182 out_lpc:
177183 release_region(lpcctl, 4);
178184 out_ior:
179
- iounmap(chip->IO_ADDR_R);
185
+ iounmap(chip->legacy.IO_ADDR_R);
180186 out_mtd:
181187 kfree(chip);
182188 out:
....@@ -186,6 +192,7 @@
186192 static int pasemi_nand_remove(struct platform_device *ofdev)
187193 {
188194 struct nand_chip *chip;
195
+ int ret;
189196
190197 if (!pasemi_nand_mtd)
191198 return 0;
....@@ -193,11 +200,13 @@
193200 chip = mtd_to_nand(pasemi_nand_mtd);
194201
195202 /* Release resources, unregister device */
196
- nand_release(chip);
203
+ ret = mtd_device_unregister(pasemi_nand_mtd);
204
+ WARN_ON(ret);
205
+ nand_cleanup(chip);
197206
198207 release_region(lpcctl, 4);
199208
200
- iounmap(chip->IO_ADDR_R);
209
+ iounmap(chip->legacy.IO_ADDR_R);
201210
202211 /* Free the MTD device structure */
203212 kfree(chip);