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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c

 kernel/drivers/mtd/nand/raw/orion_nand.c
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@@ -22,13 +22,14 @@
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 #include <linux/platform_data/mtd-orion_nand.h>
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23
 
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 struct orion_nand_info {
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+	struct nand_controller controller;
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 	struct nand_chip chip;
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 	struct clk *clk;
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 };
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29
 
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-static void orion_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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+static void orion_nand_cmd_ctrl(struct nand_chip *nc, int cmd,
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+				unsigned int ctrl)
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 {
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-	struct nand_chip *nc = mtd_to_nand(mtd);
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 	struct orion_nand_data *board = nand_get_controller_data(nc);
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 	u32 offs;
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@@ -45,13 +46,12 @@
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 	if (nc->options & NAND_BUSWIDTH_16)
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 		offs <<= 1;
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-	writeb(cmd, nc->IO_ADDR_W + offs);
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+	writeb(cmd, nc->legacy.IO_ADDR_W + offs);
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 }
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-static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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+static void orion_nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
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 {
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-	struct nand_chip *chip = mtd_to_nand(mtd);
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-	void __iomem *io_base = chip->IO_ADDR_R;
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+	void __iomem *io_base = chip->legacy.IO_ADDR_R;
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 #if defined(__LINUX_ARM_ARCH__) && __LINUX_ARM_ARCH__ >= 5
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 	uint64_t *buf64;
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 #endif
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@@ -83,6 +83,19 @@
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 		buf[i++] = readb(io_base);
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 }
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+static int orion_nand_attach_chip(struct nand_chip *chip)
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+{
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+	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
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+	    chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
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+		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
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+
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+	return 0;
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+}
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+
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+static const struct nand_controller_ops orion_nand_ops = {
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+	.attach_chip = orion_nand_attach_chip,
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+};
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+
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 static int __init orion_nand_probe(struct platform_device *pdev)
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 {
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 	struct orion_nand_info *info;
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@@ -101,6 +114,10 @@
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 		return -ENOMEM;
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 	nc = &info->chip;
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 	mtd = nand_to_mtd(nc);
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+
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+	nand_controller_init(&info->controller);
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+	info->controller.ops = &orion_nand_ops;
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+	nc->controller = &info->controller;
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 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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 	io_base = devm_ioremap_resource(&pdev->dev, res);
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@@ -137,14 +154,12 @@
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 	nand_set_controller_data(nc, board);
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 	nand_set_flash_node(nc, pdev->dev.of_node);
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-	nc->IO_ADDR_R = nc->IO_ADDR_W = io_base;
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-	nc->cmd_ctrl = orion_nand_cmd_ctrl;
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-	nc->read_buf = orion_nand_read_buf;
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-	nc->ecc.mode = NAND_ECC_SOFT;
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-	nc->ecc.algo = NAND_ECC_HAMMING;
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+	nc->legacy.IO_ADDR_R = nc->legacy.IO_ADDR_W = io_base;
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+	nc->legacy.cmd_ctrl = orion_nand_cmd_ctrl;
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+	nc->legacy.read_buf = orion_nand_read_buf;
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 	if (board->chip_delay)
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-		nc->chip_delay = board->chip_delay;
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+		nc->legacy.chip_delay = board->chip_delay;
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 	WARN(board->width > 16,
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 		"%d bit bus width out of range",
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@@ -174,6 +189,13 @@
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 		return ret;
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 	}
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191
 
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+	/*
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+	 * This driver assumes that the default ECC engine should be TYPE_SOFT.
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+	 * Set ->engine_type before registering the NAND devices in order to
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+	 * provide a driver specific default value.
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+	 */
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+	nc->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
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+
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 	ret = nand_scan(nc, 1);
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 	if (ret)
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 		goto no_dev;
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@@ -196,8 +218,12 @@
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 {
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 	struct orion_nand_info *info = platform_get_drvdata(pdev);
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 	struct nand_chip *chip = &info->chip;
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+	int ret;
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-	nand_release(chip);
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+	ret = mtd_device_unregister(nand_to_mtd(chip));
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+	WARN_ON(ret);
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+
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+	nand_cleanup(chip);
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 	clk_disable_unprepare(info->clk);
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