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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/mtd/nand/raw/marvell_nand.c
....@@ -5,6 +5,73 @@
55  * Copyright (C) 2017 Marvell
66  * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
77  *
8
+ *
9
+ * This NAND controller driver handles two versions of the hardware,
10
+ * one is called NFCv1 and is available on PXA SoCs and the other is
11
+ * called NFCv2 and is available on Armada SoCs.
12
+ *
13
+ * The main visible difference is that NFCv1 only has Hamming ECC
14
+ * capabilities, while NFCv2 also embeds a BCH ECC engine. Also, DMA
15
+ * is not used with NFCv2.
16
+ *
17
+ * The ECC layouts are depicted in details in Marvell AN-379, but here
18
+ * is a brief description.
19
+ *
20
+ * When using Hamming, the data is split in 512B chunks (either 1, 2
21
+ * or 4) and each chunk will have its own ECC "digest" of 6B at the
22
+ * beginning of the OOB area and eventually the remaining free OOB
23
+ * bytes (also called "spare" bytes in the driver). This engine
24
+ * corrects up to 1 bit per chunk and detects reliably an error if
25
+ * there are at most 2 bitflips. Here is the page layout used by the
26
+ * controller when Hamming is chosen:
27
+ *
28
+ * +-------------------------------------------------------------+
29
+ * | Data 1 | ... | Data N | ECC 1 | ... | ECCN | Free OOB bytes |
30
+ * +-------------------------------------------------------------+
31
+ *
32
+ * When using the BCH engine, there are N identical (data + free OOB +
33
+ * ECC) sections and potentially an extra one to deal with
34
+ * configurations where the chosen (data + free OOB + ECC) sizes do
35
+ * not align with the page (data + OOB) size. ECC bytes are always
36
+ * 30B per ECC chunk. Here is the page layout used by the controller
37
+ * when BCH is chosen:
38
+ *
39
+ * +-----------------------------------------
40
+ * | Data 1 | Free OOB bytes 1 | ECC 1 | ...
41
+ * +-----------------------------------------
42
+ *
43
+ *      -------------------------------------------
44
+ *       ... | Data N | Free OOB bytes N | ECC N |
45
+ *      -------------------------------------------
46
+ *
47
+ *           --------------------------------------------+
48
+ *            Last Data | Last Free OOB bytes | Last ECC |
49
+ *           --------------------------------------------+
50
+ *
51
+ * In both cases, the layout seen by the user is always: all data
52
+ * first, then all free OOB bytes and finally all ECC bytes. With BCH,
53
+ * ECC bytes are 30B long and are padded with 0xFF to align on 32
54
+ * bytes.
55
+ *
56
+ * The controller has certain limitations that are handled by the
57
+ * driver:
58
+ *   - It can only read 2k at a time. To overcome this limitation, the
59
+ *     driver issues data cycles on the bus, without issuing new
60
+ *     CMD + ADDR cycles. The Marvell term is "naked" operations.
61
+ *   - The ECC strength in BCH mode cannot be tuned. It is fixed 16
62
+ *     bits. What can be tuned is the ECC block size as long as it
63
+ *     stays between 512B and 2kiB. It's usually chosen based on the
64
+ *     chip ECC requirements. For instance, using 2kiB ECC chunks
65
+ *     provides 4b/512B correctability.
66
+ *   - The controller will always treat data bytes, free OOB bytes
67
+ *     and ECC bytes in that order, no matter what the real layout is
68
+ *     (which is usually all data then all OOB bytes). The
69
+ *     marvell_nfc_layouts array below contains the currently
70
+ *     supported layouts.
71
+ *   - Because of these weird layouts, the Bad Block Markers can be
72
+ *     located in data section. In this case, the NAND_BBT_NO_OOB_BBM
73
+ *     option must be set to prevent scanning/writing bad block
74
+ *     markers.
875  */
976 
1077 #include <linux/module.h>
....@@ -160,6 +227,8 @@
160227 #define XTYPE_MASK		7
161228 
162229 /**
230
+ * struct marvell_hw_ecc_layout - layout of Marvell ECC
231
+ *
163232  * Marvell ECC engine works differently than the others, in order to limit the
164233  * size of the IP, hardware engineers chose to set a fixed strength at 16 bits
165234  * per subpage, and depending on a the desired strength needed by the NAND chip,
....@@ -217,11 +286,16 @@
217286 	MARVELL_LAYOUT(  512,   512,  1,  1,  1,  512,  8,  8,  0,  0,  0),
218287 	MARVELL_LAYOUT( 2048,   512,  1,  1,  1, 2048, 40, 24,  0,  0,  0),
219288 	MARVELL_LAYOUT( 2048,   512,  4,  1,  1, 2048, 32, 30,  0,  0,  0),
289
+	MARVELL_LAYOUT( 2048,   512,  8,  2,  1, 1024,  0, 30,1024,32, 30),
220290 	MARVELL_LAYOUT( 4096,   512,  4,  2,  2, 2048, 32, 30,  0,  0,  0),
221291 	MARVELL_LAYOUT( 4096,   512,  8,  5,  4, 1024,  0, 30,  0, 64, 30),
292
+	MARVELL_LAYOUT( 8192,   512,  4,  4,  4, 2048,  0, 30,  0,  0,  0),
293
+	MARVELL_LAYOUT( 8192,   512,  8,  9,  8, 1024,  0, 30,  0, 160, 30),
222294 };
223295 
224296 /**
297
+ * struct marvell_nand_chip_sel - CS line description
298
+ *
225299  * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection
226300  * is made by a field in NDCB0 register, and in another field in NDCB2 register.
227301  * The datasheet describes the logic with an error: ADDR5 field is once
....@@ -242,14 +316,15 @@
242316 };
243317 
244318 /**
245
- * NAND chip structure: stores NAND chip device related information
319
+ * struct marvell_nand_chip - stores NAND chip device related information
246320  *
247321  * @chip:		Base NAND chip structure
248322  * @node:		Used to store NAND chips into a list
249
- * @layout		NAND layout when using hardware ECC
323
+ * @layout:		NAND layout when using hardware ECC
250324  * @ndcr:		Controller register value for this NAND chip
251325  * @ndtr0:		Timing registers 0 value for this NAND chip
252326  * @ndtr1:		Timing registers 1 value for this NAND chip
327
+ * @addr_cyc:		Amount of cycles needed to pass column address
253328  * @selected_die:	Current active CS
254329  * @nsels:		Number of CS lines required by the NAND chip
255330  * @sels:		Array of CS lines descriptions
....@@ -264,7 +339,7 @@
264339 	int addr_cyc;
265340 	int selected_die;
266341 	unsigned int nsels;
267
-	struct marvell_nand_chip_sel sels[0];
342
+	struct marvell_nand_chip_sel sels[];
268343 };
269344 
270345 static inline struct marvell_nand_chip *to_marvell_nand(struct nand_chip *chip)
....@@ -279,7 +354,8 @@
279354 }
280355 
281356 /**
282
- * NAND controller capabilities for distinction between compatible strings
357
+ * struct marvell_nfc_caps - NAND controller capabilities for distinction
358
+ *                           between compatible strings
283359  *
284360  * @max_cs_nb:		Number of Chip Select lines available
285361  * @max_rb_nb:		Number of Ready/Busy lines available
....@@ -302,18 +378,20 @@
302378 };
303379 
304380 /**
305
- * NAND controller structure: stores Marvell NAND controller information
381
+ * struct marvell_nfc - stores Marvell NAND controller information
306382  *
307383  * @controller:		Base controller structure
308384  * @dev:		Parent device (used to print error messages)
309385  * @regs:		NAND controller registers
310386  * @core_clk:		Core clock
311
- * @reg_clk:		Regiters clock
387
+ * @reg_clk:		Registers clock
312388  * @complete:		Completion object to wait for NAND controller events
313389  * @assigned_cs:	Bitmask describing already assigned CS lines
314390  * @chips:		List containing all the NAND chips attached to
315391  *			this NAND controller
392
+ * @selected_chip:	Currently selected target chip
316393  * @caps:		NAND controller capabilities for each compatible string
394
+ * @use_dma:		Whetner DMA is used
317395  * @dma_chan:		DMA channel (NFCv1 only)
318396  * @dma_buf:		32-bit aligned buffer for DMA transfers (NFCv1 only)
319397  */
....@@ -341,7 +419,8 @@
341419 }
342420 
343421 /**
344
- * NAND controller timings expressed in NAND Controller clock cycles
422
+ * struct marvell_nfc_timings - NAND controller timings expressed in NAND
423
+ *                              Controller clock cycles
345424  *
346425  * @tRP:		ND_nRE pulse width
347426  * @tRH:		ND_nRE high duration
....@@ -385,8 +464,8 @@
385464 						     period_ns))
386465 
387466 /**
388
- * NAND driver structure filled during the parsing of the ->exec_op() subop
389
- * subset of instructions.
467
+ * struct marvell_nfc_op - filled during the parsing of the ->exec_op()
468
+ *                         subop subset of instructions.
390469  *
391470  * @ndcb:		Array of values written to NDCBx registers
392471  * @cle_ale_delay_ns:	Optional delay after the last CMD or ADDR cycle
....@@ -615,9 +694,31 @@
615694 	return marvell_nfc_end_cmd(chip, cs_flag, "CMDD");
616695 }
617696 
697
+static int marvell_nfc_poll_status(struct marvell_nfc *nfc, u32 mask,
698
+				   u32 expected_val, unsigned long timeout_ms)
699
+{
700
+	unsigned long limit;
701
+	u32 st;
702
+
703
+	limit = jiffies + msecs_to_jiffies(timeout_ms);
704
+	do {
705
+		st = readl_relaxed(nfc->regs + NDSR);
706
+		if (st & NDSR_RDY(1))
707
+			st |= NDSR_RDY(0);
708
+
709
+		if ((st & mask) == expected_val)
710
+			return 0;
711
+
712
+		cpu_relax();
713
+	} while (time_after(limit, jiffies));
714
+
715
+	return -ETIMEDOUT;
716
+}
717
+
618718 static int marvell_nfc_wait_op(struct nand_chip *chip, unsigned int timeout_ms)
619719 {
620720 	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
721
+	struct mtd_info *mtd = nand_to_mtd(chip);
621722 	u32 pending;
622723 	int ret;
623724 
....@@ -625,12 +726,18 @@
625726 	if (!timeout_ms)
626727 		timeout_ms = IRQ_TIMEOUT;
627728 
628
-	init_completion(&nfc->complete);
729
+	if (mtd->oops_panic_write) {
730
+		ret = marvell_nfc_poll_status(nfc, NDSR_RDY(0),
731
+					      NDSR_RDY(0),
732
+					      timeout_ms);
733
+	} else {
734
+		init_completion(&nfc->complete);
629735 
630
-	marvell_nfc_enable_int(nfc, NDCR_RDYM);
631
-	ret = wait_for_completion_timeout(&nfc->complete,
632
-					  msecs_to_jiffies(timeout_ms));
633
-	marvell_nfc_disable_int(nfc, NDCR_RDYM);
736
+		marvell_nfc_enable_int(nfc, NDCR_RDYM);
737
+		ret = wait_for_completion_timeout(&nfc->complete,
738
+						  msecs_to_jiffies(timeout_ms));
739
+		marvell_nfc_disable_int(nfc, NDCR_RDYM);
740
+	}
634741 	pending = marvell_nfc_clear_int(nfc, NDSR_RDY(0) | NDSR_RDY(1));
635742 
636743 	/*
....@@ -645,24 +752,12 @@
645752 	return 0;
646753 }
647754 
648
-static void marvell_nfc_select_chip(struct mtd_info *mtd, int die_nr)
755
+static void marvell_nfc_select_target(struct nand_chip *chip,
756
+				      unsigned int die_nr)
649757 {
650
-	struct nand_chip *chip = mtd_to_nand(mtd);
651758 	struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
652759 	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
653760 	u32 ndcr_generic;
654
-
655
-	if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die)
656
-		return;
657
-
658
-	if (die_nr < 0 || die_nr >= marvell_nand->nsels) {
659
-		nfc->selected_chip = NULL;
660
-		marvell_nand->selected_die = -1;
661
-		return;
662
-	}
663
-
664
-	writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0);
665
-	writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1);
666761 
667762 	/*
668763 	 * Reset the NDCR register to a clean state for this particular chip,
....@@ -674,6 +769,12 @@
674769 
675770 	/* Also reset the interrupt status register */
676771 	marvell_nfc_clear_int(nfc, NDCR_ALL_INT);
772
+
773
+	if (chip == nfc->selected_chip && die_nr == marvell_nand->selected_die)
774
+		return;
775
+
776
+	writel_relaxed(marvell_nand->ndtr0, nfc->regs + NDTR0);
777
+	writel_relaxed(marvell_nand->ndtr1, nfc->regs + NDTR1);
677778 
678779 	nfc->selected_chip = chip;
679780 	marvell_nand->selected_die = die_nr;
....@@ -716,7 +817,7 @@
716817 		 * When enabling BCH, set threshold to 0 to always know the
717818 		 * number of corrected bitflips.
718819 		 */
719
-		if (chip->ecc.algo == NAND_ECC_BCH)
820
+		if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
720821 			writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL);
721822 	}
722823 }
....@@ -728,7 +829,7 @@
728829 
729830 	if (ndcr & NDCR_ECC_EN) {
730831 		writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR);
731
-		if (chip->ecc.algo == NAND_ECC_BCH)
832
+		if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
732833 			writel_relaxed(0, nfc->regs + NDECCCTRL);
733834 	}
734835 }
....@@ -868,14 +969,14 @@
868969 }
869970 
870971 /*
871
- * Check a chunk is correct or not according to hardware ECC engine.
972
+ * Check if a chunk is correct or not according to the hardware ECC engine.
872973  * mtd->ecc_stats.corrected is updated, as well as max_bitflips, however
873974  * mtd->ecc_stats.failure is not, the function will instead return a non-zero
874975  * value indicating that a check on the emptyness of the subpage must be
875
- * performed before declaring the subpage corrupted.
976
+ * performed before actually declaring the subpage as "corrupted".
876977  */
877
-static int marvell_nfc_hw_ecc_correct(struct nand_chip *chip,
878
-				      unsigned int *max_bitflips)
978
+static int marvell_nfc_hw_ecc_check_bitflips(struct nand_chip *chip,
979
+					     unsigned int *max_bitflips)
879980 {
880981 	struct mtd_info *mtd = nand_to_mtd(chip);
881982 	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
....@@ -902,7 +1003,7 @@
9021003 	if (ndsr & NDSR_CORERR) {
9031004 		writel_relaxed(ndsr, nfc->regs + NDSR);
9041005 
905
-		if (chip->ecc.algo == NAND_ECC_BCH)
1006
+		if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
9061007 			bf = NDSR_ERRCNT(ndsr);
9071008 		else
9081009 			bf = 1;
....@@ -966,32 +1067,30 @@
9661067 	}
9671068 
9681069 	ret = marvell_nfc_wait_cmdd(chip);
969
-
9701070 	return ret;
9711071 }
9721072 
973
-static int marvell_nfc_hw_ecc_hmg_read_page_raw(struct mtd_info *mtd,
974
-						struct nand_chip *chip, u8 *buf,
1073
+static int marvell_nfc_hw_ecc_hmg_read_page_raw(struct nand_chip *chip, u8 *buf,
9751074 						int oob_required, int page)
9761075 {
1076
+	marvell_nfc_select_target(chip, chip->cur_cs);
9771077 	return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi,
9781078 						   true, page);
9791079 }
9801080 
981
-static int marvell_nfc_hw_ecc_hmg_read_page(struct mtd_info *mtd,
982
-					    struct nand_chip *chip,
983
-					    u8 *buf, int oob_required,
984
-					    int page)
1081
+static int marvell_nfc_hw_ecc_hmg_read_page(struct nand_chip *chip, u8 *buf,
1082
+					    int oob_required, int page)
9851083 {
9861084 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
9871085 	unsigned int full_sz = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
9881086 	int max_bitflips = 0, ret;
9891087 	u8 *raw_buf;
9901088 
1089
+	marvell_nfc_select_target(chip, chip->cur_cs);
9911090 	marvell_nfc_enable_hw_ecc(chip);
9921091 	marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi, false,
9931092 					    page);
994
-	ret = marvell_nfc_hw_ecc_correct(chip, &max_bitflips);
1093
+	ret = marvell_nfc_hw_ecc_check_bitflips(chip, &max_bitflips);
9951094 	marvell_nfc_disable_hw_ecc(chip);
9961095 
9971096 	if (!ret)
....@@ -1019,14 +1118,13 @@
10191118  * it appears before the ECC bytes when reading), the ->read_oob_raw() function
10201119  * also stands for ->read_oob().
10211120  */
1022
-static int marvell_nfc_hw_ecc_hmg_read_oob_raw(struct mtd_info *mtd,
1023
-					       struct nand_chip *chip, int page)
1121
+static int marvell_nfc_hw_ecc_hmg_read_oob_raw(struct nand_chip *chip, int page)
10241122 {
1025
-	/* Invalidate page cache */
1026
-	chip->pagebuf = -1;
1123
+	u8 *buf = nand_get_data_buf(chip);
10271124 
1028
-	return marvell_nfc_hw_ecc_hmg_do_read_page(chip, chip->data_buf,
1029
-						   chip->oob_poi, true, page);
1125
+	marvell_nfc_select_target(chip, chip->cur_cs);
1126
+	return marvell_nfc_hw_ecc_hmg_do_read_page(chip, buf, chip->oob_poi,
1127
+						   true, page);
10301128 }
10311129 
10321130 /* Hamming write helpers */
....@@ -1035,6 +1133,8 @@
10351133 						const u8 *oob_buf, bool raw,
10361134 						int page)
10371135 {
1136
+	const struct nand_sdr_timings *sdr =
1137
+		nand_get_sdr_timings(nand_get_interface_config(chip));
10381138 	struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
10391139 	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
10401140 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
....@@ -1080,26 +1180,26 @@
10801180 		return ret;
10811181 
10821182 	ret = marvell_nfc_wait_op(chip,
1083
-				  PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max));
1183
+				  PSEC_TO_MSEC(sdr->tPROG_max));
10841184 	return ret;
10851185 }
10861186 
1087
-static int marvell_nfc_hw_ecc_hmg_write_page_raw(struct mtd_info *mtd,
1088
-						 struct nand_chip *chip,
1187
+static int marvell_nfc_hw_ecc_hmg_write_page_raw(struct nand_chip *chip,
10891188 						 const u8 *buf,
10901189 						 int oob_required, int page)
10911190 {
1191
+	marvell_nfc_select_target(chip, chip->cur_cs);
10921192 	return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
10931193 						    true, page);
10941194 }
10951195 
1096
-static int marvell_nfc_hw_ecc_hmg_write_page(struct mtd_info *mtd,
1097
-					     struct nand_chip *chip,
1196
+static int marvell_nfc_hw_ecc_hmg_write_page(struct nand_chip *chip,
10981197 					     const u8 *buf,
10991198 					     int oob_required, int page)
11001199 {
11011200 	int ret;
11021201 
1202
+	marvell_nfc_select_target(chip, chip->cur_cs);
11031203 	marvell_nfc_enable_hw_ecc(chip);
11041204 	ret = marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
11051205 						   false, page);
....@@ -1113,24 +1213,24 @@
11131213  * it appears before the ECC bytes when reading), the ->write_oob_raw() function
11141214  * also stands for ->write_oob().
11151215  */
1116
-static int marvell_nfc_hw_ecc_hmg_write_oob_raw(struct mtd_info *mtd,
1117
-						struct nand_chip *chip,
1216
+static int marvell_nfc_hw_ecc_hmg_write_oob_raw(struct nand_chip *chip,
11181217 						int page)
11191218 {
1120
-	/* Invalidate page cache */
1121
-	chip->pagebuf = -1;
1219
+	struct mtd_info *mtd = nand_to_mtd(chip);
1220
+	u8 *buf = nand_get_data_buf(chip);
11221221 
1123
-	memset(chip->data_buf, 0xFF, mtd->writesize);
1222
+	memset(buf, 0xFF, mtd->writesize);
11241223 
1125
-	return marvell_nfc_hw_ecc_hmg_do_write_page(chip, chip->data_buf,
1126
-						    chip->oob_poi, true, page);
1224
+	marvell_nfc_select_target(chip, chip->cur_cs);
1225
+	return marvell_nfc_hw_ecc_hmg_do_write_page(chip, buf, chip->oob_poi,
1226
+						    true, page);
11271227 }
11281228 
11291229 /* BCH read helpers */
1130
-static int marvell_nfc_hw_ecc_bch_read_page_raw(struct mtd_info *mtd,
1131
-						struct nand_chip *chip, u8 *buf,
1230
+static int marvell_nfc_hw_ecc_bch_read_page_raw(struct nand_chip *chip, u8 *buf,
11321231 						int oob_required, int page)
11331232 {
1233
+	struct mtd_info *mtd = nand_to_mtd(chip);
11341234 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
11351235 	u8 *oob = chip->oob_poi;
11361236 	int chunk_size = lt->data_bytes + lt->spare_bytes + lt->ecc_bytes;
....@@ -1140,6 +1240,8 @@
11401240 	int spare_len = lt->spare_bytes;
11411241 	int ecc_len = lt->ecc_bytes;
11421242 	int chunk;
1243
+
1244
+	marvell_nfc_select_target(chip, chip->cur_cs);
11431245 
11441246 	if (oob_required)
11451247 		memset(chip->oob_poi, 0xFF, mtd->oobsize);
....@@ -1161,12 +1263,12 @@
11611263 
11621264 		/* Read spare bytes */
11631265 		nand_read_data_op(chip, oob + (lt->spare_bytes * chunk),
1164
-				  spare_len, false);
1266
+				  spare_len, false, false);
11651267 
11661268 		/* Read ECC bytes */
11671269 		nand_read_data_op(chip, oob + ecc_offset +
11681270 				  (ALIGN(lt->ecc_bytes, 32) * chunk),
1169
-				  ecc_len, false);
1271
+				  ecc_len, false, false);
11701272 	}
11711273 
11721274 	return 0;
....@@ -1239,17 +1341,19 @@
12391341 	}
12401342 }
12411343 
1242
-static int marvell_nfc_hw_ecc_bch_read_page(struct mtd_info *mtd,
1243
-					    struct nand_chip *chip,
1344
+static int marvell_nfc_hw_ecc_bch_read_page(struct nand_chip *chip,
12441345 					    u8 *buf, int oob_required,
12451346 					    int page)
12461347 {
1348
+	struct mtd_info *mtd = nand_to_mtd(chip);
12471349 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1248
-	int data_len = lt->data_bytes, spare_len = lt->spare_bytes, ecc_len;
1249
-	u8 *data = buf, *spare = chip->oob_poi, *ecc;
1350
+	int data_len = lt->data_bytes, spare_len = lt->spare_bytes;
1351
+	u8 *data = buf, *spare = chip->oob_poi;
12501352 	int max_bitflips = 0;
12511353 	u32 failure_mask = 0;
1252
-	int chunk, ecc_offset_in_page, ret;
1354
+	int chunk, ret;
1355
+
1356
+	marvell_nfc_select_target(chip, chip->cur_cs);
12531357 
12541358 	/*
12551359 	 * With BCH, OOB is not fully used (and thus not read entirely), not
....@@ -1271,7 +1375,7 @@
12711375 		/* Read the chunk and detect number of bitflips */
12721376 		marvell_nfc_hw_ecc_bch_read_chunk(chip, chunk, data, data_len,
12731377 						  spare, spare_len, page);
1274
-		ret = marvell_nfc_hw_ecc_correct(chip, &max_bitflips);
1378
+		ret = marvell_nfc_hw_ecc_check_bitflips(chip, &max_bitflips);
12751379 		if (ret)
12761380 			failure_mask |= BIT(chunk);
12771381 
....@@ -1290,73 +1394,95 @@
12901394 	 * the controller in normal mode and must be re-read in raw mode. To
12911395 	 * avoid dropping the performances, we prefer not to include them. The
12921396 	 * user should re-read the page in raw mode if ECC bytes are required.
1397
+	 */
1398
+
1399
+	/*
1400
+	 * In case there is any subpage read error, we usually re-read only ECC
1401
+	 * bytes in raw mode and check if the whole page is empty. In this case,
1402
+	 * it is normal that the ECC check failed and we just ignore the error.
12931403 	 *
1294
-	 * However, for any subpage read error reported by ->correct(), the ECC
1295
-	 * bytes must be read in raw mode and the full subpage must be checked
1296
-	 * to see if it is entirely empty of if there was an actual error.
1404
+	 * However, it has been empirically observed that for some layouts (e.g
1405
+	 * 2k page, 8b strength per 512B chunk), the controller tries to correct
1406
+	 * bits and may create itself bitflips in the erased area. To overcome
1407
+	 * this strange behavior, the whole page is re-read in raw mode, not
1408
+	 * only the ECC bytes.
12971409 	 */
12981410 	for (chunk = 0; chunk < lt->nchunks; chunk++) {
1411
+		int data_off_in_page, spare_off_in_page, ecc_off_in_page;
1412
+		int data_off, spare_off, ecc_off;
1413
+		int data_len, spare_len, ecc_len;
1414
+
12991415 		/* No failure reported for this chunk, move to the next one */
13001416 		if (!(failure_mask & BIT(chunk)))
13011417 			continue;
13021418 
1303
-		/* Derive ECC bytes positions (in page/buffer) and length */
1304
-		ecc = chip->oob_poi +
1305
-			(lt->full_chunk_cnt * lt->spare_bytes) +
1306
-			lt->last_spare_bytes +
1307
-			(chunk * ALIGN(lt->ecc_bytes, 32));
1308
-		ecc_offset_in_page =
1309
-			(chunk * (lt->data_bytes + lt->spare_bytes +
1310
-				  lt->ecc_bytes)) +
1311
-			(chunk < lt->full_chunk_cnt ?
1312
-			 lt->data_bytes + lt->spare_bytes :
1313
-			 lt->last_data_bytes + lt->last_spare_bytes);
1314
-		ecc_len = chunk < lt->full_chunk_cnt ?
1315
-			lt->ecc_bytes : lt->last_ecc_bytes;
1419
+		data_off_in_page = chunk * (lt->data_bytes + lt->spare_bytes +
1420
+					    lt->ecc_bytes);
1421
+		spare_off_in_page = data_off_in_page +
1422
+			(chunk < lt->full_chunk_cnt ? lt->data_bytes :
1423
+						      lt->last_data_bytes);
1424
+		ecc_off_in_page = spare_off_in_page +
1425
+			(chunk < lt->full_chunk_cnt ? lt->spare_bytes :
1426
+						      lt->last_spare_bytes);
13161427 
1317
-		/* Do the actual raw read of the ECC bytes */
1318
-		nand_change_read_column_op(chip, ecc_offset_in_page,
1319
-					   ecc, ecc_len, false);
1428
+		data_off = chunk * lt->data_bytes;
1429
+		spare_off = chunk * lt->spare_bytes;
1430
+		ecc_off = (lt->full_chunk_cnt * lt->spare_bytes) +
1431
+			  lt->last_spare_bytes +
1432
+			  (chunk * (lt->ecc_bytes + 2));
13201433 
1321
-		/* Derive data/spare bytes positions (in buffer) and length */
1322
-		data = buf + (chunk * lt->data_bytes);
1323
-		data_len = chunk < lt->full_chunk_cnt ?
1324
-			lt->data_bytes : lt->last_data_bytes;
1325
-		spare = chip->oob_poi + (chunk * (lt->spare_bytes +
1326
-						  lt->ecc_bytes));
1327
-		spare_len = chunk < lt->full_chunk_cnt ?
1328
-			lt->spare_bytes : lt->last_spare_bytes;
1434
+		data_len = chunk < lt->full_chunk_cnt ? lt->data_bytes :
1435
+							lt->last_data_bytes;
1436
+		spare_len = chunk < lt->full_chunk_cnt ? lt->spare_bytes :
1437
+							 lt->last_spare_bytes;
1438
+		ecc_len = chunk < lt->full_chunk_cnt ? lt->ecc_bytes :
1439
+						       lt->last_ecc_bytes;
1440
+
1441
+		/*
1442
+		 * Only re-read the ECC bytes, unless we are using the 2k/8b
1443
+		 * layout which is buggy in the sense that the ECC engine will
1444
+		 * try to correct data bytes anyway, creating bitflips. In this
1445
+		 * case, re-read the entire page.
1446
+		 */
1447
+		if (lt->writesize == 2048 && lt->strength == 8) {
1448
+			nand_change_read_column_op(chip, data_off_in_page,
1449
+						   buf + data_off, data_len,
1450
+						   false);
1451
+			nand_change_read_column_op(chip, spare_off_in_page,
1452
+						   chip->oob_poi + spare_off, spare_len,
1453
+						   false);
1454
+		}
1455
+
1456
+		nand_change_read_column_op(chip, ecc_off_in_page,
1457
+					   chip->oob_poi + ecc_off, ecc_len,
1458
+					   false);
13291459 
13301460 		/* Check the entire chunk (data + spare + ecc) for emptyness */
1331
-		marvell_nfc_check_empty_chunk(chip, data, data_len, spare,
1332
-					      spare_len, ecc, ecc_len,
1461
+		marvell_nfc_check_empty_chunk(chip, buf + data_off, data_len,
1462
+					      chip->oob_poi + spare_off, spare_len,
1463
+					      chip->oob_poi + ecc_off, ecc_len,
13331464 					      &max_bitflips);
13341465 	}
13351466 
13361467 	return max_bitflips;
13371468 }
13381469 
1339
-static int marvell_nfc_hw_ecc_bch_read_oob_raw(struct mtd_info *mtd,
1340
-					       struct nand_chip *chip, int page)
1470
+static int marvell_nfc_hw_ecc_bch_read_oob_raw(struct nand_chip *chip, int page)
13411471 {
1342
-	/* Invalidate page cache */
1343
-	chip->pagebuf = -1;
1472
+	u8 *buf = nand_get_data_buf(chip);
13441473 
1345
-	return chip->ecc.read_page_raw(mtd, chip, chip->data_buf, true, page);
1474
+	return chip->ecc.read_page_raw(chip, buf, true, page);
13461475 }
13471476 
1348
-static int marvell_nfc_hw_ecc_bch_read_oob(struct mtd_info *mtd,
1349
-					   struct nand_chip *chip, int page)
1477
+static int marvell_nfc_hw_ecc_bch_read_oob(struct nand_chip *chip, int page)
13501478 {
1351
-	/* Invalidate page cache */
1352
-	chip->pagebuf = -1;
1479
+	u8 *buf = nand_get_data_buf(chip);
13531480 
1354
-	return chip->ecc.read_page(mtd, chip, chip->data_buf, true, page);
1481
+	return chip->ecc.read_page(chip, buf, true, page);
13551482 }
13561483 
13571484 /* BCH write helpers */
1358
-static int marvell_nfc_hw_ecc_bch_write_page_raw(struct mtd_info *mtd,
1359
-						 struct nand_chip *chip,
1485
+static int marvell_nfc_hw_ecc_bch_write_page_raw(struct nand_chip *chip,
13601486 						 const u8 *buf,
13611487 						 int oob_required, int page)
13621488 {
....@@ -1369,6 +1495,8 @@
13691495 	int ecc_offset = (lt->full_chunk_cnt * lt->spare_bytes) +
13701496 		lt->last_spare_bytes;
13711497 	int chunk;
1498
+
1499
+	marvell_nfc_select_target(chip, chip->cur_cs);
13721500 
13731501 	nand_prog_page_begin_op(chip, page, 0, NULL, 0);
13741502 
....@@ -1469,17 +1597,21 @@
14691597 	return 0;
14701598 }
14711599 
1472
-static int marvell_nfc_hw_ecc_bch_write_page(struct mtd_info *mtd,
1473
-					     struct nand_chip *chip,
1600
+static int marvell_nfc_hw_ecc_bch_write_page(struct nand_chip *chip,
14741601 					     const u8 *buf,
14751602 					     int oob_required, int page)
14761603 {
1604
+	const struct nand_sdr_timings *sdr =
1605
+		nand_get_sdr_timings(nand_get_interface_config(chip));
1606
+	struct mtd_info *mtd = nand_to_mtd(chip);
14771607 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
14781608 	const u8 *data = buf;
14791609 	const u8 *spare = chip->oob_poi;
14801610 	int data_len = lt->data_bytes;
14811611 	int spare_len = lt->spare_bytes;
14821612 	int chunk, ret;
1613
+
1614
+	marvell_nfc_select_target(chip, chip->cur_cs);
14831615 
14841616 	/* Spare data will be written anyway, so clear it to avoid garbage */
14851617 	if (!oob_required)
....@@ -1507,8 +1639,7 @@
15071639 		marvell_nfc_wait_ndrun(chip);
15081640 	}
15091641 
1510
-	ret = marvell_nfc_wait_op(chip,
1511
-				  PSEC_TO_MSEC(chip->data_interface.timings.sdr.tPROG_max));
1642
+	ret = marvell_nfc_wait_op(chip, PSEC_TO_MSEC(sdr->tPROG_max));
15121643 
15131644 	marvell_nfc_disable_hw_ecc(chip);
15141645 
....@@ -1518,27 +1649,25 @@
15181649 	return 0;
15191650 }
15201651 
1521
-static int marvell_nfc_hw_ecc_bch_write_oob_raw(struct mtd_info *mtd,
1522
-						struct nand_chip *chip,
1652
+static int marvell_nfc_hw_ecc_bch_write_oob_raw(struct nand_chip *chip,
15231653 						int page)
15241654 {
1525
-	/* Invalidate page cache */
1526
-	chip->pagebuf = -1;
1655
+	struct mtd_info *mtd = nand_to_mtd(chip);
1656
+	u8 *buf = nand_get_data_buf(chip);
15271657 
1528
-	memset(chip->data_buf, 0xFF, mtd->writesize);
1658
+	memset(buf, 0xFF, mtd->writesize);
15291659 
1530
-	return chip->ecc.write_page_raw(mtd, chip, chip->data_buf, true, page);
1660
+	return chip->ecc.write_page_raw(chip, buf, true, page);
15311661 }
15321662 
1533
-static int marvell_nfc_hw_ecc_bch_write_oob(struct mtd_info *mtd,
1534
-					    struct nand_chip *chip, int page)
1663
+static int marvell_nfc_hw_ecc_bch_write_oob(struct nand_chip *chip, int page)
15351664 {
1536
-	/* Invalidate page cache */
1537
-	chip->pagebuf = -1;
1665
+	struct mtd_info *mtd = nand_to_mtd(chip);
1666
+	u8 *buf = nand_get_data_buf(chip);
15381667 
1539
-	memset(chip->data_buf, 0xFF, mtd->writesize);
1668
+	memset(buf, 0xFF, mtd->writesize);
15401669 
1541
-	return chip->ecc.write_page(mtd, chip, chip->data_buf, true, page);
1670
+	return chip->ecc.write_page(chip, buf, true, page);
15421671 }
15431672 
15441673 /* NAND framework ->exec_op() hooks and related helpers */
....@@ -2017,6 +2146,9 @@
20172146 {
20182147 	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
20192148 
2149
+	if (!check_only)
2150
+		marvell_nfc_select_target(chip, op->cs);
2151
+
20202152 	if (nfc->caps->is_nfcv2)
20212153 		return nand_op_parser_exec_op(chip, &marvell_nfcv2_op_parser,
20222154 					      op, check_only);
....@@ -2074,8 +2206,8 @@
20742206 	.free = marvell_nand_ooblayout_free,
20752207 };
20762208 
2077
-static int marvell_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
2078
-					 struct nand_ecc_ctrl *ecc)
2209
+static int marvell_nand_hw_ecc_controller_init(struct mtd_info *mtd,
2210
+					       struct nand_ecc_ctrl *ecc)
20792211 {
20802212 	struct nand_chip *chip = mtd_to_nand(mtd);
20812213 	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
....@@ -2108,12 +2240,22 @@
21082240 		return -ENOTSUPP;
21092241 	}
21102242 
2243
+	/* Special care for the layout 2k/8-bit/512B  */
2244
+	if (l->writesize == 2048 && l->strength == 8) {
2245
+		if (mtd->oobsize < 128) {
2246
+			dev_err(nfc->dev, "Requested layout needs at least 128 OOB bytes\n");
2247
+			return -ENOTSUPP;
2248
+		} else {
2249
+			chip->bbt_options |= NAND_BBT_NO_OOB_BBM;
2250
+		}
2251
+	}
2252
+
21112253 	mtd_set_ooblayout(mtd, &marvell_nand_ooblayout_ops);
21122254 	ecc->steps = l->nchunks;
21132255 	ecc->size = l->data_bytes;
21142256 
21152257 	if (ecc->strength == 1) {
2116
-		chip->ecc.algo = NAND_ECC_HAMMING;
2258
+		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
21172259 		ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw;
21182260 		ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page;
21192261 		ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw;
....@@ -2123,7 +2265,7 @@
21232265 		ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw;
21242266 		ecc->write_oob = ecc->write_oob_raw;
21252267 	} else {
2126
-		chip->ecc.algo = NAND_ECC_BCH;
2268
+		chip->ecc.algo = NAND_ECC_ALGO_BCH;
21272269 		ecc->strength = 16;
21282270 		ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw;
21292271 		ecc->read_page = marvell_nfc_hw_ecc_bch_read_page;
....@@ -2142,13 +2284,16 @@
21422284 				 struct nand_ecc_ctrl *ecc)
21432285 {
21442286 	struct nand_chip *chip = mtd_to_nand(mtd);
2287
+	const struct nand_ecc_props *requirements =
2288
+		nanddev_get_ecc_requirements(&chip->base);
21452289 	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
21462290 	int ret;
21472291 
2148
-	if (ecc->mode != NAND_ECC_NONE && (!ecc->size || !ecc->strength)) {
2149
-		if (chip->ecc_step_ds && chip->ecc_strength_ds) {
2150
-			ecc->size = chip->ecc_step_ds;
2151
-			ecc->strength = chip->ecc_strength_ds;
2292
+	if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_NONE &&
2293
+	    (!ecc->size || !ecc->strength)) {
2294
+		if (requirements->step_size && requirements->strength) {
2295
+			ecc->size = requirements->step_size;
2296
+			ecc->strength = requirements->strength;
21522297 		} else {
21532298 			dev_info(nfc->dev,
21542299 				 "No minimum ECC strength, using 1b/512B\n");
....@@ -2157,15 +2302,15 @@
21572302 		}
21582303 	}
21592304 
2160
-	switch (ecc->mode) {
2161
-	case NAND_ECC_HW:
2162
-		ret = marvell_nand_hw_ecc_ctrl_init(mtd, ecc);
2305
+	switch (ecc->engine_type) {
2306
+	case NAND_ECC_ENGINE_TYPE_ON_HOST:
2307
+		ret = marvell_nand_hw_ecc_controller_init(mtd, ecc);
21632308 		if (ret)
21642309 			return ret;
21652310 		break;
2166
-	case NAND_ECC_NONE:
2167
-	case NAND_ECC_SOFT:
2168
-	case NAND_ECC_ON_DIE:
2311
+	case NAND_ECC_ENGINE_TYPE_NONE:
2312
+	case NAND_ECC_ENGINE_TYPE_SOFT:
2313
+	case NAND_ECC_ENGINE_TYPE_ON_DIE:
21692314 		if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 &&
21702315 		    mtd->writesize != SZ_2K) {
21712316 			dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n",
....@@ -2203,11 +2348,9 @@
22032348 	.pattern = bbt_mirror_pattern
22042349 };
22052350 
2206
-static int marvell_nfc_setup_data_interface(struct mtd_info *mtd, int chipnr,
2207
-					    const struct nand_data_interface
2208
-					    *conf)
2351
+static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr,
2352
+				       const struct nand_interface_config *conf)
22092353 {
2210
-	struct nand_chip *chip = mtd_to_nand(mtd);
22112354 	struct marvell_nand_chip *marvell_nand = to_marvell_nand(chip);
22122355 	struct marvell_nfc *nfc = to_marvell_nfc(chip->controller);
22132356 	unsigned int period_ns = 1000000000 / clk_get_rate(nfc->core_clk) * 2;
....@@ -2364,7 +2507,7 @@
23642507 		return ret;
23652508 	}
23662509 
2367
-	if (chip->ecc.mode == NAND_ECC_HW) {
2510
+	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
23682511 		/*
23692512 		 * Subpage write not available with hardware ECC, prohibit also
23702513 		 * subpage read as in userspace subpage access would still be
....@@ -2406,6 +2549,8 @@
24062549 
24072550 static const struct nand_controller_ops marvell_nand_controller_ops = {
24082551 	.attach_chip = marvell_nand_attach_chip,
2552
+	.exec_op = marvell_nfc_exec_op,
2553
+	.setup_interface = marvell_nfc_setup_interface,
24092554 };
24102555 
24112556 static int marvell_nand_chip_init(struct device *dev, struct marvell_nfc *nfc,
....@@ -2438,9 +2583,8 @@
24382583 	}
24392584 
24402585 	/* Alloc the nand chip structure */
2441
-	marvell_nand = devm_kzalloc(dev, sizeof(*marvell_nand) +
2442
-				    (nsels *
2443
-				     sizeof(struct marvell_nand_chip_sel)),
2586
+	marvell_nand = devm_kzalloc(dev,
2587
+				    struct_size(marvell_nand, sels, nsels),
24442588 				    GFP_KERNEL);
24452589 	if (!marvell_nand) {
24462590 		dev_err(dev, "could not allocate chip structure\n");
....@@ -2528,10 +2672,8 @@
25282672 	chip->controller = &nfc->controller;
25292673 	nand_set_flash_node(chip, np);
25302674 
2531
-	chip->exec_op = marvell_nfc_exec_op;
2532
-	chip->select_chip = marvell_nfc_select_chip;
2533
-	if (!of_property_read_bool(np, "marvell,nand-keep-config"))
2534
-		chip->setup_data_interface = marvell_nfc_setup_data_interface;
2675
+	if (of_property_read_bool(np, "marvell,nand-keep-config"))
2676
+		chip->options |= NAND_KEEP_TIMINGS;
25352677 
25362678 	mtd = nand_to_mtd(chip);
25372679 	mtd->dev.parent = dev;
....@@ -2540,11 +2682,11 @@
25402682 	 * Default to HW ECC engine mode. If the nand-ecc-mode property is given
25412683 	 * in the DT node, this entry will be overwritten in nand_scan_ident().
25422684 	 */
2543
-	chip->ecc.mode = NAND_ECC_HW;
2685
+	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
25442686 
25452687 	/*
25462688 	 * Save a reference value for timing registers before
2547
-	 * ->setup_data_interface() is called.
2689
+	 * ->setup_interface() is called.
25482690 	 */
25492691 	marvell_nand->ndtr0 = readl_relaxed(nfc->regs + NDTR0);
25502692 	marvell_nand->ndtr1 = readl_relaxed(nfc->regs + NDTR1);
....@@ -2576,9 +2718,14 @@
25762718 static void marvell_nand_chips_cleanup(struct marvell_nfc *nfc)
25772719 {
25782720 	struct marvell_nand_chip *entry, *temp;
2721
+	struct nand_chip *chip;
2722
+	int ret;
25792723 
25802724 	list_for_each_entry_safe(entry, temp, &nfc->chips, node) {
2581
-		nand_release(&entry->chip);
2725
+		chip = &entry->chip;
2726
+		ret = mtd_device_unregister(nand_to_mtd(chip));
2727
+		WARN_ON(ret);
2728
+		nand_cleanup(chip);
25822729 		list_del(&entry->node);
25832730 	}
25842731 }
....@@ -2648,16 +2795,18 @@
26482795 	if (ret)
26492796 		return ret;
26502797 
2651
-	nfc->dma_chan =	dma_request_slave_channel(nfc->dev, "data");
2652
-	if (!nfc->dma_chan) {
2653
-		dev_err(nfc->dev,
2654
-			"Unable to request data DMA channel\n");
2655
-		return -ENODEV;
2798
+	nfc->dma_chan =	dma_request_chan(nfc->dev, "data");
2799
+	if (IS_ERR(nfc->dma_chan)) {
2800
+		ret = PTR_ERR(nfc->dma_chan);
2801
+		nfc->dma_chan = NULL;
2802
+		return dev_err_probe(nfc->dev, ret, "DMA channel request failed\n");
26562803 	}
26572804 
26582805 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2659
-	if (!r)
2660
-		return -ENXIO;
2806
+	if (!r) {
2807
+		ret = -ENXIO;
2808
+		goto release_channel;
2809
+	}
26612810 
26622811 	config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
26632812 	config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
....@@ -2668,7 +2817,7 @@
26682817 	ret = dmaengine_slave_config(nfc->dma_chan, &config);
26692818 	if (ret < 0) {
26702819 		dev_err(nfc->dev, "Failed to configure DMA channel\n");
2671
-		return ret;
2820
+		goto release_channel;
26722821 	}
26732822 
26742823 	/*
....@@ -2678,12 +2827,20 @@
26782827 	 * the provided buffer.
26792828 	 */
26802829 	nfc->dma_buf = kmalloc(MAX_CHUNK_SIZE, GFP_KERNEL | GFP_DMA);
2681
-	if (!nfc->dma_buf)
2682
-		return -ENOMEM;
2830
+	if (!nfc->dma_buf) {
2831
+		ret = -ENOMEM;
2832
+		goto release_channel;
2833
+	}
26832834 
26842835 	nfc->use_dma = true;
26852836 
26862837 	return 0;
2838
+
2839
+release_channel:
2840
+	dma_release_channel(nfc->dma_chan);
2841
+	nfc->dma_chan = NULL;
2842
+
2843
+	return ret;
26872844 }
26882845 
26892846 static void marvell_nfc_reset(struct marvell_nfc *nfc)
....@@ -2746,7 +2903,6 @@
27462903 static int marvell_nfc_probe(struct platform_device *pdev)
27472904 {
27482905 	struct device *dev = &pdev->dev;
2749
-	struct resource *r;
27502906 	struct marvell_nfc *nfc;
27512907 	int ret;
27522908 	int irq;
....@@ -2761,16 +2917,13 @@
27612917 	nfc->controller.ops = &marvell_nand_controller_ops;
27622918 	INIT_LIST_HEAD(&nfc->chips);
27632919 
2764
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2765
-	nfc->regs = devm_ioremap_resource(dev, r);
2920
+	nfc->regs = devm_platform_ioremap_resource(pdev, 0);
27662921 	if (IS_ERR(nfc->regs))
27672922 		return PTR_ERR(nfc->regs);
27682923 
27692924 	irq = platform_get_irq(pdev, 0);
2770
-	if (irq < 0) {
2771
-		dev_err(dev, "failed to retrieve irq\n");
2925
+	if (irq < 0)
27722926 		return irq;
2773
-	}
27742927 
27752928 	nfc->core_clk = devm_clk_get(&pdev->dev, "core");
27762929 
....@@ -2827,10 +2980,13 @@
28272980 
28282981 	ret = marvell_nand_chips_init(dev, nfc);
28292982 	if (ret)
2830
-		goto unprepare_reg_clk;
2983
+		goto release_dma;
28312984 
28322985 	return 0;
28332986 
2987
+release_dma:
2988
+	if (nfc->use_dma)
2989
+		dma_release_channel(nfc->dma_chan);
28342990 unprepare_reg_clk:
28352991 	clk_disable_unprepare(nfc->reg_clk);
28362992 unprepare_core_clk:
....@@ -2887,7 +3043,7 @@
28873043 
28883044 	/*
28893045 	 * Reset nfc->selected_chip so the next command will cause the timing
2890
-	 * registers to be restored in marvell_nfc_select_chip().
3046
+	 * registers to be restored in marvell_nfc_select_target().
28913047 	 */
28923048 	nfc->selected_chip = NULL;
28933049