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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/mtd/nand/raw/lpc32xx_slc.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * NXP LPC32XX NAND SLC driver
34  *
....@@ -7,16 +8,6 @@
78  *
89  * Copyright © 2011 NXP Semiconductors
910  * Copyright © 2012 Roland Stigge
10
- *
11
- * This program is free software; you can redistribute it and/or modify
12
- * it under the terms of the GNU General Public License as published by
13
- * the Free Software Foundation; either version 2 of the License, or
14
- * (at your option) any later version.
15
- *
16
- * This program is distributed in the hope that it will be useful,
17
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
18
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19
- * GNU General Public License for more details.
2011  */
2112 
2213 #include <linux/slab.h>
....@@ -278,11 +269,10 @@
278269 /*
279270  * Hardware specific access to control lines
280271  */
281
-static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
282
-	unsigned int ctrl)
272
+static void lpc32xx_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
273
+				  unsigned int ctrl)
283274 {
284275 	uint32_t tmp;
285
-	struct nand_chip *chip = mtd_to_nand(mtd);
286276 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
287277 
288278 	/* Does CE state need to be changed? */
....@@ -304,9 +294,8 @@
304294 /*
305295  * Read the Device Ready pin
306296  */
307
-static int lpc32xx_nand_device_ready(struct mtd_info *mtd)
297
+static int lpc32xx_nand_device_ready(struct nand_chip *chip)
308298 {
309
-	struct nand_chip *chip = mtd_to_nand(mtd);
310299 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
311300 	int rdy = 0;
312301 
....@@ -337,7 +326,7 @@
337326 /*
338327  * Prepares SLC for transfers with H/W ECC enabled
339328  */
340
-static void lpc32xx_nand_ecc_enable(struct mtd_info *mtd, int mode)
329
+static void lpc32xx_nand_ecc_enable(struct nand_chip *chip, int mode)
341330 {
342331 	/* Hardware ECC is enabled automatically in hardware as needed */
343332 }
....@@ -345,7 +334,7 @@
345334 /*
346335  * Calculates the ECC for the data
347336  */
348
-static int lpc32xx_nand_ecc_calculate(struct mtd_info *mtd,
337
+static int lpc32xx_nand_ecc_calculate(struct nand_chip *chip,
349338 				      const unsigned char *buf,
350339 				      unsigned char *code)
351340 {
....@@ -359,9 +348,8 @@
359348 /*
360349  * Read a single byte from NAND device
361350  */
362
-static uint8_t lpc32xx_nand_read_byte(struct mtd_info *mtd)
351
+static uint8_t lpc32xx_nand_read_byte(struct nand_chip *chip)
363352 {
364
-	struct nand_chip *chip = mtd_to_nand(mtd);
365353 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
366354 
367355 	return (uint8_t)readl(SLC_DATA(host->io_base));
....@@ -370,9 +358,8 @@
370358 /*
371359  * Simple device read without ECC
372360  */
373
-static void lpc32xx_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
361
+static void lpc32xx_nand_read_buf(struct nand_chip *chip, u_char *buf, int len)
374362 {
375
-	struct nand_chip *chip = mtd_to_nand(mtd);
376363 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
377364 
378365 	/* Direct device read with no ECC */
....@@ -383,9 +370,9 @@
383370 /*
384371  * Simple device write without ECC
385372  */
386
-static void lpc32xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
373
+static void lpc32xx_nand_write_buf(struct nand_chip *chip, const uint8_t *buf,
374
+				   int len)
387375 {
388
-	struct nand_chip *chip = mtd_to_nand(mtd);
389376 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
390377 
391378 	/* Direct device write with no ECC */
....@@ -396,18 +383,20 @@
396383 /*
397384  * Read the OOB data from the device without ECC using FIFO method
398385  */
399
-static int lpc32xx_nand_read_oob_syndrome(struct mtd_info *mtd,
400
-					  struct nand_chip *chip, int page)
386
+static int lpc32xx_nand_read_oob_syndrome(struct nand_chip *chip, int page)
401387 {
388
+	struct mtd_info *mtd = nand_to_mtd(chip);
389
+
402390 	return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
403391 }
404392 
405393 /*
406394  * Write the OOB data to the device without ECC using FIFO method
407395  */
408
-static int lpc32xx_nand_write_oob_syndrome(struct mtd_info *mtd,
409
-	struct nand_chip *chip, int page)
396
+static int lpc32xx_nand_write_oob_syndrome(struct nand_chip *chip, int page)
410397 {
398
+	struct mtd_info *mtd = nand_to_mtd(chip);
399
+
411400 	return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
412401 				 mtd->oobsize);
413402 }
....@@ -610,10 +599,10 @@
610599  * Read the data and OOB data from the device, use ECC correction with the
611600  * data, disable ECC for the OOB data
612601  */
613
-static int lpc32xx_nand_read_page_syndrome(struct mtd_info *mtd,
614
-					   struct nand_chip *chip, uint8_t *buf,
602
+static int lpc32xx_nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf,
615603 					   int oob_required, int page)
616604 {
605
+	struct mtd_info *mtd = nand_to_mtd(chip);
617606 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
618607 	struct mtd_oob_region oobregion = { };
619608 	int stat, i, status, error;
....@@ -626,7 +615,7 @@
626615 	status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1);
627616 
628617 	/* Get OOB data */
629
-	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
618
+	chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
630619 
631620 	/* Convert to stored ECC format */
632621 	lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);
....@@ -639,7 +628,7 @@
639628 	oobecc = chip->oob_poi + oobregion.offset;
640629 
641630 	for (i = 0; i < chip->ecc.steps; i++) {
642
-		stat = chip->ecc.correct(mtd, buf, oobecc,
631
+		stat = chip->ecc.correct(chip, buf, oobecc,
643632 					 &tmpecc[i * chip->ecc.bytes]);
644633 		if (stat < 0)
645634 			mtd->ecc_stats.failed++;
....@@ -657,17 +646,18 @@
657646  * Read the data and OOB data from the device, no ECC correction with the
658647  * data or OOB data
659648  */
660
-static int lpc32xx_nand_read_page_raw_syndrome(struct mtd_info *mtd,
661
-					       struct nand_chip *chip,
649
+static int lpc32xx_nand_read_page_raw_syndrome(struct nand_chip *chip,
662650 					       uint8_t *buf, int oob_required,
663651 					       int page)
664652 {
653
+	struct mtd_info *mtd = nand_to_mtd(chip);
654
+
665655 	/* Issue read command */
666656 	nand_read_page_op(chip, page, 0, NULL, 0);
667657 
668658 	/* Raw reads can just use the FIFO interface */
669
-	chip->read_buf(mtd, buf, chip->ecc.size * chip->ecc.steps);
670
-	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
659
+	chip->legacy.read_buf(chip, buf, chip->ecc.size * chip->ecc.steps);
660
+	chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
671661 
672662 	return 0;
673663 }
....@@ -676,11 +666,11 @@
676666  * Write the data and OOB data to the device, use ECC with the data,
677667  * disable ECC for the OOB data
678668  */
679
-static int lpc32xx_nand_write_page_syndrome(struct mtd_info *mtd,
680
-					    struct nand_chip *chip,
669
+static int lpc32xx_nand_write_page_syndrome(struct nand_chip *chip,
681670 					    const uint8_t *buf,
682671 					    int oob_required, int page)
683672 {
673
+	struct mtd_info *mtd = nand_to_mtd(chip);
684674 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
685675 	struct mtd_oob_region oobregion = { };
686676 	uint8_t *pb;
....@@ -705,7 +695,7 @@
705695 	lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);
706696 
707697 	/* Write ECC data to device */
708
-	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
698
+	chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
709699 
710700 	return nand_prog_page_end_op(chip);
711701 }
....@@ -714,15 +704,16 @@
714704  * Write the data and OOB data to the device, no ECC correction with the
715705  * data or OOB data
716706  */
717
-static int lpc32xx_nand_write_page_raw_syndrome(struct mtd_info *mtd,
718
-						struct nand_chip *chip,
707
+static int lpc32xx_nand_write_page_raw_syndrome(struct nand_chip *chip,
719708 						const uint8_t *buf,
720709 						int oob_required, int page)
721710 {
711
+	struct mtd_info *mtd = nand_to_mtd(chip);
712
+
722713 	/* Raw writes can just use the FIFO interface */
723714 	nand_prog_page_begin_op(chip, page, 0, buf,
724715 				chip->ecc.size * chip->ecc.steps);
725
-	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
716
+	chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
726717 
727718 	return nand_prog_page_end_op(chip);
728719 }
....@@ -784,6 +775,9 @@
784775 	struct mtd_info *mtd = nand_to_mtd(chip);
785776 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
786777 
778
+	if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
779
+		return 0;
780
+
787781 	/* OOB and ECC CPU and DMA work areas */
788782 	host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE);
789783 
....@@ -795,11 +789,22 @@
795789 	if (mtd->writesize <= 512)
796790 		mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
797791 
792
+	chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
798793 	/* These sizes remain the same regardless of page size */
799794 	chip->ecc.size = 256;
795
+	chip->ecc.strength = 1;
800796 	chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
801797 	chip->ecc.prepad = 0;
802798 	chip->ecc.postpad = 0;
799
+	chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
800
+	chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
801
+	chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
802
+	chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
803
+	chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
804
+	chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
805
+	chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
806
+	chip->ecc.correct = nand_correct_data;
807
+	chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
803808 
804809 	/*
805810 	 * Use a custom BBT marker setup for small page FLASH that
....@@ -878,11 +883,11 @@
878883 		goto enable_wp;
879884 
880885 	/* Set NAND IO addresses and command/ready functions */
881
-	chip->IO_ADDR_R = SLC_DATA(host->io_base);
882
-	chip->IO_ADDR_W = SLC_DATA(host->io_base);
883
-	chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
884
-	chip->dev_ready = lpc32xx_nand_device_ready;
885
-	chip->chip_delay = 20; /* 20us command delay time */
886
+	chip->legacy.IO_ADDR_R = SLC_DATA(host->io_base);
887
+	chip->legacy.IO_ADDR_W = SLC_DATA(host->io_base);
888
+	chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
889
+	chip->legacy.dev_ready = lpc32xx_nand_device_ready;
890
+	chip->legacy.chip_delay = 20; /* 20us command delay time */
886891 
887892 	/* Init NAND controller */
888893 	lpc32xx_nand_setup(host);
....@@ -890,20 +895,9 @@
890895 	platform_set_drvdata(pdev, host);
891896 
892897 	/* NAND callbacks for LPC32xx SLC hardware */
893
-	chip->ecc.mode = NAND_ECC_HW_SYNDROME;
894
-	chip->read_byte = lpc32xx_nand_read_byte;
895
-	chip->read_buf = lpc32xx_nand_read_buf;
896
-	chip->write_buf = lpc32xx_nand_write_buf;
897
-	chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
898
-	chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
899
-	chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
900
-	chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
901
-	chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
902
-	chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
903
-	chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
904
-	chip->ecc.correct = nand_correct_data;
905
-	chip->ecc.strength = 1;
906
-	chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
898
+	chip->legacy.read_byte = lpc32xx_nand_read_byte;
899
+	chip->legacy.read_buf = lpc32xx_nand_read_buf;
900
+	chip->legacy.write_buf = lpc32xx_nand_write_buf;
907901 
908902 	/*
909903 	 * Allocate a large enough buffer for a single huge page plus
....@@ -924,7 +918,7 @@
924918 	}
925919 
926920 	/* Find NAND device */
927
-	chip->dummy_controller.ops = &lpc32xx_nand_controller_ops;
921
+	chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops;
928922 	res = nand_scan(chip, 1);
929923 	if (res)
930924 		goto release_dma;
....@@ -956,8 +950,12 @@
956950 {
957951 	uint32_t tmp;
958952 	struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
953
+	struct nand_chip *chip = &host->nand_chip;
954
+	int ret;
959955 
960
-	nand_release(&host->nand_chip);
956
+	ret = mtd_device_unregister(nand_to_mtd(chip));
957
+	WARN_ON(ret);
958
+	nand_cleanup(chip);
961959 	dma_release_channel(host->dma_chan);
962960 
963961 	/* Force CE high */