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2023-12-09 b22da3d8526a935aa31e086e63f60ff3246cb61c 
 kernel/drivers/mtd/nand/raw/fsl_ifc_nand.c
....@@ -1,23 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Freescale Integrated Flash Controller NAND driver
34  *
45  * Copyright 2011-2012 Freescale Semiconductor, Inc
56  *
67  * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; either version 2 of the License, or
11
- * (at your option) any later version.
12
- *
13
- * This program is distributed in the hope that it will be useful,
14
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
15
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
- * GNU General Public License for more details.
17
- *
18
- * You should have received a copy of the GNU General Public License
19
- * along with this program; if not, write to the Free Software
20
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
218  */
229 
2310 #include <linux/module.h>
....@@ -301,9 +288,9 @@
301288 }
302289 
303290 /* cmdfunc send commands to the IFC NAND Machine */
304
-static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
305
-			     int column, int page_addr) {
306
-	struct nand_chip *chip = mtd_to_nand(mtd);
291
+static void fsl_ifc_cmdfunc(struct nand_chip *chip, unsigned int command,
292
+			    int column, int page_addr) {
293
+	struct mtd_info *mtd = nand_to_mtd(chip);
307294 	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
308295 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
309296 	struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
....@@ -322,7 +309,7 @@
322309 		ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
323310 		ifc_nand_ctrl->index += column;
324311 
325
-		if (chip->ecc.mode == NAND_ECC_HW)
312
+		if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
326313 			ifc_nand_ctrl->eccread = 1;
327314 
328315 		fsl_ifc_do_read(chip, 0, mtd);
....@@ -509,7 +496,7 @@
509496 	}
510497 }
511498 
512
-static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
499
+static void fsl_ifc_select_chip(struct nand_chip *chip, int cs)
513500 {
514501 	/* The hardware does not seem to support multiple
515502 	 * chips per bank.
....@@ -519,9 +506,9 @@
519506 /*
520507  * Write buf to the IFC NAND Controller Data Buffer
521508  */
522
-static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
509
+static void fsl_ifc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
523510 {
524
-	struct nand_chip *chip = mtd_to_nand(mtd);
511
+	struct mtd_info *mtd = nand_to_mtd(chip);
525512 	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
526513 	unsigned int bufsize = mtd->writesize + mtd->oobsize;
527514 
....@@ -545,9 +532,8 @@
545532  * Read a byte from either the IFC hardware buffer
546533  * read function for 8-bit buswidth
547534  */
548
-static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
535
+static uint8_t fsl_ifc_read_byte(struct nand_chip *chip)
549536 {
550
-	struct nand_chip *chip = mtd_to_nand(mtd);
551537 	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
552538 	unsigned int offset;
553539 
....@@ -568,9 +554,8 @@
568554  * Read two bytes from the IFC hardware buffer
569555  * read function for 16-bit buswith
570556  */
571
-static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
557
+static uint8_t fsl_ifc_read_byte16(struct nand_chip *chip)
572558 {
573
-	struct nand_chip *chip = mtd_to_nand(mtd);
574559 	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
575560 	uint16_t data;
576561 
....@@ -591,9 +576,8 @@
591576 /*
592577  * Read from the IFC Controller Data Buffer
593578  */
594
-static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
579
+static void fsl_ifc_read_buf(struct nand_chip *chip, u8 *buf, int len)
595580 {
596
-	struct nand_chip *chip = mtd_to_nand(mtd);
597581 	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
598582 	int avail;
599583 
....@@ -617,8 +601,9 @@
617601  * This function is called after Program and Erase Operations to
618602  * check for success or failure.
619603  */
620
-static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
604
+static int fsl_ifc_wait(struct nand_chip *chip)
621605 {
606
+	struct mtd_info *mtd = nand_to_mtd(chip);
622607 	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
623608 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
624609 	struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
....@@ -679,20 +664,21 @@
679664 	return bitflips;
680665 }
681666 
682
-static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
683
-			     uint8_t *buf, int oob_required, int page)
667
+static int fsl_ifc_read_page(struct nand_chip *chip, uint8_t *buf,
668
+			     int oob_required, int page)
684669 {
670
+	struct mtd_info *mtd = nand_to_mtd(chip);
685671 	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
686672 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
687673 	struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
688674 
689675 	nand_read_page_op(chip, page, 0, buf, mtd->writesize);
690676 	if (oob_required)
691
-		fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
677
+		fsl_ifc_read_buf(chip, chip->oob_poi, mtd->oobsize);
692678 
693679 	if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) {
694680 		if (!oob_required)
695
-			fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
681
+			fsl_ifc_read_buf(chip, chip->oob_poi, mtd->oobsize);
696682 
697683 		return check_erased_page(chip, buf);
698684 	}
....@@ -706,11 +692,13 @@
706692 /* ECC will be calculated automatically, and errors will be detected in
707693  * waitfunc.
708694  */
709
-static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
710
-			       const uint8_t *buf, int oob_required, int page)
695
+static int fsl_ifc_write_page(struct nand_chip *chip, const uint8_t *buf,
696
+			      int oob_required, int page)
711697 {
698
+	struct mtd_info *mtd = nand_to_mtd(chip);
699
+
712700 	nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
713
-	fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
701
+	fsl_ifc_write_buf(chip, chip->oob_poi, mtd->oobsize);
714702 
715703 	return nand_prog_page_end_op(chip);
716704 }
....@@ -719,15 +707,39 @@
719707 {
720708 	struct mtd_info *mtd = nand_to_mtd(chip);
721709 	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
710
+	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
711
+	struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
712
+	u32 csor;
713
+
714
+	csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
715
+
716
+	/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
717
+	if (csor & CSOR_NAND_ECC_DEC_EN) {
718
+		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
719
+		mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
720
+
721
+		/* Hardware generates ECC per 512 Bytes */
722
+		chip->ecc.size = 512;
723
+		if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
724
+			chip->ecc.bytes = 8;
725
+			chip->ecc.strength = 4;
726
+		} else {
727
+			chip->ecc.bytes = 16;
728
+			chip->ecc.strength = 8;
729
+		}
730
+	} else {
731
+		chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
732
+		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
733
+	}
722734 
723735 	dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
724
-							chip->numchips);
736
+		nanddev_ntargets(&chip->base));
725737 	dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
726
-							chip->chipsize);
738
+	        nanddev_target_size(&chip->base));
727739 	dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
728740 							chip->pagemask);
729
-	dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
730
-							chip->chip_delay);
741
+	dev_dbg(priv->dev, "%s: nand->legacy.chip_delay = %d\n", __func__,
742
+		chip->legacy.chip_delay);
731743 	dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
732744 							chip->badblockpos);
733745 	dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
....@@ -736,8 +748,8 @@
736748 							chip->page_shift);
737749 	dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
738750 							chip->phys_erase_shift);
739
-	dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
740
-							chip->ecc.mode);
751
+	dev_dbg(priv->dev, "%s: nand->ecc.engine_type = %d\n", __func__,
752
+							chip->ecc.engine_type);
741753 	dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
742754 							chip->ecc.steps);
743755 	dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
....@@ -857,17 +869,17 @@
857869 	/* set up function call table */
858870 	if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
859871 		& CSPR_PORT_SIZE_16)
860
-		chip->read_byte = fsl_ifc_read_byte16;
872
+		chip->legacy.read_byte = fsl_ifc_read_byte16;
861873 	else
862
-		chip->read_byte = fsl_ifc_read_byte;
874
+		chip->legacy.read_byte = fsl_ifc_read_byte;
863875 
864
-	chip->write_buf = fsl_ifc_write_buf;
865
-	chip->read_buf = fsl_ifc_read_buf;
866
-	chip->select_chip = fsl_ifc_select_chip;
867
-	chip->cmdfunc = fsl_ifc_cmdfunc;
868
-	chip->waitfunc = fsl_ifc_wait;
869
-	chip->set_features = nand_get_set_features_notsupp;
870
-	chip->get_features = nand_get_set_features_notsupp;
876
+	chip->legacy.write_buf = fsl_ifc_write_buf;
877
+	chip->legacy.read_buf = fsl_ifc_read_buf;
878
+	chip->legacy.select_chip = fsl_ifc_select_chip;
879
+	chip->legacy.cmdfunc = fsl_ifc_cmdfunc;
880
+	chip->legacy.waitfunc = fsl_ifc_wait;
881
+	chip->legacy.set_features = nand_get_set_features_notsupp;
882
+	chip->legacy.get_features = nand_get_set_features_notsupp;
871883 
872884 	chip->bbt_td = &bbt_main_descr;
873885 	chip->bbt_md = &bbt_mirror_descr;
....@@ -880,10 +892,10 @@
880892 
881893 	if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
882894 		& CSPR_PORT_SIZE_16) {
883
-		chip->read_byte = fsl_ifc_read_byte16;
895
+		chip->legacy.read_byte = fsl_ifc_read_byte16;
884896 		chip->options |= NAND_BUSWIDTH_16;
885897 	} else {
886
-		chip->read_byte = fsl_ifc_read_byte;
898
+		chip->legacy.read_byte = fsl_ifc_read_byte;
887899 	}
888900 
889901 	chip->controller = &ifc_nand_ctrl->controller;
....@@ -920,25 +932,6 @@
920932 	default:
921933 		dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
922934 		return -ENODEV;
923
-	}
924
-
925
-	/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
926
-	if (csor & CSOR_NAND_ECC_DEC_EN) {
927
-		chip->ecc.mode = NAND_ECC_HW;
928
-		mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
929
-
930
-		/* Hardware generates ECC per 512 Bytes */
931
-		chip->ecc.size = 512;
932
-		if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
933
-			chip->ecc.bytes = 8;
934
-			chip->ecc.strength = 4;
935
-		} else {
936
-			chip->ecc.bytes = 16;
937
-			chip->ecc.strength = 8;
938
-		}
939
-	} else {
940
-		chip->ecc.mode = NAND_ECC_SOFT;
941
-		chip->ecc.algo = NAND_ECC_HAMMING;
942935 	}
943936 
944937 	ret = fsl_ifc_sram_init(priv);
....@@ -1105,8 +1098,13 @@
11051098 static int fsl_ifc_nand_remove(struct platform_device *dev)
11061099 {
11071100 	struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1101
+	struct nand_chip *chip = &priv->chip;
1102
+	int ret;
11081103 
1109
-	nand_release(&priv->chip);
1104
+	ret = mtd_device_unregister(nand_to_mtd(chip));
1105
+	WARN_ON(ret);
1106
+	nand_cleanup(chip);
1107
+
11101108 	fsl_ifc_chip_remove(priv);
11111109 
11121110 	mutex_lock(&fsl_ifc_nand_mutex);